Lines Matching +full:0 +full:x12345678
19 #define CW1200_CUT_11_ID_STR (0x302E3830)
20 #define CW1200_CUT_22_ID_STR1 (0x302e3132)
21 #define CW1200_CUT_22_ID_STR2 (0x32302e30)
22 #define CW1200_CUT_22_ID_STR3 (0x3335)
23 #define CW1200_CUT_ID_ADDR (0xFFF17F90)
24 #define CW1200_CUT2_ID_ADDR (0xFFF1FF90)
28 #define DOWNLOAD_BOOT_LOADER_OFFSET (0x00000000)
29 /* 32K, 0x4000 to 0xDFFF */
30 #define DOWNLOAD_FIFO_OFFSET (0x00004000)
32 #define DOWNLOAD_FIFO_SIZE (0x00008000)
33 /* 128 bytes, 0xFF80 to 0xFFFF */
34 #define DOWNLOAD_CTRL_OFFSET (0x0000FF80)
73 #define DOWNLOAD_ARE_YOU_HERE (0x87654321)
74 #define DOWNLOAD_I_AM_HERE (0x12345678)
77 #define DOWNLOAD_PENDING (0xFFFFFFFF)
78 #define DOWNLOAD_SUCCESS (0)
91 #define SYS_BASE_ADDR_SILICON (0)
92 #define PAC_BASE_ADDRESS_SILICON (SYS_BASE_ADDR_SILICON + 0x09000000)
100 #define ST90TDS_ADDR_ID_BASE (0x0000)
102 #define ST90TDS_CONFIG_REG_ID (0x0000)
104 #define ST90TDS_CONTROL_REG_ID (0x0001)
106 #define ST90TDS_IN_OUT_QUEUE_REG_ID (0x0002)
108 #define ST90TDS_AHB_DPORT_REG_ID (0x0003)
110 #define ST90TDS_SRAM_BASE_ADDR_REG_ID (0x0004)
112 #define ST90TDS_SRAM_DPORT_REG_ID (0x0005)
114 #define ST90TDS_TSET_GEN_R_W_REG_ID (0x0006)
116 #define ST90TDS_FRAME_OUT_REG_ID (0x0007)
120 /* next o/p length, bit 11 to 0 */
121 #define ST90TDS_CONT_NEXT_LEN_MASK (0x0FFF)
172 *val = le32_to_cpu(tmp) & 0xfffff; in cw1200_reg_read_16()