Lines Matching +full:24 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
26 #define RTW89_TXWD_BODY0_WP_OFFSET GENMASK(31, 24)
27 #define RTW89_TXWD_BODY0_WP_OFFSET_V1 GENMASK(28, 24)
28 #define RTW89_TXWD_BODY0_MORE_DATA BIT(23)
29 #define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22)
30 #define RTW89_TXWD_BODY0_FW_DL BIT(20)
33 #define RTW89_TXWD_BODY0_WD_PAGE BIT(7)
34 #define RTW89_TXWD_BODY0_HW_AMSDU BIT(5)
45 #define RTW89_TXWD_BODY2_MACID GENMASK(30, 24)
46 #define RTW89_TXWD_BODY2_TID_INDICATE BIT(23)
51 #define RTW89_TXWD_BODY3_BK BIT(13)
52 #define RTW89_TXWD_BODY3_AGG_EN BIT(12)
56 #define RTW89_TXWD_BODY4_SEC_IV_L1 GENMASK(31, 24)
60 #define RTW89_TXWD_BODY5_SEC_IV_H5 GENMASK(31, 24)
68 #define RTW89_TXWD_BODY7_USE_RATE_V1 BIT(31)
71 #define RTW89_TXWD_BODY7_DATA_RATE GENMASK(24, 16)
74 #define RTW89_TXWD_INFO0_USE_RATE BIT(30)
77 #define RTW89_TXWD_INFO0_DATA_RATE GENMASK(24, 16)
78 #define RTW89_TXWD_INFO0_DISDATAFB BIT(10)
82 #define RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE GENMASK(24, 16)
83 #define RTW89_TXWD_INFO1_A_CTRL_BSR BIT(14)
89 #define RTW89_TXWD_INFO2_SEC_HW_ENC BIT(8)
90 #define RTW89_TXWD_INFO2_FORCE_KEY_EN BIT(8)
96 #define RTW89_TXWD_INFO4_RTS_EN BIT(27)
97 #define RTW89_TXWD_INFO4_HW_RTS_EN BIT(31)
105 #define AX_RXD_BB_SEL BIT(22)
106 #define AX_RXD_MAC_INFO_VLD BIT(23)
107 #define AX_RXD_RPKT_TYPE_MASK GENMASK(27, 24)
109 #define AX_RXD_LONG_RXD BIT(31)
114 #define AX_RXD_SR_EN BIT(7)
117 #define AX_RXD_RX_DATARATE_MASK GENMASK(24, 16)
119 #define AX_RXD_NON_SRG_PPDU BIT(28)
120 #define AX_RXD_INTER_PPDU BIT(29)
121 #define AX_RXD_NON_SRG_PPDU_v1 BIT(14)
122 #define AX_RXD_INTER_PPDU_v1 BIT(15)
130 #define AX_RXD_A1_MATCH BIT(0)
131 #define AX_RXD_SW_DEC BIT(1)
132 #define AX_RXD_HW_DEC BIT(2)
133 #define AX_RXD_AMPDU BIT(3)
134 #define AX_RXD_AMPDU_END_PKT BIT(4)
135 #define AX_RXD_AMSDU BIT(5)
136 #define AX_RXD_AMSDU_CUT BIT(6)
137 #define AX_RXD_LAST_MSDU BIT(7)
138 #define AX_RXD_BYPASS BIT(8)
139 #define AX_RXD_CRC32_ERR BIT(9)
140 #define AX_RXD_ICV_ERR BIT(10)
141 #define AX_RXD_MAGIC_WAKE BIT(11)
142 #define AX_RXD_UNICAST_WAKE BIT(12)
143 #define AX_RXD_PATTERN_WAKE BIT(13)
147 #define AX_RXD_CHKSUM_OFFLOAD_EN BIT(24)
148 #define AX_RXD_WITH_LLC BIT(25)
149 #define AX_RXD_RX_STATISTICS BIT(26)
153 #define AX_RXD_MC BIT(2)
154 #define AX_RXD_BC BIT(3)
155 #define AX_RXD_MD BIT(4)
156 #define AX_RXD_MF BIT(5)
157 #define AX_RXD_PWR BIT(6)
158 #define AX_RXD_QOS BIT(7)
160 #define AX_RXD_EOSP BIT(12)
161 #define AX_RXD_HTC BIT(13)
162 #define AX_RXD_QNULL BIT(14)
170 #define AX_RXD_RX_PL_ID_MASK GENMASK(27, 24)
171 #define AX_RXD_ADDR_CAM_VLD BIT(28)
172 #define AX_RXD_ADDR_FWD_EN BIT(29)
173 #define AX_RXD_RX_PL_MATCH BIT(30)
180 #define AX_RXD_SMART_ANT BIT(16)
182 #define AX_RXD_HDR_CNV BIT(21)
184 #define AX_RXD_BIP_KEYID BIT(27)
185 #define AX_RXD_BIP_ENC BIT(28)
190 le32_get_bits((rxdesc)->dword0, BIT(31))
192 le32_get_bits((rxdesc)->dword0, GENMASK(30, 28))
194 le32_get_bits((rxdesc)->dword0, GENMASK(27, 24))
196 le32_get_bits((rxdesc)->dword0, BIT(23))
198 le32_get_bits((rxdesc)->dword0, BIT(22))
200 le32_get_bits((rxdesc)->dword0, GENMASK(21, 16))
202 le32_get_bits((rxdesc)->dword0, GENMASK(15, 14))
204 le32_get_bits((rxdesc)->dword0, GENMASK(13, 0))
206 le32_get_bits((rxdesc)->dword1, GENMASK(31, 30))
208 le32_get_bits((rxdesc)->dword1, GENMASK(31, 29))
210 le32_get_bits((rxdesc)->dword1, GENMASK(27, 25))
212 le32_get_bits((rxdesc)->dword1, GENMASK(24, 16))
214 le32_get_bits((rxdesc)->dword1, GENMASK(15, 8))
216 le32_get_bits((rxdesc)->dword1, BIT(7))
218 le32_get_bits((rxdesc)->dword1, GENMASK(6, 4))
220 le32_get_bits((rxdesc)->dword1, GENMASK(3, 0))
222 le32_get_bits((rxdesc)->dword2, GENMASK(31, 0))
224 le32_get_bits((rxdesc)->dword3, BIT(10))
226 le32_get_bits((rxdesc)->dword3, BIT(9))
228 le32_get_bits((rxdesc)->dword3, BIT(2))
230 le32_get_bits((rxdesc)->dword3, BIT(1))
232 le32_get_bits((rxdesc)->dword3, BIT(0))
236 le32_get_bits((rxdesc)->dword4, GENMASK(31, 28))
238 le32_get_bits((rxdesc)->dword4, GENMASK(27, 16))
240 le32_get_bits((rxdesc)->dword4, GENMASK(1, 0))
242 le32_get_bits((rxdesc)->dword5, BIT(28))
244 le32_get_bits((rxdesc)->dword5, GENMASK(27, 24))
246 le32_get_bits((rxdesc)->dword5, GENMASK(23, 16))
248 le32_get_bits((rxdesc)->dword5, GENMASK(15, 8))
250 le32_get_bits((rxdesc)->dword5, GENMASK(7, 0))
259 le32_get_bits(*((const __le32 *)rpt), BIT(28))
261 le32_get_bits(*((const __le32 *)rpt), BIT(29))
269 le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(0))
271 le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(1))
273 le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(2))
275 le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(3))
277 le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(4))
290 le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(31, 24))
294 le32_get_bits(*((const __le32 *)sts), GENMASK(31, 24))
321 RTW89_TXCH_MAX = RTW89_TXCH_NUM - 1
330 RTW89_RXCH_MAX = RTW89_RXCH_NUM - 1