Lines Matching +full:3 +full:- +full:31
1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
55 #define B_AX_EF_MODE_SEL_MASK GENMASK(31, 30)
62 #define B_AX_EF_ENT BIT(31)
95 #define B_AX_DBG_SEL1_4BIT GENMASK(31, 30)
117 #define B_AX_EN_REGBG BIT(3)
122 #define B_AX_AXIDMA_EN BIT(3)
130 #define B_AX_TOGGLE BIT(31)
138 #define B_AX_DEBUG_ST_MASK GENMASK(31, 0)
153 #define B_AX_PCIE_MIO_DATA_MASK GENMASK(31, 0)
160 #define B_AX_PAD_HCI_SEL_V2_MASK GENMASK(5, 3)
164 #define MAC_AX_HCI_SEL_PCIE_USB 3
186 #define RPWM_SEQ_NUM_MAX 3
190 #define CPWM_SEQ_NUM_MAX 3
196 #define B_AX_EN_32K BIT(31)
207 #define B_AX_VOL_L1_MASK GENMASK(3, 0)
213 #define B_AX_WL_XTAL_SI_CMD_POLL BIT(31)
225 #define B_AX_XTAL_SC_LPS BIT(31)
249 #define B_AX_USB_HCISYS_PWR_STE_MASK GENMASK(3, 2)
260 #define B_AX_WD_ITVL_IDLE_V1_MASK GENMASK(31, 28)
274 #define B_AX_RST_BDRAM BIT(3)
335 #define PCIE_LTR_IDX_IDLE 3
337 #define B_AX_LTR_FW_DEC_EN BIT(3)
432 #define B_AX_DMAC_CRPRT BIT(31)
466 #define PCI_LTR_IDLE_TIMER_200US 3
478 #define PCI_LTR_SPC_1MS 3
502 #define B_AX_L0_TO_L1_EVENT_MASK GENMASK(31, 28)
521 #define B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 BIT(3)
534 #define B_AX_STA_SCHEDULER_ERR_INT_EN BIT(3)
538 #define DMAC_ERR_IMR_EN GENMASK(31, 0)
549 #define B_AX_STA_SCHEDULER_ERR_FLAG BIT(3)
564 #define B_AX_HDT_RX_WRITE_UNDERFLOW_INT_EN BIT(31)
590 #define B_AX_HDT_PERMU_OVERFLOW_INT_EN BIT(3)
629 #define B_AX_HR_WRFF_UNDERFLOW_ERR_INT_EN BIT(31)
655 #define B_AX_HT_PERMU_FF_OVERFLOW_ERR_INT_EN BIT(3)
696 #define B_AX_CPU_RX_WRITE_UNDERFLOW_INT_EN BIT(31)
721 #define B_AX_CPU_PERMU_OVERFLOW_INT_EN BIT(3)
782 #define B_AX_CT_PERMU_FF_OVERFLOW_ERR_INT_EN BIT(3)
835 #define B_AX_WDE_RESP_ERR_INT_EN BIT(3)
858 #define B_AX_REUSE_SIZE_ERR_INT_EN BIT(31)
879 #define B_AX_WDE_RESPONSE_ERR_INT_EN BIT(3)
925 #define B_AX_HCI_FC_CH12_EN BIT(3)
935 #define B_AX_GRP BIT(31)
999 #define B_AX_WDE_ERR_FLAG_MSG_MASK GENMASK(31, 0)
1020 #define B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN BIT(3)
1081 #define B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN_V1 BIT(3)
1150 #define B_AX_WDE_BUFRTN_SIZE_ERR BIT(3)
1168 #define B_AX_DLE_QEMPTY_GRP GENMASK(31, 0)
1175 #define B_AX_WDE_DFI_ACTIVE BIT(31)
1179 #define B_AX_WDE_DFI_DATA_MASK GENMASK(31, 0)
1204 #define B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN BIT(3)
1254 #define B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN_V1 BIT(3)
1329 #define B_AX_PLE_DFI_ACTIVE BIT(31)
1333 #define B_AX_PLE_DFI_DATA_MASK GENMASK(31, 0)
1401 #define B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN BIT(3)
1427 #define B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN BIT(3)
1453 #define B_AX_WD_BUF_REQ_EXEC BIT(31)
1459 #define B_AX_WD_BUF_STAT_DONE BIT(31)
1464 #define B_AX_WD_CPUQ_OP_EXEC BIT(31)
1483 #define B_AX_WD_CPUQ_OP_STAT_DONE BIT(31)
1520 #define B_AX_TX_MPDU_SIZE_ZERO_INT_EN BIT(3)
1551 #define B_AX_RPT_ERR_INT_EN BIT(3)
1563 #define B_AX_MC_DEC BIT(3)
1577 #define B_AX_IMR_ERROR BIT(3)
1580 #define B_AX_TX_TIMEOUT_SEL_MASK GENMASK(31, 30)
1593 #define B_AX_SS_INIT_DONE_1 BIT(31)
1599 #define B_AX_SS_UL_REL BIT(31)
1608 #define B_AX_SS_MACID31_0_PAUSE_MASK GENMASK(31, 0)
1612 #define B_AX_SS_MACID63_32_PAUSE_MASK GENMASK(31, 0)
1616 #define B_AX_SS_MACID95_64_PAUSE_MASK GENMASK(31, 0)
1620 #define B_AX_SS_MACID127_96_PAUSE_MASK GENMASK(31, 0)
1641 #define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN BIT(3)
1666 #define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN BIT(3)
1671 #define B_AX_DFI_ACTIVE BIT(31)
1675 #define B_AX_DFI_DATA_MASK GENMASK(31, 0)
1678 #define B_AX_B0_PRELD_FEN BIT(31)
1699 #define B_AX_B0_IMR_ERR_USRCTL_RLSBMPLEN BIT(3)
1727 #define B_AX_B1_PRELD_FEN BIT(31)
1746 #define B_AX_B1_IMR_ERR_USRCTL_RLSBMPLEN BIT(3)
1776 #define B_AX_R_SYM_WLCMAC1_P3_PC_EN BIT(3)
1791 #define B_AX_CMAC_CRPRT BIT(31)
1798 #define B_AX_PTCLTOP_EN BIT(3)
1805 #define B_AX_CMAC_ALLCKEN GENMASK(31, 0)
1809 #define B_AX_PTCLTOP_CKEN BIT(3)
1820 #define AX_WMAC_RFMOD_160M 3
1839 #define B_AX_TXSC_20M_MASK GENMASK(3, 0)
1844 #define RRSR_OFDM_CCK_EN 3
1846 #define B_AX_RRSR_CCK_MASK GENMASK(3, 0)
1854 #define B_AX_DMA_TOP_ERR_IND_EN BIT(3)
1857 #define CMAC0_ERR_IMR_EN GENMASK(31, 0)
1858 #define CMAC1_ERR_IMR_EN GENMASK(31, 0)
1868 #define B_AX_DMA_TOP_ERR_IND BIT(3)
1875 #define B_AX_MACID31_0_SLEEP_MASK GENMASK(31, 0)
1880 #define B_AX_MACID63_32_SLEEP_MASK GENMASK(31, 0)
1885 #define B_AX_MACID95_64_SLEEP_MASK GENMASK(31, 0)
1890 #define B_AX_MACID127_96_SLEEP_MASK GENMASK(31, 0)
1911 #define B_AX_SEC80_EN BIT(3)
1930 #define B_AX_CTN_TXEN_VO_0 BIT(3)
1938 #define B_AX_MUEDCA_BE_PARAM_0_TIMER_MASK GENMASK(31, 16)
1957 #define B_AX_TB_CHK_TX_NAV BIT(31)
1976 #define B_AX_CTN_CHK_CCA_S80 BIT(3)
2002 #define B_AX_SCHEDULER_DBG_MASK GENMASK(31, 0)
2025 #define B_AX_TSF_UDT_EN BIT(3)
2089 #define B_AX_BCN_ERR_CNT_SUM_MASK GENMASK(31, 24)
2102 #define B_AX_BCN_ERR_FLAG_SRCHEND BIT(3)
2129 #define B_AX_BCN_CNT_TMR_MASK GENMASK(31, 0)
2136 #define B_AX_TSFTR_LOW_MASK GENMASK(31, 0)
2143 #define B_AX_TSFTR_HIGH_MASK GENMASK(31, 0)
2161 #define B_AX_P0MB3_EN BIT(3)
2177 #define B_AX_PTCL_TRIGGER_SS_EN_1 BIT(3)
2183 #define B_AX_AMPDU_MAX_TIME_MASK GENMASK(31, 24)
2190 #define B_AX_AMPDU_MAX_LEN_HT_MASK GENMASK(31, 16)
2197 #define B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK GENMASK(31, 24)
2209 #define B_AX_MAX_TXNSS_MASK GENMASK(3, 2)
2215 #define B_AX_ADD_TXCNT_BY BIT(31)
2234 #define B_AX_TX_RPT_PATH_MASK GENMASK(3, 2)
2240 #define B_AX_BT_PLT_PKT_CNT_MASK GENMASK(31, 16)
2247 #define B_AX_TX_PLT_GNT_LTE_RX BIT(3)
2265 #define B_AX_F2PCMD_PKTID_ERR_INT_EN BIT(31)
2283 #define B_AX_PTCL_IMR_CLR_ALL GENMASK(31, 0)
2324 #define B_AX_PTCL_DBG_INFO_MASK GENMASK(31, 0)
2343 #define B_AX_RXDMA_DBGOUT_EN BIT(31)
2355 #define B_AX_RU3_PTR_FULL_MODE BIT(3)
2396 #define B_AX_PLE_ENQ_FSM_HANG_MSK BIT(3)
2453 #define B_AX_TX_RU0_FSM_HANG_ERR_MSK BIT(31)
2494 #define B_AX_TCR_ZLD_NUM_MASK GENMASK(31, 24)
2505 #define B_AX_TCR_EN_SCRAM_INC BIT(3)
2512 #define B_AX_TXDFIFO_THRESHOLD GENMASK(31, 28)
2525 #define B_AX_TSFT_OFS_MASK GENMASK(31, 16)
2546 #define B_AX_MACTX_MPDU_CNT GENMASK(31, 24)
2556 #define B_AX_TX_CTRL_DEBUG_SEL_MASK GENMASK(3, 0)
2560 #define B_AX_TX_CTRL_INFO_P0_MASK GENMASK(31, 0)
2564 #define B_AX_TX_CTRL_INFO_P1_MASK GENMASK(31, 0)
2581 #define B_AX_WMAC_RESP_STBC_EN BIT(31)
2603 #define B_AX_RESP_TX_MACID_CCA_TH_EN BIT(31)
2632 #define B_AX_RXTRIG_MACID_MASK GENMASK(31, 24)
2648 #define B_AX_TMAC_TXPLCP BIT(3)
2676 #define B_AX_WMAC_TX_TF_INFO_P0_MASK GENMASK(31, 0)
2680 #define B_AX_WMAC_TX_TF_INFO_P1_MASK GENMASK(31, 0)
2716 #define B_AX_DATA_ON_TIMEOUT_EN BIT(3)
2760 #define B_AX_BFMER_HE_CSI_OFFSET_MASK GENMASK(31, 24)
2768 #define B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK GENMASK(31, 24)
2799 #define B_AX_BFMEE_CSIINFO0_NR_MASK GENMASK(5, 3)
2819 #define B_AX_CH_EN_MASK GENMASK(3, 0)
2832 #define B_AX_SIGA_CRC_CHK BIT(3)
2839 #define B_AX_UID_FILTER_MASK GENMASK(31, 24)
2854 #define B_AX_A_MC BIT(3)
2861 u32_encode_bits(3, B_AX_UID_FILTER_MASK) | \
2895 #define B_AX_APP_PLCP_HDR_RPT BIT(3)
2911 #define B_AX_RX_STATE_MONITOR_MASK GENMASK(31, 0)
2912 #define B_AX_STATE_CUR_MASK GENMASK(31, 16)
2919 #define B_AX_RXERR_INTPS_EN BIT(31)
2932 #define B_AX_BMAC_CCA_TIMEOUT_FLAG BIT(3)
2957 #define B_AX_CCA_ASSERT_TO_MSK BIT(3)
2984 #define B_AX_RMAC_PLCP_MON_MASK GENMASK(31, 0)
2985 #define B_AX_PCLP_MON_SEL_MASK GENMASK(31, 28)
3000 #define B_AX_TXAGC_BT_MASK GENMASK(11, 3)
3007 #define B_AX_PWR_UL_TB_CTRL_EN BIT(31)
3072 #define B_AX_BANDEDGE_CFG_IDX_MASK GENMASK(31, 30)
3081 #define B_AX_BTC_EN BIT(31)
3092 #define B_AX_BTC_DBG_SEL_MASK GENMASK(4, 3)
3131 #define B_BTC_PRI_MASK_TX_RESP_V1 BIT(3)
3149 #define B_AX_WL_ACT_MSK BIT(3)
3157 #define B_AX_STATIS_BT_HI_RX_MASK GENMASK(31, 16)
3161 #define B_AX_STATIS_BT_LO_RX_1_MASK GENMASK(31, 16)
3183 #define B_AX_GNT_WL_RFC_S0_VAL BIT(3)
3191 #define B_AX_GNT_BT_RFC_S0_STA BIT(3)
3196 #define B_AX_GNT_BT_RFC_S0 BIT(3)
3202 #define B_AX_R_BT_CMD_RPT_MASK GENMASK(31, 16)
3207 #define B_AX_ENABLE_PTA_TDMA_MODE BIT(3)
3214 #define B_AX_BT_TIME_MASK GENMASK(31, 6)
3231 #define B_AX_GNT_BT_RFC_S1_SW_VAL BIT(31)
3254 #define B_AX_LTECOEX_UART_MUX BIT(3)
3264 #define B_AX_GNT_BT_RX_SW_VAL BIT(3)
3310 #define CFGCH_BAND1_6G 3
3317 #define CFGCH_BW_20M 3
3407 #define RR_RXAE_IQKMOD GENMASK(3, 0)
3412 #define RR_RXA2_C2 GENMASK(9, 3)
3414 #define RR_RXA2_ATT GENMASK(3, 0)
3432 #define RR_DCK1_CLR GENMASK(3, 0)
3433 #define RR_DCK1_SEL BIT(3)
3437 #define RR_DCKC_CHK BIT(3)
3445 #define RR_MIXER_GN GENMASK(4, 3)
3472 #define B_UPD_P0_EN BIT(31)
3474 #define B_ANAPAR_PW15 GENMASK(31, 24)
3478 #define B_ANAPAR_15 GENMASK(31, 16)
3491 #define B_SWSI_DATA_BIT_MASK_EN_V1 BIT(31)
3508 #define B_STS_DIS_TRIG_BY_FAIL BIT(3)
3538 #define B_MAC_SEL_OFDM_TRI_FILTER BIT(31)
3545 #define B_PMAC_TX_PRD_MSK GENMASK(31, 8)
3549 #define B_PMAC_TX_CNT_MSK GENMASK(31, 0)
3560 #define B_IFS_CLM_PERIOD_MSK GENMASK(31, 16)
3565 #define B_IFS_T1_TH_HIGH_MSK GENMASK(31, 16)
3569 #define B_IFS_T2_TH_HIGH_MSK GENMASK(31, 16)
3573 #define B_IFS_T3_TH_HIGH_MSK GENMASK(31, 16)
3577 #define B_IFS_T4_TH_HIGH_MSK GENMASK(31, 16)
3587 #define B_PD_ARBITER_OFF BIT(31)
3620 #define B_P0_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4)
3626 #define B_S0_RXDC_Q GENMASK(31, 26)
3631 #define B_S0_RXDC2_Q2 GENMASK(3, 0)
3642 #define B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK GENMASK(31, 16)
3645 #define B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK GENMASK(31, 16)
3648 #define B_IFS_CLM_OFDM_FA_MSK GENMASK(31, 16)
3651 #define B_IFS_T4_HIS_MSK GENMASK(31, 24)
3656 #define B_IFS_T2_AVG_MSK GENMASK(31, 16)
3659 #define B_IFS_T4_AVG_MSK GENMASK(31, 16)
3662 #define B_IFS_T2_CCA_MSK GENMASK(31, 16)
3665 #define B_IFS_T4_CCA_MSK GENMASK(31, 16)
3675 #define B_TXAGC_BTP GENMASK(31, 24)
3677 #define B_TXAGC_BB_OFT GENMASK(31, 16)
3678 #define B_TXAGC_BB GENMASK(31, 24)
3683 #define B_ADC_FIFO_RST GENMASK(31, 24)
3684 #define B_ADC_FIFO_RXK GENMASK(31, 16)
3710 #define B_RXCCA_DIS BIT(31)
3729 #define B_P1_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4)
3735 #define B_S1_RXDC_Q GENMASK(31, 26)
3739 #define B_S1_RXDC2_Q2 GENMASK(3, 0)
3741 #define B_TXAGC_BB_S1_OFT GENMASK(31, 16)
3742 #define B_TXAGC_BB_S1 GENMASK(31, 24)
3764 #define B_BT_DYN_DC_EST_EN_MSK BIT(31)
3776 #define B_TXPATH_SEL_MSK GENMASK(31, 28)
3822 #define B_PATH0_TIA_ERR_G1_SEL GENMASK(31, 30)
3847 #define B_PATH0_G_LNA6_OP1DB_V1 GENMASK(31, 24)
3865 #define B_P0_BACKOFF_IBADC_V1 GENMASK(31, 26)
3868 #define B_P1_MODE_SEL GENMASK(31, 30)
3870 #define B_P0_AGC_EN BIT(31)
3883 #define B_PATH1_G_LNA6_OP1DB_V1 GENMASK(31, 24)
3914 #define B_FC0_BW_SET GENMASK(31, 30)
3922 #define B_ANT_RX_SEG0 GENMASK(3, 0)
3926 #define B_P1_BACKOFF_IBADC_V1 GENMASK(31, 26)
3934 #define B_P1_AGC_EN BIT(31)
3938 #define B_PATH0_RXBB_MSK_V1 GENMASK(31, 0)
3940 #define B_PATH1_RXBB_MSK_V1 GENMASK(31, 0)
3986 #define B_BMODE_PDTH_LOWER_BOUND_MSK_V1 GENMASK(31, 24)
3996 #define B_DAC_VAL BIT(31)
4007 #define B_DPD_OFT_ADDR GENMASK(31, 27)
4034 #define B_P0_TXDPD GENMASK(31, 28)
4037 #define B_P0_TXPW_RSTB_TSSI BIT(31)
4042 #define B_TXGAIN_SCALE_OFT GENMASK(31, 24)
4045 #define B_S0_DACKI_AR GENMASK(31, 28)
4046 #define B_S0_DACKI_EN BIT(3)
4054 #define B_S0_DACKQ_AR GENMASK(31, 28)
4055 #define B_S0_DACKQ_EN BIT(3)
4079 #define B_P1_TXPW_RSTB_TSSI BIT(31)
4084 #define B_S1_DACKI_AR GENMASK(31, 28)
4085 #define B_S1_DACKI_EN BIT(3)
4093 #define B_S1_DACKQ_AR GENMASK(31, 28)
4094 #define B_S1_DACKQ_EN BIT(3)
4125 #define B_MDPK_SYNC_SEL BIT(31)
4126 #define B_MDPK_SYNC_MAN GENMASK(31, 28)
4128 #define B_MDPK_RX_DCK_EN BIT(31)
4162 #define B_DPK_TRK_DIS BIT(31)
4179 #define B_IQK_RES_RXCFIR GENMASK(3, 0)
4185 #define B_RXIQC_NEWX GENMASK(31, 20)
4198 #define B_CFIR_LUT_G3 BIT(3)
4210 #define B_DPD_MEN GENMASK(31, 28)
4228 #define B_DPK_GL_A0 GENMASK(31, 28)
4251 #define B_IQKINF_VER GENMASK(31, 24)
4254 #define B_IQKINF_FAIL GENMASK(3, 0)
4255 #define B_IQKINF_F_RX BIT(3)
4262 #define B_IQKCH_BAND GENMASK(3, 0)
4274 #define B_DACK_S0P0_OK BIT(31)
4278 #define B_DACK_S0M0 GENMASK(31, 24)
4281 #define B_DACK_DADCK00 GENMASK(31, 24)
4283 #define B_DACK_S0P1_OK BIT(31)
4287 #define B_DACK_S0M1 GENMASK(31, 24)
4290 #define B_DACK_DADCK01 GENMASK(31, 24)
4297 #define B_DRCK_POL BIT(3)
4322 #define B_DACK_S1P0_OK BIT(31)
4326 #define B_DACK10S GENMASK(31, 24)
4330 #define B_DACK_DADCK10 GENMASK(31, 24)
4332 #define B_DACK_S1P1_OK BIT(31)
4336 #define B_DACK11S GENMASK(31, 24)
4340 #define B_DACK_DADCK11 GENMASK(31, 24)
4361 #define B_AX_WDT_EN BIT(31)