Lines Matching +full:24 +full:- +full:9

1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020  Realtek Corporation
31 #define B_AX_APFM_OFFMAC BIT(9)
48 #define B_AX_EF_VDDQST_MASK GENMASK(26, 24)
52 #define B_AX_EF_CELL_SEL_MASK GENMASK(9, 8)
70 #define B_AX_WDT_WAKE_USB_EN BIT(9)
82 #define B_AX_PO_BT_PTA_PINS BIT(9)
131 #define B_MAC_AX_SB_FW_MASK GENMASK(30, 24)
188 #define PS_CPWM_RSP_SEQ_NUM GENMASK(9, 8)
217 #define B_AX_WL_XTAL_SI_MODE_MASK GENMASK(25, 24)
240 #define B_AX_WLRF1_CTRL_1 BIT(9)
246 #define B_AX_WLMAC_PWR_STE_MASK GENMASK(9, 8)
253 #define B_AX_S1_LDO_VSEL_F_MASK GENMASK(25, 24)
261 #define B_AX_WD_ITVL_ACT_V1_MASK GENMASK(27, 24)
271 #define B_AX_HAXI_MAX_RXDMA_MASK GENMASK(9, 8)
288 #define B_AX_STOP_ACH1 BIT(9)
303 #define B_AX_ACH1_BUSY BIT(9)
332 #define B_AX_LTR_CURR_IDX_HW_MASK GENMASK(9, 8)
439 #define B_AX_STA_SCH_EN BIT(24)
455 #define B_AX_STA_SCH_CLK_EN BIT(24)
507 #define B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU BIT(24)
517 #define B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX BIT(9)
528 #define B_AX_APB_BRIDGE_ERR_INT_EN BIT(9)
543 #define B_AX_APB_BRIDGE_ERR_FLAG BIT(9)
555 #define B_AX_PL_PAGE_128B_SEL BIT(9)
571 #define B_AX_HDT_RXAGG_CFG_ERR_INT_EN BIT(24)
584 #define B_AX_HDT_WD_CHK_ERR_INT_EN BIT(9)
636 #define B_AX_HR_AGG_CFG_ERR_INT_EN BIT(24)
649 #define B_AX_HT_WD_CHKSUM_ERR_INT_EN BIT(9)
703 #define B_AX_CPU_RXAGG_CFG_ERR_INT_EN BIT(24)
715 #define B_AX_CPU_CHANNEL_DMA_ERR_INT_EN BIT(9)
763 #define B_AX_CR_SHIFT_EN_ERR_INT_EN BIT(24)
776 #define B_AX_CT_CHANNEL_DMA_ERR_INT_EN BIT(9)
826 #define B_AX_OTHER_STF_CMD_OVERFLOW_INT_EN BIT(24)
832 #define B_AX_PLE_NULL_PKT_ERR_INT_EN BIT(9)
865 #define B_AX_STF_CMD_OVERFLOW_ERR_INT_EN BIT(24)
922 #define B_AX_HCI_FC_WP_CH811_FULL_COND_MASK GENMASK(9, 8)
930 #define B_AX_PREC_PAGE_CH12_MASK GENMASK(24, 16)
984 #define B_AX_PREC_PAGE_WP_CH811_MASK GENMASK(24, 16)
1007 #define B_AX_WDE_DATCHN_ARBT_ERR_INT_EN BIT(24)
1068 #define B_AX_WDE_DATCHN_ARBT_ERR_INT_EN BIT(24)
1075 #define B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN_V1 BIT(9)
1137 #define B_AX_WDE_DATCHN_ARBT_ERR BIT(24)
1191 #define B_AX_PLE_DATCHN_ARBT_ERR_INT_EN BIT(24)
1248 #define B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN_V1 BIT(9)
1340 #define B_AX_RLSRPT0_FLTR_MAP_MASK GENMASK(27, 24)
1352 #define B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN BIT(9)
1465 #define B_AX_CPUQ_OP_CMD_TYPE_MASK GENMASK(27, 24)
1471 #define B_AX_CPUQ_OP_SRC_PID_MASK GENMASK(24, 22)
1514 #define B_AX_TX_KSRCH_ERR_EN BIT(9)
1559 #define B_AX_CLK_EN_WAPI BIT(9)
1600 #define B_AX_SS_REL_QUEUE_MASK GENMASK(29, 24)
1634 #define B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR BIT(24)
1639 #define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN BIT(9)
1665 #define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN BIT(9)
1697 #define B_AX_B0_IMR_ERR_CMDPSR_CMDTYPE BIT(9)
1744 #define B_AX_B1_IMR_ERR_CMDPSR_CMDTYPE BIT(9)
1899 #define B_AX_SIFS_TIMEOUT_TB_AGGR_MASK GENMASK(30, 24)
1908 #define B_AX_BTCCA_BRK_TXOP_EN BIT(9)
1924 #define B_AX_CTN_TXEN_MGQ1 BIT(9)
1964 #define B_AX_TB_CHK_CCA_P20 BIT(24)
2019 #define B_AX_BCN_FORCETX_EN BIT(9)
2089 #define B_AX_BCN_ERR_CNT_SUM_MASK GENMASK(31, 24)
2155 #define B_AX_P0MB9_EN BIT(9)
2183 #define B_AX_AMPDU_MAX_TIME_MASK GENMASK(31, 24)
2197 #define B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK GENMASK(31, 24)
2216 #define B_AX_S_TXCNT_LMT_MASK GENMASK(29, 24)
2222 #define B_AX_RATE_SEL_MASK GENMASK(29, 24)
2229 #define B_AX_F2PCMD_FWWD_RLS_MODE BIT(9)
2241 #define B_AX_BT_PLT_RST BIT(9)
2254 #define B_AX_BSS_COLOB_AX_PORT_3_MASK GENMASK(29, 24)
2272 #define B_AX_TX_SPF_U3_PKTID_ERR_INT_EN BIT(24)
2279 #define B_AX_TXPRT_FULL_DROP_ERR_INT_EN BIT(9)
2350 #define B_AX_RXDMA_DIS_CSI_RELEASE BIT(9)
2375 #define B_AX_RX_RU5_FSM_HANG_MSK_ERR_MSK BIT(24)
2390 #define B_AX_RX_RXSTS_ZERO_LEN_ERR_MSK BIT(9)
2460 #define B_AX_TX_RU7_FSM_HANG_ERR_MSK BIT(24)
2494 #define B_AX_TCR_ZLD_NUM_MASK GENMASK(31, 24)
2499 #define B_AX_TCR_VHTSIGA1_TXPS BIT(9)
2535 #define B_AX_NON_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(28, 24)
2546 #define B_AX_MACTX_MPDU_CNT GENMASK(31, 24)
2550 #define B_AX_LENGTH_ERR_FLAG_U1 BIT(9)
2588 #define B_AX_RSP_CHK_EDCCA BIT(24)
2605 #define B_AX_FTM_RRSR_RATE_EN_MASK GENMASK(27, 24)
2612 #define B_AX_WMAC_RESP_REF_RATE_SEL BIT(9)
2632 #define B_AX_RXTRIG_MACID_MASK GENMASK(31, 24)
2693 #define B_AX_TMAC_RESP_INT_EN BIT(9)
2740 #define B_AXC_PHY_TXON_TIMEOUT BIT(24)
2760 #define B_AX_BFMER_HE_CSI_OFFSET_MASK GENMASK(31, 24)
2768 #define B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK GENMASK(31, 24)
2784 #define B_AX_BFMEE_OFDM_LEN_TH_MASK GENMASK(27, 24)
2797 #define B_AX_BFMEE_CSIINFO0_CB_MASK GENMASK(9, 8)
2839 #define B_AX_UID_FILTER_MASK GENMASK(31, 24)
2849 #define B_AX_A_BCN_CHK_RULE_MASK GENMASK(9, 8)
2907 #define B_AX_CSIPRT_VHTSU_AID_EN BIT(24)
2951 #define B_AX_RX_ERR_TRIG_ACT_TO_MSK BIT(9)
2994 #define B_AX_FORCE_PWR_BY_RATE_EN BIT(9)
3085 #define B_AX_BTC_MODE_MASK GENMASK(25, 24)
3099 #define B_AX_BT_BLE_EN_V1 BIT(24)
3104 #define B_AX_BT_H_TX_ULTRA_MASK GENMASK(9, 8)
3177 #define B_AX_GNT_BT_RFC_S1_VAL BIT(9)
3238 #define B_AX_GNT_WL_BB_S1_SW_CTRL BIT(24)
3249 #define B_AX_GNT_WL_BB_S0_SW_VAL BIT(9)
3284 #define RR_MOD_M_RXBB GENMASK(9, 5)
3297 #define RR_LOKVB_COQ GENMASK(9, 4)
3304 #define RR_CHTR_TXRX GENMASK(9, 0)
3311 #define RR_CFGCH_BAND0 GENMASK(9, 8)
3330 #define RR_RCKO_OFF GENMASK(13, 9)
3336 #define RR_RSV4_PLLCH GENMASK(9, 0)
3342 #define RR_LUTWA_MASK GENMASK(9, 0)
3364 #define RR_GAINTX_PAD GENMASK(9, 5)
3369 #define RR_TXMO_FII GENMASK(9, 6)
3399 #define RR_RXBB_C1G GENMASK(9, 8)
3409 #define RR_RXA_DPK GENMASK(9, 8)
3412 #define RR_RXA2_C2 GENMASK(9, 3)
3422 #define RR_RXBB2_IDAC GENMASK(11, 9)
3453 #define RR_IQKPLL_MOD GENMASK(9, 8)
3474 #define B_ANAPAR_PW15 GENMASK(31, 24)
3475 #define B_ANAPAR_PW15_H GENMASK(27, 24)
3500 #define B_UPD_CLK_ADC_ON BIT(24)
3581 #define B_PD_HIT_DIS BIT(9)
3593 #define B_RXHT_MCS_LIMIT GENMASK(9, 8)
3628 #define B_S0_RXDC2_SEL GENMASK(9, 8)
3637 #define B_SWSI_W_BUSY_V1 BIT(24)
3651 #define B_IFS_T4_HIS_MSK GENMASK(31, 24)
3673 #define B_TSSI_THER GENMASK(29, 24)
3675 #define B_TXAGC_BTP GENMASK(31, 24)
3678 #define B_TXAGC_BB GENMASK(31, 24)
3680 #define B_S0_ADDCK_I GENMASK(9, 0)
3683 #define B_ADC_FIFO_RST GENMASK(31, 24)
3686 #define B_ADC_FIFO_A2 BIT(24)
3738 #define B_S1_RXDC2_SEL GENMASK(9, 8)
3742 #define B_TXAGC_BB_S1 GENMASK(31, 24)
3744 #define B_S1_ADDCK_I GENMASK(9, 0)
3766 #define B_ASSIGN_SBD_OPT_EN BIT(24)
3770 #define B_DCFO_WEIGHT_MSK GENMASK(27, 24)
3800 #define B_PATH0_LNA_ERR_G1_A_MSK GENMASK(29, 24)
3808 #define B_PATH0_LNA_ERR_G4_G_MSK GENMASK(29, 24)
3813 #define B_PATH0_LNA_ERR_G6_A_MSK GENMASK(29, 24)
3828 #define B_PATH0_RXB_INIT_IDX_MSK GENMASK(9, 5)
3831 #define B_PATH0_LNA_INIT_IDX_MSK GENMASK(26, 24)
3847 #define B_PATH0_G_LNA6_OP1DB_V1 GENMASK(31, 24)
3873 #define B_PATH1_LNA_INIT_IDX_MSK GENMASK(26, 24)
3875 #define B_PATH0_TIA_INIT_IDX_MSK_V1 BIT(9)
3881 #define B_PATH1_RXB_INIT_IDX_MSK GENMASK(9, 5)
3883 #define B_PATH1_G_LNA6_OP1DB_V1 GENMASK(31, 24)
3936 #define B_PATH1_TIA_INIT_IDX_MSK_V1 BIT(9)
3986 #define B_BMODE_PDTH_LOWER_BOUND_MSK_V1 GENMASK(31, 24)
3993 #define B_CFO_COMP_WEIGHT_MSK GENMASK(27, 24)
4013 #define B_P0_TMETER_TRK BIT(24)
4042 #define B_TXGAIN_SCALE_OFT GENMASK(31, 24)
4067 #define B_P1_TMETER_TRK BIT(24)
4157 #define B_DPK_MPA_T1 BIT(9)
4204 #define B_DPK_GN_AG GENMASK(9, 0)
4211 #define B_DPD_ORDER GENMASK(26, 24)
4251 #define B_IQKINF_VER GENMASK(31, 24)
4278 #define B_DACK_S0M0 GENMASK(31, 24)
4281 #define B_DACK_DADCK00 GENMASK(31, 24)
4287 #define B_DACK_S0M1 GENMASK(31, 24)
4290 #define B_DACK_DADCK01 GENMASK(31, 24)
4292 #define B_DRCK_IDLE BIT(9)
4305 #define B_ADDCK0 GENMASK(9, 8)
4314 #define B_ADDCKR0_A1 GENMASK(9, 0)
4326 #define B_DACK10S GENMASK(31, 24)
4330 #define B_DACK_DADCK10 GENMASK(31, 24)
4336 #define B_DACK11S GENMASK(31, 24)
4340 #define B_DACK_DADCK11 GENMASK(31, 24)
4348 #define B_ADDCK1 GENMASK(9, 8)
4357 #define B_ADDCKR1_A1 GENMASK(9, 0)