Lines Matching +full:0 +full:x1280
10 #define MDIO_PG0_G1 0
14 #define RAC_CTRL_PPR 0x00
15 #define RAC_ANA0A 0x0A
17 #define RAC_ANA0C 0x0C
19 #define RAC_ANA10 0x10
21 #define RAC_REG_REV2 0x1B
23 #define PCIE_DPHY_DLY_25US 0x1
24 #define RAC_ANA19 0x19
26 #define RAC_REG_FLD_0 0x1D
28 #define PCIE_AUTOK_4 0x3
29 #define RAC_ANA1F 0x1F
30 #define RAC_ANA24 0x24
32 #define RAC_ANA26 0x26
34 #define RAC_CTRL_PPR_V1 0x30
38 #define RAC_SET_PPR_V1 0x31
40 #define R_AX_DBI_FLAG 0x1090
45 #define R_AX_DBI_WDATA 0x1094
46 #define R_AX_DBI_RDATA 0x1098
48 #define R_AX_MDIO_WDATA 0x10A4
49 #define R_AX_MDIO_RDATA 0x10A6
51 #define R_AX_PCIE_PS_CTRL_V1 0x3008
56 #define B_AX_SEL_REQ_EXIT_L1 BIT(0)
58 #define R_AX_PCIE_MIX_CFG_V1 0x300C
66 #define B_AX_L1SUB_DISABLE BIT(0)
68 #define R_AX_L1_CLK_CTRL 0x3010
71 #define R_AX_PCIE_BG_CLR 0x303C
74 #define R_AX_PCIE_LAT_CTRL 0x3044
76 #define B_AX_CLK_REQ_SEL BIT(0)
78 #define R_AX_PCIE_IO_RCY_M1 0x3100
82 #define B_AX_PCIE_IO_RCY_TRIG_M1 BIT(0)
84 #define R_AX_PCIE_WDT_TIMER_M1 0x3104
85 #define B_AX_PCIE_WDT_TIMER_M1_MASK GENMASK(31, 0)
87 #define R_AX_PCIE_IO_RCY_M2 0x310C
91 #define B_AX_PCIE_IO_RCY_TRIG_M2 BIT(0)
93 #define R_AX_PCIE_WDT_TIMER_M2 0x3110
94 #define B_AX_PCIE_WDT_TIMER_M2_MASK GENMASK(31, 0)
96 #define R_AX_PCIE_IO_RCY_E0 0x3118
100 #define B_AX_PCIE_IO_RCY_TRIG_E0 BIT(0)
102 #define R_AX_PCIE_WDT_TIMER_E0 0x311C
103 #define B_AX_PCIE_WDT_TIMER_E0_MASK GENMASK(31, 0)
105 #define R_AX_PCIE_IO_RCY_S1 0x3124
112 #define B_AX_PCIE_IO_RCY_WTRIG_S1 BIT(0)
114 #define R_AX_PCIE_WDT_TIMER_S1 0x3128
115 #define B_AX_PCIE_WDT_TIMER_S1_MASK GENMASK(31, 0)
117 #define R_RAC_DIRECT_OFFSET_G1 0x3800
119 #define R_RAC_DIRECT_OFFSET_G2 0x3880
126 #define R_AX_HIMR0 0x01A0
129 #define R_AX_HISR0 0x01A4
131 #define R_AX_HIMR1 0x01A8
134 #define B_AX_GPIO16_INT_EN BIT(0)
136 #define R_AX_HISR1 0x01AC
139 #define B_AX_GPIO16_INT BIT(0)
141 #define R_AX_MDIO_CFG 0x10A0
145 #define B_AX_MDIO_ADDR_MASK GENMASK(4, 0)
147 #define R_AX_PCIE_HIMR00 0x10B0
148 #define R_AX_HAXI_HIMR00 0x10B0
174 #define B_AX_RXDMA_INT_EN BIT(0)
176 #define R_AX_PCIE_HISR00 0x10B4
177 #define R_AX_HAXI_HISR00 0x10B4
203 #define B_AX_RXDMA_INT BIT(0)
205 #define R_AX_HAXI_HIMR10 0x11E0
207 #define B_AX_TXDMA_CH10_INT_EN_V1 BIT(0)
209 #define R_AX_PCIE_HIMR10 0x13B0
214 #define R_AX_PCIE_HISR10 0x13B4
219 #define R_AX_PCIE_HIMR00_V1 0x30B0
227 #define R_AX_PCIE_HISR00_V1 0x30B4
236 #define R_AX_DRV_FW_HSK_0 0x01B0
237 #define R_AX_DRV_FW_HSK_1 0x01B4
238 #define R_AX_DRV_FW_HSK_2 0x01B8
239 #define R_AX_DRV_FW_HSK_3 0x01BC
240 #define R_AX_DRV_FW_HSK_4 0x01C0
241 #define R_AX_DRV_FW_HSK_5 0x01C4
242 #define R_AX_DRV_FW_HSK_6 0x01C8
243 #define R_AX_DRV_FW_HSK_7 0x01CC
245 #define R_AX_RXQ_RXBD_IDX 0x1050
246 #define R_AX_RPQ_RXBD_IDX 0x1054
247 #define R_AX_ACH0_TXBD_IDX 0x1058
248 #define R_AX_ACH1_TXBD_IDX 0x105C
249 #define R_AX_ACH2_TXBD_IDX 0x1060
250 #define R_AX_ACH3_TXBD_IDX 0x1064
251 #define R_AX_ACH4_TXBD_IDX 0x1068
252 #define R_AX_ACH5_TXBD_IDX 0x106C
253 #define R_AX_ACH6_TXBD_IDX 0x1070
254 #define R_AX_ACH7_TXBD_IDX 0x1074
255 #define R_AX_CH8_TXBD_IDX 0x1078 /* Management Queue band 0 */
256 #define R_AX_CH9_TXBD_IDX 0x107C /* HI Queue band 0 */
257 #define R_AX_CH10_TXBD_IDX 0x137C /* Management Queue band 1 */
258 #define R_AX_CH11_TXBD_IDX 0x1380 /* HI Queue band 1 */
259 #define R_AX_CH12_TXBD_IDX 0x1080 /* FWCMD Queue */
260 #define R_AX_CH10_TXBD_IDX_V1 0x11D0
261 #define R_AX_CH11_TXBD_IDX_V1 0x11D4
262 #define R_AX_RXQ_RXBD_IDX_V1 0x1218
263 #define R_AX_RPQ_RXBD_IDX_V1 0x121C
265 #define TXBD_HOST_IDX_MASK GENMASK(11, 0)
267 #define R_AX_ACH0_TXBD_DESA_L 0x1110
268 #define R_AX_ACH0_TXBD_DESA_H 0x1114
269 #define R_AX_ACH1_TXBD_DESA_L 0x1118
270 #define R_AX_ACH1_TXBD_DESA_H 0x111C
271 #define R_AX_ACH2_TXBD_DESA_L 0x1120
272 #define R_AX_ACH2_TXBD_DESA_H 0x1124
273 #define R_AX_ACH3_TXBD_DESA_L 0x1128
274 #define R_AX_ACH3_TXBD_DESA_H 0x112C
275 #define R_AX_ACH4_TXBD_DESA_L 0x1130
276 #define R_AX_ACH4_TXBD_DESA_H 0x1134
277 #define R_AX_ACH5_TXBD_DESA_L 0x1138
278 #define R_AX_ACH5_TXBD_DESA_H 0x113C
279 #define R_AX_ACH6_TXBD_DESA_L 0x1140
280 #define R_AX_ACH6_TXBD_DESA_H 0x1144
281 #define R_AX_ACH7_TXBD_DESA_L 0x1148
282 #define R_AX_ACH7_TXBD_DESA_H 0x114C
283 #define R_AX_CH8_TXBD_DESA_L 0x1150
284 #define R_AX_CH8_TXBD_DESA_H 0x1154
285 #define R_AX_CH9_TXBD_DESA_L 0x1158
286 #define R_AX_CH9_TXBD_DESA_H 0x115C
287 #define R_AX_CH10_TXBD_DESA_L 0x1358
288 #define R_AX_CH10_TXBD_DESA_H 0x135C
289 #define R_AX_CH11_TXBD_DESA_L 0x1360
290 #define R_AX_CH11_TXBD_DESA_H 0x1364
291 #define R_AX_CH12_TXBD_DESA_L 0x1160
292 #define R_AX_CH12_TXBD_DESA_H 0x1164
293 #define R_AX_RXQ_RXBD_DESA_L 0x1100
294 #define R_AX_RXQ_RXBD_DESA_H 0x1104
295 #define R_AX_RPQ_RXBD_DESA_L 0x1108
296 #define R_AX_RPQ_RXBD_DESA_H 0x110C
297 #define R_AX_RXQ_RXBD_DESA_L_V1 0x1220
298 #define R_AX_RXQ_RXBD_DESA_H_V1 0x1224
299 #define R_AX_RPQ_RXBD_DESA_L_V1 0x1228
300 #define R_AX_RPQ_RXBD_DESA_H_V1 0x122C
301 #define R_AX_ACH0_TXBD_DESA_L_V1 0x1230
302 #define R_AX_ACH0_TXBD_DESA_H_V1 0x1234
303 #define R_AX_ACH1_TXBD_DESA_L_V1 0x1238
304 #define R_AX_ACH1_TXBD_DESA_H_V1 0x123C
305 #define R_AX_ACH2_TXBD_DESA_L_V1 0x1240
306 #define R_AX_ACH2_TXBD_DESA_H_V1 0x1244
307 #define R_AX_ACH3_TXBD_DESA_L_V1 0x1248
308 #define R_AX_ACH3_TXBD_DESA_H_V1 0x124C
309 #define R_AX_ACH4_TXBD_DESA_L_V1 0x1250
310 #define R_AX_ACH4_TXBD_DESA_H_V1 0x1254
311 #define R_AX_ACH5_TXBD_DESA_L_V1 0x1258
312 #define R_AX_ACH5_TXBD_DESA_H_V1 0x125C
313 #define R_AX_ACH6_TXBD_DESA_L_V1 0x1260
314 #define R_AX_ACH6_TXBD_DESA_H_V1 0x1264
315 #define R_AX_ACH7_TXBD_DESA_L_V1 0x1268
316 #define R_AX_ACH7_TXBD_DESA_H_V1 0x126C
317 #define R_AX_CH8_TXBD_DESA_L_V1 0x1270
318 #define R_AX_CH8_TXBD_DESA_H_V1 0x1274
319 #define R_AX_CH9_TXBD_DESA_L_V1 0x1278
320 #define R_AX_CH9_TXBD_DESA_H_V1 0x127C
321 #define R_AX_CH12_TXBD_DESA_L_V1 0x1280
322 #define R_AX_CH12_TXBD_DESA_H_V1 0x1284
323 #define R_AX_CH10_TXBD_DESA_L_V1 0x1458
324 #define R_AX_CH10_TXBD_DESA_H_V1 0x145C
325 #define R_AX_CH11_TXBD_DESA_L_V1 0x1460
326 #define R_AX_CH11_TXBD_DESA_H_V1 0x1464
327 #define B_AX_DESC_NUM_MSK GENMASK(11, 0)
329 #define R_AX_RXQ_RXBD_NUM 0x1020
330 #define R_AX_RPQ_RXBD_NUM 0x1022
331 #define R_AX_ACH0_TXBD_NUM 0x1024
332 #define R_AX_ACH1_TXBD_NUM 0x1026
333 #define R_AX_ACH2_TXBD_NUM 0x1028
334 #define R_AX_ACH3_TXBD_NUM 0x102A
335 #define R_AX_ACH4_TXBD_NUM 0x102C
336 #define R_AX_ACH5_TXBD_NUM 0x102E
337 #define R_AX_ACH6_TXBD_NUM 0x1030
338 #define R_AX_ACH7_TXBD_NUM 0x1032
339 #define R_AX_CH8_TXBD_NUM 0x1034
340 #define R_AX_CH9_TXBD_NUM 0x1036
341 #define R_AX_CH10_TXBD_NUM 0x1338
342 #define R_AX_CH11_TXBD_NUM 0x133A
343 #define R_AX_CH12_TXBD_NUM 0x1038
344 #define R_AX_RXQ_RXBD_NUM_V1 0x1210
345 #define R_AX_RPQ_RXBD_NUM_V1 0x1212
346 #define R_AX_CH10_TXBD_NUM_V1 0x1438
347 #define R_AX_CH11_TXBD_NUM_V1 0x143A
349 #define R_AX_ACH0_BDRAM_CTRL 0x1200
350 #define R_AX_ACH1_BDRAM_CTRL 0x1204
351 #define R_AX_ACH2_BDRAM_CTRL 0x1208
352 #define R_AX_ACH3_BDRAM_CTRL 0x120C
353 #define R_AX_ACH4_BDRAM_CTRL 0x1210
354 #define R_AX_ACH5_BDRAM_CTRL 0x1214
355 #define R_AX_ACH6_BDRAM_CTRL 0x1218
356 #define R_AX_ACH7_BDRAM_CTRL 0x121C
357 #define R_AX_CH8_BDRAM_CTRL 0x1220
358 #define R_AX_CH9_BDRAM_CTRL 0x1224
359 #define R_AX_CH10_BDRAM_CTRL 0x1320
360 #define R_AX_CH11_BDRAM_CTRL 0x1324
361 #define R_AX_CH12_BDRAM_CTRL 0x1228
362 #define R_AX_ACH0_BDRAM_CTRL_V1 0x1300
363 #define R_AX_ACH1_BDRAM_CTRL_V1 0x1304
364 #define R_AX_ACH2_BDRAM_CTRL_V1 0x1308
365 #define R_AX_ACH3_BDRAM_CTRL_V1 0x130C
366 #define R_AX_ACH4_BDRAM_CTRL_V1 0x1310
367 #define R_AX_ACH5_BDRAM_CTRL_V1 0x1314
368 #define R_AX_ACH6_BDRAM_CTRL_V1 0x1318
369 #define R_AX_ACH7_BDRAM_CTRL_V1 0x131C
370 #define R_AX_CH8_BDRAM_CTRL_V1 0x1320
371 #define R_AX_CH9_BDRAM_CTRL_V1 0x1324
372 #define R_AX_CH12_BDRAM_CTRL_V1 0x1328
373 #define R_AX_CH10_BDRAM_CTRL_V1 0x1420
374 #define R_AX_CH11_BDRAM_CTRL_V1 0x1424
375 #define BDRAM_SIDX_MASK GENMASK(7, 0)
379 #define R_AX_PCIE_INIT_CFG1 0x1000
396 #define R_AX_TXDMA_ADDR_H 0x10F0
397 #define R_AX_RXDMA_ADDR_H 0x10F4
399 #define R_AX_PCIE_DMA_STOP1 0x1010
414 #define B_AX_STOP_RXQ BIT(0)
427 #define R_AX_PCIE_DMA_STOP2 0x1310
429 #define B_AX_STOP_CH10 BIT(0)
430 #define B_AX_TX_STOP2_ALL GENMASK(1, 0)
432 #define R_AX_TXBD_RWPTR_CLR1 0x1014
443 #define B_AX_CLR_ACH0_IDX BIT(0)
444 #define B_AX_TXBD_CLR1_ALL GENMASK(10, 0)
446 #define R_AX_RXBD_RWPTR_CLR 0x1018
448 #define B_AX_CLR_RXQ_IDX BIT(0)
449 #define B_AX_RXBD_CLR_ALL GENMASK(1, 0)
451 #define R_AX_TXBD_RWPTR_CLR2 0x1314
453 #define B_AX_CLR_CH10_IDX BIT(0)
454 #define B_AX_TXBD_CLR2_ALL GENMASK(1, 0)
456 #define R_AX_PCIE_DMA_BUSY1 0x101C
473 #define B_AX_RXQ_BUSY BIT(0)
482 #define R_AX_PCIE_DMA_BUSY2 0x131C
484 #define B_AX_CH10_BUSY BIT(0)
487 #define R_AX_PCIE_INIT_CFG2 0x1004
490 #define B_AX_PCIE_RX_APPLEN_MASK GENMASK(13, 0)
492 #define R_AX_PCIE_PS_CTRL 0x1008
495 #define R_AX_INT_MIT_RX 0x10D4
499 #define AX_RXTIMER_UNIT_64US 0
504 #define B_AX_RXTIMER_MATCH_MASK GENMASK(7, 0)
506 #define R_AX_DBG_ERR_FLAG 0x11C4
515 #define B_AX_PCIE_TXBD_4KBOUD_LENERR BIT(0)
517 #define R_AX_TXBD_RWPTR_CLR2_V1 0x11C4
519 #define B_AX_CLR_CH10_IDX BIT(0)
521 #define R_AX_LBC_WATCHDOG 0x11D8
524 #define B_AX_LBC_EN BIT(0)
526 #define R_AX_RXBD_RWPTR_CLR_V1 0x1200
528 #define B_AX_CLR_RXQ_IDX BIT(0)
530 #define R_AX_HAXI_EXP_CTRL 0x1204
531 #define B_AX_MAX_TAG_NUM_V1_MASK GENMASK(2, 0)
533 #define R_AX_PCIE_EXP_CTRL 0x13F0
538 #define R_AX_PCIE_RX_PREF_ADV 0x13F4
539 #define B_AX_RXDMA_PREF_ADV_EN BIT(0)
541 #define R_AX_PCIE_HRPWM_V1 0x30C0
542 #define R_AX_PCIE_CRPWM 0x30C4
555 #define RTW89_PCIE_L1_STS_V1 0x80
557 #define RTW89_PCIE_GEN1_SPEED 0x01
558 #define RTW89_PCIE_GEN2_SPEED 0x02
559 #define RTW89_PCIE_PHY_RATE 0x82
560 #define RTW89_PCIE_PHY_RATE_MASK GENMASK(1, 0)
561 #define RTW89_PCIE_L1SS_STS_V1 0x0168
565 #define RTW89_PCIE_BIT_PCI_L12 BIT(0)
566 #define RTW89_PCIE_ASPM_CTRL 0x070F
568 #define RTW89_L0DLY_MASK GENMASK(2, 0)
569 #define RTW89_PCIE_TIMER_CTRL 0x0718
571 #define RTW89_PCIE_L1_CTRL 0x0719
574 #define RTW89_PCIE_CLK_CTRL 0x0725
575 #define RTW89_PCIE_RST_MSTATE 0x0B48
576 #define RTW89_PCIE_BIT_CFG_RST_MSTATE BIT(0)
584 PCIE_PHY_GEN1_UNDEFINE = 0x7F,
588 PCIE_L0SDLY_1US = 0,
605 PCIE_CLKDLY_HW_0 = 0,
606 PCIE_CLKDLY_HW_30US = 0x1,
607 PCIE_CLKDLY_HW_50US = 0x2,
608 PCIE_CLKDLY_HW_100US = 0x3,
609 PCIE_CLKDLY_HW_150US = 0x4,
610 PCIE_CLKDLY_HW_200US = 0x5,
616 MAC_AX_BD_DEF = 0xFE
622 MAC_AX_RXBD_DEF = 0xFE
628 MAC_AX_TAG_DEF = 0xFE
632 MAC_AX_TX_BURST_16B = 0,
635 MAC_AX_TX_BURST_V1_64B = 0,
643 MAC_AX_TX_BURST_DEF = 0xFE
647 MAC_AX_RX_BURST_16B = 0,
650 MAC_AX_RX_BURST_V1_64B = 0,
653 MAC_AX_RX_BURST_V1_256B = 0,
654 MAC_AX_RX_BURST_DEF = 0xFE
668 MAC_AX_WD_DMA_INTVL_DEF = 0xFE
680 MAC_AX_TAG_NUM_DEF = 0xFE
684 MAC_AX_LBC_TMR_8US = 0,
695 MAC_AX_LBC_TMR_DEF = 0xFE
699 MAC_AX_PCIE_DISABLE = 0,
701 MAC_AX_PCIE_DEFAULT = 0xFE,
702 MAC_AX_PCIE_IGNORE = 0xFF
709 MAC_AX_IO_RCY_ANA_TMR_DEF = 0xFE
824 #define RTW89_PCI_ADDR_NUM(x) ((x) & GENMASK(5, 0))
836 #define B_PCIADDR_LEN_V1_MASK GENMASK(10, 0)
847 #define RTW89_TX_DONE 0x0
848 #define RTW89_TX_RETRY_LIMIT 0x1
849 #define RTW89_TX_LIFE_TIME 0x2
850 #define RTW89_TX_MACID_DROP 0x3
852 #define RTW89_PCI_RPP_MACID GENMASK(7, 0)
866 #define RTW89_PCI_RXBD_WRITE_SIZE GENMASK(13, 0)
907 #define RTW89_RX_TAG_MAX 0x1fff
915 u16 tag; /* range from 0x0001 ~ 0x1fff */
1023 txwd->len = 0; in rtw89_pci_dequeue_txwd()
1035 memset(txwd->vaddr, 0, wd_ring->page_size); in rtw89_pci_enqueue_txwd()
1042 return val == 0xffffffff || val == 0xeaeaeaea; in rtw89_pci_ltr_is_err_reg_val()