183 		rtw89_write32_set(rtwdev, dma_stop1->addr, dma_stop1->mask);  in rtw89_pci_ctrl_txdma_ch_pcie()
185 			rtw89_write32_set(rtwdev, dma_stop2->addr, dma_stop2->mask);  in rtw89_pci_ctrl_txdma_ch_pcie()
1642 		rtw89_write32_set(rtwdev, info->init_cfg_reg,  in rtw89_pci_ctrl_dma_trx()
1665 		rtw89_write32_set(rtwdev, reg, mask);  in rtw89_pci_ctrl_dma_io()
2069 	rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_DIS_RXDMA_PRE);  in rtw89_pci_rxdma_prefth()
2112 		rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL,  in rtw89_pci_hci_ldo()
2134 		rtw89_write32_set(rtwdev, R_AX_HCI_OPT_CTRL, BIT_WAKE_CTRL);  in rtw89_pci_power_wake()
2144 	rtw89_write32_set(rtwdev, R_AX_PCIE_BG_CLR, B_AX_BG_CLR_ASYNC_M3);  in rtw89_pci_autoload_hang()
2153 	rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_FORCE_PWR_NGAT);  in rtw89_pci_l12_vmain()
2161 	rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2,  in rtw89_pci_gen2_force_ib()
2163 	rtw89_write32_set(rtwdev, R_AX_HCI_BG_CTRL, B_AX_BG_CLR_ASYNC_M3);  in rtw89_pci_gen2_force_ib()
2181 	rtw89_write32_set(rtwdev, R_AX_PCIE_PS_CTRL_V1, B_AX_DMAC0_EXIT_L1_EN);  in rtw89_pci_wd_exit_l1()
2209 	rtw89_write32_set(rtwdev, R_AX_LBC_WATCHDOG, lbc);  in rtw89_pci_set_lbc()
2227 		rtw89_write32_set(rtwdev, R_AX_PCIE_IO_RCY_M1, B_AX_PCIE_IO_RCY_WDT_MODE_M1);  in rtw89_pci_set_io_rcy()
2228 		rtw89_write32_set(rtwdev, R_AX_PCIE_IO_RCY_M2, B_AX_PCIE_IO_RCY_WDT_MODE_M2);  in rtw89_pci_set_io_rcy()
2229 		rtw89_write32_set(rtwdev, R_AX_PCIE_IO_RCY_E0, B_AX_PCIE_IO_RCY_WDT_MODE_E0);  in rtw89_pci_set_io_rcy()
2244 	rtw89_write32_set(rtwdev, R_AX_PCIE_DBG_CTRL,  in rtw89_pci_set_dbg()
2248 		rtw89_write32_set(rtwdev, R_AX_PCIE_EXP_CTRL,  in rtw89_pci_set_dbg()
2257 	rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1,  in rtw89_pci_set_keep_reg()
2275 	rtw89_write32_set(rtwdev, R_AX_TXBD_RWPTR_CLR1, val);  in rtw89_pci_clr_idx_all()
2277 		rtw89_write32_set(rtwdev, txbd_rwptr_clr2,  in rtw89_pci_clr_idx_all()
2279 	rtw89_write32_set(rtwdev, rxbd_rwptr_clr,  in rtw89_pci_clr_idx_all()
2362 			rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_TX_TRUNC_MODE);  in rtw89_pci_mode_op()
2370 			rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_RX_TRUNC_MODE);  in rtw89_pci_mode_op()
2379 		rtw89_write32_set(rtwdev, info->init_cfg_reg, info->rxbd_mode_bit);  in rtw89_pci_mode_op()
2422 		rtw89_write32_set(rtwdev, R_AX_TX_ADDRESS_INFO_MODE_SETTING,  in rtw89_pci_mode_op()
2428 		rtw89_write32_set(rtwdev, R_AX_PKTIN_SETTING, B_AX_WD_ADDR_INFO_LENGTH);  in rtw89_pci_mode_op()
2440 		rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_APP_LTR_IDLE);  in rtw89_pci_ops_deinit()
2491 	rtw89_write32_set(rtwdev, info->dma_stop1.addr, B_AX_STOP_WPDMA);  in rtw89_pci_ops_mac_pre_init()
2544 	rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_HW_EN | B_AX_LTR_EN |  in rtw89_pci_ltr_set()
2592 		rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0,  in rtw89_pci_ltr_set_v1()
2619 		rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_APP_LTR_ACT);  in rtw89_pci_ops_mac_post_init()
2623 		rtw89_write32_set(rtwdev, R_AX_TX_ADDRESS_INFO_MODE_SETTING,  in rtw89_pci_ops_mac_post_init()
3378 		rtw89_write32_set(rtwdev, R_AX_PCIE_LAT_CTRL,  in rtw89_pci_clkreq_set()
3381 			rtw89_write32_set(rtwdev, R_AX_L1_CLK_CTRL,  in rtw89_pci_clkreq_set()
3421 			rtw89_write32_set(rtwdev, R_AX_PCIE_MIX_CFG_V1,  in rtw89_pci_aspm_set()
3512 			rtw89_write32_set(rtwdev, R_AX_PCIE_MIX_CFG_V1,  in rtw89_pci_l1ss_set()
3591 	rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, val32);  in rtw89_pci_rst_bdram()
3686 	rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6);  in rtw89_pci_suspend()
3687 	rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_R_DIS_PRST);  in rtw89_pci_suspend()
3692 		rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1,  in rtw89_pci_suspend()
3720 	rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6);  in rtw89_pci_resume()
3724 		rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL,  in rtw89_pci_resume()
3729 		rtw89_write32_set(rtwdev, R_AX_PCIE_PS_CTRL_V1,  in rtw89_pci_resume()