Lines Matching refs:rtw89_write32_mask

2382 			rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2,  in rtw89_pci_mode_op()
2387 		rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_PCIE_MAX_TXDMA_MASK, tx_burst);  in rtw89_pci_mode_op()
2388 		rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_PCIE_MAX_RXDMA_MASK, rx_burst);  in rtw89_pci_mode_op()
2390 		rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_HAXI_MAX_TXDMA_MASK, tx_burst);  in rtw89_pci_mode_op()
2391 		rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_HAXI_MAX_RXDMA_MASK, rx_burst);  in rtw89_pci_mode_op()
2406 	rtw89_write32_mask(rtwdev, info->exp_ctrl_reg, info->max_tag_num_mask,  in rtw89_pci_mode_op()
2410 		rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, B_AX_WD_ITVL_IDLE,  in rtw89_pci_mode_op()
2412 		rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, B_AX_WD_ITVL_ACT,  in rtw89_pci_mode_op()
2415 		rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_WD_ITVL_IDLE_V1_MASK,  in rtw89_pci_mode_op()
2417 		rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_WD_ITVL_ACT_V1_MASK,  in rtw89_pci_mode_op()
2546 	rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_SPACE_IDX_MASK,  in rtw89_pci_ltr_set()
2548 	rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_IDLE_TIMER_IDX_MASK,  in rtw89_pci_ltr_set()
2550 	rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_1, B_AX_LTR_RX0_TH_MASK, 0x28);  in rtw89_pci_ltr_set()
2551 	rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_1, B_AX_LTR_RX1_TH_MASK, 0x28);  in rtw89_pci_ltr_set()
2594 	rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_IDLE_TIMER_IDX_MASK,  in rtw89_pci_ltr_set_v1()
2596 	rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_1, B_AX_LTR_RX0_TH_MASK, 0x28);  in rtw89_pci_ltr_set_v1()
2597 	rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_1, B_AX_LTR_RX1_TH_MASK, 0x28);  in rtw89_pci_ltr_set_v1()