Lines Matching +full:0 +full:x2140
11 #define MAC_MEM_DUMP_PAGE_SIZE 0x40000
12 #define ADDR_CAM_ENT_SIZE 0x40
13 #define BSSID_CAM_ENT_SIZE 0x08
18 RTW89_DMAC_SEL = 0,
25 RTW89_FWD_DONT_CARE = 0,
41 RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE
53 RTW89_MAC_TAG_NUM_DEF = 0xFE
57 RTW89_MAC_LBC_TMR_8US = 0,
68 RTW89_MAC_LBC_TMR_DEF = 0xFE
72 CPUIO_OP_CMD_GET_1ST_PID = 0,
82 WDE_DLE_PORT_ID_DISPATCH = 0,
92 WDE_DLE_QUEID_TXOK = 0,
100 PLE_DLE_PORT_ID_DISPATCH = 0,
112 PLE_DLE_QUEID_NO_REPORT = 0x0
116 RTW89_MGNT = 0,
122 DLE_DFI_TYPE_FREEPG = 0,
133 WDE_QTAID_HOST_IF = 0,
141 PLE_QTAID_B0_TXPL = 0,
155 DLE_CTRL_TYPE_WDE = 0,
161 MAC_AX_L0_TO_L1_CHIF_IDLE = 0,
172 /* CMAC 0 related */
173 RTW89_DBG_PORT_SEL_PTCL_C0 = 0,
230 #define R_AX_INDIR_ACCESS_ENTRY 0x40000
232 #define AXIDMA_BASE_ADDR 0x18006000
233 #define STA_SCHED_BASE_ADDR 0x18808000
234 #define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000
235 #define SECURITY_CAM_BASE_ADDR 0x18814000
236 #define WOW_CAM_BASE_ADDR 0x18815000
237 #define CMAC_TBL_BASE_ADDR 0x18840000
238 #define ADDR_CAM_BASE_ADDR 0x18850000
239 #define BSSID_CAM_BASE_ADDR 0x18853000
240 #define BA_CAM_BASE_ADDR 0x18854000
241 #define BCN_IE_CAM0_BASE_ADDR 0x18855000
242 #define SHARED_BUF_BASE_ADDR 0x18700000
243 #define DMAC_TBL_BASE_ADDR 0x18800000
244 #define SHCUT_MACHDR_BASE_ADDR 0x18800800
245 #define BCN_IE_CAM1_BASE_ADDR 0x188A0000
246 #define TXD_FIFO_0_BASE_ADDR 0x18856200
247 #define TXD_FIFO_1_BASE_ADDR 0x188A1080
248 #define TXDATA_FIFO_0_BASE_ADDR 0x18856000
249 #define TXDATA_FIFO_1_BASE_ADDR 0x188A1000
250 #define CPU_LOCAL_BASE_ADDR 0x18003000
282 RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0,
309 RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT = 0x6,
310 RTW89_MAC_C2H_FUNC_SCANOFLD_RSP = 0x9,
333 #define RTW89_MAC_AX_COEX_RTK_MODE 0
336 #define RTW89_MAC_AX_COEX_INNER 0
343 #define RTW89_MAC_AX_PLT_LTE_RX BIT(0)
353 RTW89_MAC_BF_RRSC_6M = 0,
388 #define RTW89_R32_EA 0xEAEAEAEA
389 #define RTW89_R32_DEAD 0xDEADBEEF
407 #define S_AX_WDE_PAGE_SEL_64 0
415 #define S_AX_PLE_PAGE_SEL_64 0
419 #define SDIO_LOCAL_BASE_ADDR 0x80000000
421 #define PWR_CMD_WRITE 0
426 #define PWR_INTF_MSK_SDIO BIT(0)
429 #define PWR_INTF_MSK_ALL 0x7
431 #define PWR_BASE_MAC 0
436 #define PWR_CV_MSK_A BIT(0)
444 #define PWR_CV_MSK_ALL 0xFF
446 #define PWR_DELAY_US 0
451 #define SS_TX_LEN_MSK 0x1FFFFF
457 #define TMAC_DBG_SEL_C0 0xA5
458 #define RMAC_DBG_SEL_C0 0xA6
459 #define TRXPTCL_DBG_SEL_C0 0xA7
460 #define TMAC_DBG_SEL_C1 0xB5
461 #define RMAC_DBG_SEL_C1 0xB6
462 #define TRXPTCL_DBG_SEL_C1 0xB7
463 #define FW_PROG_CNTR_DBG_SEL 0xF2
464 #define PCIE_TXDMA_DBG_SEL 0x30
465 #define PCIE_RXDMA_DBG_SEL 0x31
466 #define PCIE_CVT_DBG_SEL 0x32
467 #define PCIE_CXPL_DBG_SEL 0x33
468 #define PCIE_IO_DBG_SEL 0x37
469 #define PCIE_MISC_DBG_SEL 0x38
470 #define PCIE_MISC2_DBG_SEL 0x00
475 #define TRXPTRL_DBG_SEL_TMAC 0
502 #define QLNKTBL_ADDR_INFO_SEL BIT(0)
503 #define QLNKTBL_ADDR_INFO_SEL_0 0
506 #define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0)
540 MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001,
541 MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002,
542 MAC_AX_ERR_L0_RESET_DONE = 0x0003,
543 MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010,
546 MAC_AX_ERR_L1_ERR_DMAC = 0x1000,
547 MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001,
548 MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002,
549 MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010,
550 MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011,
554 MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000,
555 MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010,
556 MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020,
557 MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030,
558 MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040,
559 MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050,
560 MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060,
561 MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070,
564 MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100,
565 MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110,
566 MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120,
567 MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130,
568 MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140,
569 MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150,
570 MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160,
571 MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170,
574 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200,
575 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201,
576 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202,
577 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203,
578 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204,
579 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205,
580 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206,
581 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207,
582 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208,
583 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209,
584 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A,
585 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210,
586 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211,
587 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212,
588 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213,
589 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214,
590 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215,
591 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216,
592 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218,
593 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219,
594 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A,
595 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220,
596 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221,
597 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222,
598 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223,
599 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224,
600 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225,
601 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226,
602 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227,
603 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228,
604 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229,
605 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A,
606 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230,
607 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231,
608 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232,
609 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233,
610 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234,
611 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235,
612 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236,
613 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237,
614 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238,
615 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239,
616 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A,
617 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240,
618 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241,
619 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242,
620 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243,
621 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244,
622 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245,
623 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246,
624 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247,
625 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248,
626 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249,
627 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A,
628 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250,
629 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251,
630 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252,
631 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253,
632 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254,
633 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255,
634 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256,
635 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257,
636 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258,
637 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259,
638 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A,
639 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260,
640 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261,
641 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262,
642 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263,
643 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264,
644 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265,
645 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266,
646 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267,
647 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268,
648 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269,
649 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A,
650 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270,
651 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271,
652 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272,
653 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273,
654 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274,
655 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275,
656 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276,
657 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277,
658 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278,
659 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279,
660 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A,
663 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300,
664 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310,
665 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320,
666 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330,
667 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340,
668 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350,
669 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360,
670 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370,
671 MAC_AX_ERR_L2_RESET_DONE = 0x2400,
672 MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT = 0x2599,
673 MAC_AX_ERR_CPU_EXCEPTION = 0x3000,
674 MAC_AX_ERR_ASSERTION = 0x4000,
676 MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000,
679 MAC_AX_ERR_L1_DISABLE_EN = 0x0001,
680 MAC_AX_ERR_L1_RCVY_EN = 0x0002,
681 MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003,
682 MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004,
683 MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010,
684 MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011,
685 MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012,
686 MAC_AX_ERR_L0_RCVY_EN = 0x0013,
724 return band == 0 ? reg_base : (reg_base + 0x2000); in rtw89_mac_reg_by_idx()
729 return rtw89_mac_reg_by_idx(base + port * 0x40, mac_idx); in rtw89_mac_reg_by_port()
897 return 0; in rtw89_mac_txpwr_read32()
910 return 0; in rtw89_mac_txpwr_write32()
923 return 0; in rtw89_mac_txpwr_write32_mask()
976 XTAL0 = 0x0,
977 XTAL3 = 0x3,
978 XTAL_SI_XTAL_SC_XI = 0x04,
979 #define XTAL_SC_XI_MASK GENMASK(7, 0)
980 XTAL_SI_XTAL_SC_XO = 0x05,
981 #define XTAL_SC_XO_MASK GENMASK(7, 0)
982 XTAL_SI_PWR_CUT = 0x10,
983 #define XTAL_SI_SMALL_PWR_CUT BIT(0)
985 XTAL_SI_XTAL_XMD_2 = 0x24,
987 XTAL_SI_XTAL_XMD_4 = 0x26,
988 #define XTAL_SI_LPS_CAP GENMASK(3, 0)
989 XTAL_SI_CV = 0x41,
990 XTAL_SI_LOW_ADDR = 0x62,
991 #define XTAL_SI_LOW_ADDR_MASK GENMASK(7, 0)
992 XTAL_SI_CTRL = 0x63,
995 #define XTAL_SI_HIGH_ADDR_MASK GENMASK(2, 0)
996 XTAL_SI_READ_VAL = 0x7A,
997 XTAL_SI_WL_RFC_S0 = 0x80,
998 #define XTAL_SI_RF00S_EN GENMASK(2, 0)
999 #define XTAL_SI_RF00 BIT(0)
1000 XTAL_SI_WL_RFC_S1 = 0x81,
1001 #define XTAL_SI_RF10S_EN GENMASK(2, 0)
1002 #define XTAL_SI_RF10 BIT(0)
1003 XTAL_SI_ANAPAR_WL = 0x90,
1011 #define XTAL_SI_PON_WEI BIT(0)
1012 XTAL_SI_SRAM_CTRL = 0xA1,
1013 #define FULL_BIT_MASK GENMASK(7, 0)