Lines Matching refs:rtwdev
36 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, in rtw89_mac_mem_write() argument
41 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr); in rtw89_mac_mem_write()
42 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, val); in rtw89_mac_mem_write()
45 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, in rtw89_mac_mem_read() argument
50 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr); in rtw89_mac_mem_read()
51 return rtw89_read32(rtwdev, R_AX_INDIR_ACCESS_ENTRY); in rtw89_mac_mem_read()
54 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx, in rtw89_mac_check_mac_en() argument
60 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); in rtw89_mac_check_mac_en()
63 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); in rtw89_mac_check_mac_en()
66 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); in rtw89_mac_check_mac_en()
78 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) in rtw89_mac_write_lte() argument
84 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); in rtw89_mac_write_lte()
86 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); in rtw89_mac_write_lte()
88 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); in rtw89_mac_write_lte()
89 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); in rtw89_mac_write_lte()
94 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) in rtw89_mac_read_lte() argument
100 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); in rtw89_mac_read_lte()
102 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); in rtw89_mac_read_lte()
104 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); in rtw89_mac_read_lte()
105 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); in rtw89_mac_read_lte()
111 int dle_dfi_ctrl(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) in dle_dfi_ctrl() argument
133 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); in dle_dfi_ctrl()
137 rtw89_write32(rtwdev, ctrl_reg, ctrl_data); in dle_dfi_ctrl()
140 1, 1000, false, rtwdev, ctrl_reg); in dle_dfi_ctrl()
142 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", in dle_dfi_ctrl()
147 ctrl->out_data = rtw89_read32(rtwdev, data_reg); in dle_dfi_ctrl()
151 static int dle_dfi_quota(struct rtw89_dev *rtwdev, in dle_dfi_quota() argument
160 ret = dle_dfi_ctrl(rtwdev, &ctrl); in dle_dfi_quota()
162 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); in dle_dfi_quota()
171 static int dle_dfi_qempty(struct rtw89_dev *rtwdev, in dle_dfi_qempty() argument
180 ret = dle_dfi_ctrl(rtwdev, &ctrl); in dle_dfi_qempty()
182 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); in dle_dfi_qempty()
190 static void dump_err_status_dispatcher(struct rtw89_dev *rtwdev) in dump_err_status_dispatcher() argument
192 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", in dump_err_status_dispatcher()
193 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); in dump_err_status_dispatcher()
194 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", in dump_err_status_dispatcher()
195 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); in dump_err_status_dispatcher()
196 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", in dump_err_status_dispatcher()
197 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); in dump_err_status_dispatcher()
198 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", in dump_err_status_dispatcher()
199 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); in dump_err_status_dispatcher()
200 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", in dump_err_status_dispatcher()
201 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); in dump_err_status_dispatcher()
202 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", in dump_err_status_dispatcher()
203 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); in dump_err_status_dispatcher()
206 static void rtw89_mac_dump_qta_lost(struct rtw89_dev *rtwdev) in rtw89_mac_dump_qta_lost() argument
217 ret = dle_dfi_qempty(rtwdev, &qempty); in rtw89_mac_dump_qta_lost()
219 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); in rtw89_mac_dump_qta_lost()
221 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); in rtw89_mac_dump_qta_lost()
230 ret = dle_dfi_ctrl(rtwdev, &ctrl); in rtw89_mac_dump_qta_lost()
232 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); in rtw89_mac_dump_qta_lost()
234 rtw89_info(rtwdev, "qidx%d pktcnt = %ld\n", i, in rtw89_mac_dump_qta_lost()
241 ret = dle_dfi_quota(rtwdev, "a); in rtw89_mac_dump_qta_lost()
243 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); in rtw89_mac_dump_qta_lost()
245 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", in rtw89_mac_dump_qta_lost()
248 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); in rtw89_mac_dump_qta_lost()
249 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%lx\n", in rtw89_mac_dump_qta_lost()
251 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%lx\n", in rtw89_mac_dump_qta_lost()
254 dump_err_status_dispatcher(rtwdev); in rtw89_mac_dump_qta_lost()
257 static void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, in rtw89_mac_dump_l0_to_l1() argument
262 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); in rtw89_mac_dump_l0_to_l1()
267 rtw89_info(rtwdev, "quota lost!\n"); in rtw89_mac_dump_l0_to_l1()
268 rtw89_mac_dump_qta_lost(rtwdev); in rtw89_mac_dump_l0_to_l1()
275 static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev, in rtw89_mac_dump_err_status() argument
286 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); in rtw89_mac_dump_err_status()
287 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", in rtw89_mac_dump_err_status()
288 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); in rtw89_mac_dump_err_status()
290 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR); in rtw89_mac_dump_err_status()
291 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR =0x%08x\n", cmac_err); in rtw89_mac_dump_err_status()
292 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); in rtw89_mac_dump_err_status()
293 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR =0x%08x\n", dmac_err); in rtw89_mac_dump_err_status()
296 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG =0x%08x ", in rtw89_mac_dump_err_status()
297 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG)); in rtw89_mac_dump_err_status()
298 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG =0x%08x\n", in rtw89_mac_dump_err_status()
299 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG)); in rtw89_mac_dump_err_status()
303 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR =0x%08x ", in rtw89_mac_dump_err_status()
304 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); in rtw89_mac_dump_err_status()
305 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR =0x%08x\n", in rtw89_mac_dump_err_status()
306 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); in rtw89_mac_dump_err_status()
310 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR =0x%08x\n", in rtw89_mac_dump_err_status()
311 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); in rtw89_mac_dump_err_status()
312 rtw89_info(rtwdev, "SEC_local_Register 0x9D00 =0x%08x\n", in rtw89_mac_dump_err_status()
313 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); in rtw89_mac_dump_err_status()
314 rtw89_info(rtwdev, "SEC_local_Register 0x9D04 =0x%08x\n", in rtw89_mac_dump_err_status()
315 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); in rtw89_mac_dump_err_status()
316 rtw89_info(rtwdev, "SEC_local_Register 0x9D10 =0x%08x\n", in rtw89_mac_dump_err_status()
317 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); in rtw89_mac_dump_err_status()
318 rtw89_info(rtwdev, "SEC_local_Register 0x9D14 =0x%08x\n", in rtw89_mac_dump_err_status()
319 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); in rtw89_mac_dump_err_status()
320 rtw89_info(rtwdev, "SEC_local_Register 0x9D18 =0x%08x\n", in rtw89_mac_dump_err_status()
321 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); in rtw89_mac_dump_err_status()
322 rtw89_info(rtwdev, "SEC_local_Register 0x9D20 =0x%08x\n", in rtw89_mac_dump_err_status()
323 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); in rtw89_mac_dump_err_status()
324 rtw89_info(rtwdev, "SEC_local_Register 0x9D24 =0x%08x\n", in rtw89_mac_dump_err_status()
325 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); in rtw89_mac_dump_err_status()
326 rtw89_info(rtwdev, "SEC_local_Register 0x9D28 =0x%08x\n", in rtw89_mac_dump_err_status()
327 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); in rtw89_mac_dump_err_status()
328 rtw89_info(rtwdev, "SEC_local_Register 0x9D2C =0x%08x\n", in rtw89_mac_dump_err_status()
329 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); in rtw89_mac_dump_err_status()
333 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR =0x%08x ", in rtw89_mac_dump_err_status()
334 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); in rtw89_mac_dump_err_status()
335 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR =0x%08x\n", in rtw89_mac_dump_err_status()
336 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); in rtw89_mac_dump_err_status()
337 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR =0x%08x ", in rtw89_mac_dump_err_status()
338 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); in rtw89_mac_dump_err_status()
339 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR =0x%08x\n", in rtw89_mac_dump_err_status()
340 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); in rtw89_mac_dump_err_status()
344 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR =0x%08x ", in rtw89_mac_dump_err_status()
345 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); in rtw89_mac_dump_err_status()
346 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR= 0x%08x\n", in rtw89_mac_dump_err_status()
347 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); in rtw89_mac_dump_err_status()
351 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x ", in rtw89_mac_dump_err_status()
352 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); in rtw89_mac_dump_err_status()
353 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", in rtw89_mac_dump_err_status()
354 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); in rtw89_mac_dump_err_status()
355 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x ", in rtw89_mac_dump_err_status()
356 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); in rtw89_mac_dump_err_status()
357 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", in rtw89_mac_dump_err_status()
358 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); in rtw89_mac_dump_err_status()
359 dump_err_status_dispatcher(rtwdev); in rtw89_mac_dump_err_status()
363 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", in rtw89_mac_dump_err_status()
364 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); in rtw89_mac_dump_err_status()
365 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", in rtw89_mac_dump_err_status()
366 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); in rtw89_mac_dump_err_status()
370 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x ", in rtw89_mac_dump_err_status()
371 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); in rtw89_mac_dump_err_status()
372 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", in rtw89_mac_dump_err_status()
373 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); in rtw89_mac_dump_err_status()
374 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x ", in rtw89_mac_dump_err_status()
375 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); in rtw89_mac_dump_err_status()
376 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", in rtw89_mac_dump_err_status()
377 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); in rtw89_mac_dump_err_status()
378 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", in rtw89_mac_dump_err_status()
379 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); in rtw89_mac_dump_err_status()
380 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", in rtw89_mac_dump_err_status()
381 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); in rtw89_mac_dump_err_status()
382 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", in rtw89_mac_dump_err_status()
383 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); in rtw89_mac_dump_err_status()
384 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", in rtw89_mac_dump_err_status()
385 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); in rtw89_mac_dump_err_status()
386 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", in rtw89_mac_dump_err_status()
387 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); in rtw89_mac_dump_err_status()
388 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", in rtw89_mac_dump_err_status()
389 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); in rtw89_mac_dump_err_status()
390 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", in rtw89_mac_dump_err_status()
391 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); in rtw89_mac_dump_err_status()
392 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", in rtw89_mac_dump_err_status()
393 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); in rtw89_mac_dump_err_status()
394 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", in rtw89_mac_dump_err_status()
395 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); in rtw89_mac_dump_err_status()
396 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", in rtw89_mac_dump_err_status()
397 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); in rtw89_mac_dump_err_status()
398 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", in rtw89_mac_dump_err_status()
399 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); in rtw89_mac_dump_err_status()
400 dump_err_status_dispatcher(rtwdev); in rtw89_mac_dump_err_status()
404 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR =0x%08x ", in rtw89_mac_dump_err_status()
405 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); in rtw89_mac_dump_err_status()
406 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR =0x%08x\n", in rtw89_mac_dump_err_status()
407 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); in rtw89_mac_dump_err_status()
408 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR =0x%08x ", in rtw89_mac_dump_err_status()
409 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); in rtw89_mac_dump_err_status()
410 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR =0x%08x\n", in rtw89_mac_dump_err_status()
411 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); in rtw89_mac_dump_err_status()
415 dump_err_status_dispatcher(rtwdev); in rtw89_mac_dump_err_status()
418 rtw89_info(rtwdev, "R_AX_CPUIO_ERR_IMR=0x%08x ", in rtw89_mac_dump_err_status()
419 rtw89_read32(rtwdev, R_AX_CPUIO_ERR_IMR)); in rtw89_mac_dump_err_status()
420 rtw89_info(rtwdev, "R_AX_CPUIO_ERR_ISR=0x%08x\n", in rtw89_mac_dump_err_status()
421 rtw89_read32(rtwdev, R_AX_CPUIO_ERR_ISR)); in rtw89_mac_dump_err_status()
425 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", in rtw89_mac_dump_err_status()
426 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); in rtw89_mac_dump_err_status()
430 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR=0x%08x ", in rtw89_mac_dump_err_status()
431 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR)); in rtw89_mac_dump_err_status()
432 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR=0x%04x\n", in rtw89_mac_dump_err_status()
433 rtw89_read16(rtwdev, R_AX_SCHEDULE_ERR_ISR)); in rtw89_mac_dump_err_status()
437 rtw89_info(rtwdev, "R_AX_PTCL_IMR0=0x%08x ", in rtw89_mac_dump_err_status()
438 rtw89_read32(rtwdev, R_AX_PTCL_IMR0)); in rtw89_mac_dump_err_status()
439 rtw89_info(rtwdev, "R_AX_PTCL_ISR0=0x%08x\n", in rtw89_mac_dump_err_status()
440 rtw89_read32(rtwdev, R_AX_PTCL_ISR0)); in rtw89_mac_dump_err_status()
444 rtw89_info(rtwdev, "R_AX_DLE_CTRL=0x%08x\n", in rtw89_mac_dump_err_status()
445 rtw89_read32(rtwdev, R_AX_DLE_CTRL)); in rtw89_mac_dump_err_status()
449 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR=0x%08x\n", in rtw89_mac_dump_err_status()
450 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR)); in rtw89_mac_dump_err_status()
454 rtw89_info(rtwdev, "R_AX_TXPWR_IMR=0x%08x ", in rtw89_mac_dump_err_status()
455 rtw89_read32(rtwdev, R_AX_TXPWR_IMR)); in rtw89_mac_dump_err_status()
456 rtw89_info(rtwdev, "R_AX_TXPWR_ISR=0x%08x\n", in rtw89_mac_dump_err_status()
457 rtw89_read32(rtwdev, R_AX_TXPWR_ISR)); in rtw89_mac_dump_err_status()
461 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL=0x%08x ", in rtw89_mac_dump_err_status()
462 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL)); in rtw89_mac_dump_err_status()
463 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR=0x%08x\n", in rtw89_mac_dump_err_status()
464 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR)); in rtw89_mac_dump_err_status()
468 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR=0x%08x ", in rtw89_mac_dump_err_status()
469 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR)); in rtw89_mac_dump_err_status()
470 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL=0x%08x\n", in rtw89_mac_dump_err_status()
471 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL)); in rtw89_mac_dump_err_status()
474 rtwdev->hci.ops->dump_err_status(rtwdev); in rtw89_mac_dump_err_status()
477 rtw89_mac_dump_l0_to_l1(rtwdev, err); in rtw89_mac_dump_err_status()
479 rtw89_info(rtwdev, "<---\n"); in rtw89_mac_dump_err_status()
482 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) in rtw89_mac_get_err_status() argument
488 false, rtwdev, R_AX_HALT_C2H_CTRL); in rtw89_mac_get_err_status()
490 rtw89_warn(rtwdev, "Polling FW err status fail\n"); in rtw89_mac_get_err_status()
494 err = rtw89_read32(rtwdev, R_AX_HALT_C2H); in rtw89_mac_get_err_status()
495 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); in rtw89_mac_get_err_status()
503 rtw89_fw_st_dbg_dump(rtwdev); in rtw89_mac_get_err_status()
504 rtw89_mac_dump_err_status(rtwdev, err); in rtw89_mac_get_err_status()
510 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) in rtw89_mac_set_err_status() argument
516 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); in rtw89_mac_set_err_status()
521 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); in rtw89_mac_set_err_status()
523 rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); in rtw89_mac_set_err_status()
527 rtw89_write32(rtwdev, R_AX_HALT_H2C, err); in rtw89_mac_set_err_status()
528 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); in rtw89_mac_set_err_status()
534 static int hfc_reset_param(struct rtw89_dev *rtwdev) in hfc_reset_param() argument
536 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; in hfc_reset_param()
538 u8 qta_mode = rtwdev->mac.dle_info.qta_mode; in hfc_reset_param()
540 switch (rtwdev->hci.type) { in hfc_reset_param()
542 param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; in hfc_reset_param()
554 rtwdev->hal.sw_amsdu_max_size = in hfc_reset_param()
568 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) in hfc_ch_cfg_chk() argument
570 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; in hfc_ch_cfg_chk()
587 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) in hfc_pub_info_chk() argument
589 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; in hfc_pub_info_chk()
594 if (rtwdev->chip->chip_id == RTL8852A) in hfc_pub_info_chk()
603 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) in hfc_pub_cfg_chk() argument
605 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; in hfc_pub_cfg_chk()
614 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) in hfc_ch_ctrl() argument
616 const struct rtw89_chip_info *chip = rtwdev->chip; in hfc_ch_ctrl()
618 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; in hfc_ch_ctrl()
623 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); in hfc_ch_ctrl()
627 ret = hfc_ch_cfg_chk(rtwdev, ch); in hfc_ch_ctrl()
637 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); in hfc_ch_ctrl()
642 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) in hfc_upd_ch_info() argument
644 const struct rtw89_chip_info *chip = rtwdev->chip; in hfc_upd_ch_info()
646 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; in hfc_upd_ch_info()
652 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); in hfc_upd_ch_info()
659 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); in hfc_upd_ch_info()
669 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) in hfc_pub_ctrl() argument
671 const struct rtw89_chip_info *chip = rtwdev->chip; in hfc_pub_ctrl()
673 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; in hfc_pub_ctrl()
677 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); in hfc_pub_ctrl()
681 ret = hfc_pub_cfg_chk(rtwdev); in hfc_pub_ctrl()
687 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); in hfc_pub_ctrl()
690 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); in hfc_pub_ctrl()
695 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) in hfc_upd_mix_info() argument
697 const struct rtw89_chip_info *chip = rtwdev->chip; in hfc_upd_mix_info()
699 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; in hfc_upd_mix_info()
706 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); in hfc_upd_mix_info()
710 val = rtw89_read32(rtwdev, regs->pub_page_info1); in hfc_upd_mix_info()
713 val = rtw89_read32(rtwdev, regs->pub_page_info3); in hfc_upd_mix_info()
717 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), in hfc_upd_mix_info()
720 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), in hfc_upd_mix_info()
723 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); in hfc_upd_mix_info()
736 val = rtw89_read32(rtwdev, regs->ch_page_ctrl); in hfc_upd_mix_info()
740 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); in hfc_upd_mix_info()
743 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); in hfc_upd_mix_info()
747 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); in hfc_upd_mix_info()
750 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); in hfc_upd_mix_info()
754 ret = hfc_pub_info_chk(rtwdev); in hfc_upd_mix_info()
761 static void hfc_h2c_cfg(struct rtw89_dev *rtwdev) in hfc_h2c_cfg() argument
763 const struct rtw89_chip_info *chip = rtwdev->chip; in hfc_h2c_cfg()
765 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; in hfc_h2c_cfg()
770 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); in hfc_h2c_cfg()
772 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, in hfc_h2c_cfg()
777 static void hfc_mix_cfg(struct rtw89_dev *rtwdev) in hfc_mix_cfg() argument
779 const struct rtw89_chip_info *chip = rtwdev->chip; in hfc_mix_cfg()
781 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; in hfc_mix_cfg()
788 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); in hfc_mix_cfg()
791 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); in hfc_mix_cfg()
797 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); in hfc_mix_cfg()
799 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), in hfc_mix_cfg()
809 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); in hfc_mix_cfg()
812 static void hfc_func_en(struct rtw89_dev *rtwdev, bool en, bool h2c_en) in hfc_func_en() argument
814 const struct rtw89_chip_info *chip = rtwdev->chip; in hfc_func_en()
816 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; in hfc_func_en()
819 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); in hfc_func_en()
825 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); in hfc_func_en()
828 static int hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) in hfc_init() argument
830 const struct rtw89_chip_info *chip = rtwdev->chip; in hfc_init()
836 ret = hfc_reset_param(rtwdev); in hfc_init()
840 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); in hfc_init()
844 hfc_func_en(rtwdev, false, false); in hfc_init()
847 hfc_h2c_cfg(rtwdev); in hfc_init()
848 hfc_func_en(rtwdev, en, h2c_en); in hfc_init()
855 ret = hfc_ch_ctrl(rtwdev, ch); in hfc_init()
860 ret = hfc_pub_ctrl(rtwdev); in hfc_init()
864 hfc_mix_cfg(rtwdev); in hfc_init()
866 hfc_func_en(rtwdev, en, h2c_en); in hfc_init()
872 ret = hfc_upd_ch_info(rtwdev, ch); in hfc_init()
876 ret = hfc_upd_mix_info(rtwdev); in hfc_init()
882 static int pwr_cmd_poll(struct rtw89_dev *rtwdev, in pwr_cmd_poll() argument
891 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); in pwr_cmd_poll()
896 rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); in pwr_cmd_poll()
897 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); in pwr_cmd_poll()
898 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); in pwr_cmd_poll()
903 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, in rtw89_mac_sub_pwr_seq() argument
922 val = rtw89_read8(rtwdev, addr); in rtw89_mac_sub_pwr_seq()
926 rtw89_write8(rtwdev, addr, val); in rtw89_mac_sub_pwr_seq()
929 if (pwr_cmd_poll(rtwdev, cur_cfg)) in rtw89_mac_sub_pwr_seq()
946 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, in rtw89_mac_pwr_seq() argument
952 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), in rtw89_mac_pwr_seq()
962 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) in rtw89_mac_get_req_pwr_state() argument
966 switch (rtwdev->ps_mode) { in rtw89_mac_get_req_pwr_state()
983 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, in rtw89_mac_send_rpwm() argument
989 spin_lock_bh(&rtwdev->rpwm_lock); in rtw89_mac_send_rpwm()
991 request = rtw89_read16(rtwdev, R_AX_RPWM); in rtw89_mac_send_rpwm()
998 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & in rtw89_mac_send_rpwm()
1001 rtwdev->mac.rpwm_seq_num); in rtw89_mac_send_rpwm()
1006 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); in rtw89_mac_send_rpwm()
1008 spin_unlock_bh(&rtwdev->rpwm_lock); in rtw89_mac_send_rpwm()
1011 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, in rtw89_mac_check_cpwm_state() argument
1026 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) in rtw89_mac_check_cpwm_state()
1037 rpwm_req_num = rtwdev->mac.rpwm_seq_num; in rtw89_mac_check_cpwm_state()
1038 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, in rtw89_mac_check_cpwm_state()
1044 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & in rtw89_mac_check_cpwm_state()
1047 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); in rtw89_mac_check_cpwm_state()
1048 if (cpwm_seq != rtwdev->mac.cpwm_seq_num) in rtw89_mac_check_cpwm_state()
1051 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); in rtw89_mac_check_cpwm_state()
1058 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) in rtw89_mac_power_mode_change() argument
1066 state = rtw89_mac_get_req_pwr_state(rtwdev); in rtw89_mac_power_mode_change()
1071 rtw89_mac_send_rpwm(rtwdev, state, false); in rtw89_mac_power_mode_change()
1074 rtwdev, state); in rtw89_mac_power_mode_change()
1079 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", in rtw89_mac_power_mode_change()
1082 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, in rtw89_mac_power_mode_change()
1088 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) in rtw89_mac_notify_wake() argument
1092 state = rtw89_mac_get_req_pwr_state(rtwdev); in rtw89_mac_notify_wake()
1093 rtw89_mac_send_rpwm(rtwdev, state, true); in rtw89_mac_notify_wake()
1096 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) in rtw89_mac_power_switch() argument
1099 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_mac_power_switch()
1101 int (*cfg_func)(struct rtw89_dev *rtwdev); in rtw89_mac_power_switch()
1113 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) in rtw89_mac_power_switch()
1114 __rtw89_leave_ps_mode(rtwdev); in rtw89_mac_power_switch()
1116 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); in rtw89_mac_power_switch()
1118 rtw89_err(rtwdev, "MAC has already powered on\n"); in rtw89_mac_power_switch()
1122 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); in rtw89_mac_power_switch()
1127 set_bit(RTW89_FLAG_POWERON, rtwdev->flags); in rtw89_mac_power_switch()
1128 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); in rtw89_mac_power_switch()
1130 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); in rtw89_mac_power_switch()
1131 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); in rtw89_mac_power_switch()
1132 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); in rtw89_mac_power_switch()
1133 rtw89_set_entity_state(rtwdev, false); in rtw89_mac_power_switch()
1140 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) in rtw89_mac_pwr_off() argument
1142 rtw89_mac_power_switch(rtwdev, false); in rtw89_mac_pwr_off()
1145 static int cmac_func_en(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) in cmac_func_en() argument
1168 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); in cmac_func_en()
1169 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, in cmac_func_en()
1171 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, in cmac_func_en()
1174 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); in cmac_func_en()
1175 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); in cmac_func_en()
1177 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); in cmac_func_en()
1178 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); in cmac_func_en()
1180 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, in cmac_func_en()
1182 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, in cmac_func_en()
1184 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); in cmac_func_en()
1191 static int dmac_func_en(struct rtw89_dev *rtwdev) in dmac_func_en() argument
1193 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; in dmac_func_en()
1212 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); in dmac_func_en()
1218 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); in dmac_func_en()
1223 static int chip_func_en(struct rtw89_dev *rtwdev) in chip_func_en() argument
1225 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; in chip_func_en()
1228 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, in chip_func_en()
1234 static int rtw89_mac_sys_init(struct rtw89_dev *rtwdev) in rtw89_mac_sys_init() argument
1238 ret = dmac_func_en(rtwdev); in rtw89_mac_sys_init()
1242 ret = cmac_func_en(rtwdev, 0, true); in rtw89_mac_sys_init()
1246 ret = chip_func_en(rtwdev); in rtw89_mac_sys_init()
1310 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, in get_dle_mem_cfg() argument
1313 struct rtw89_mac_info *mac = &rtwdev->mac; in get_dle_mem_cfg()
1316 cfg = &rtwdev->chip->dle_mem[mode]; in get_dle_mem_cfg()
1321 rtw89_warn(rtwdev, "qta mode unmatch!\n"); in get_dle_mem_cfg()
1341 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, in dle_expected_used_size() argument
1344 u32 size = rtwdev->chip->fifo_size; in dle_expected_used_size()
1347 size -= rtwdev->chip->dle_scc_rsvd_size; in dle_expected_used_size()
1352 static void dle_func_en(struct rtw89_dev *rtwdev, bool enable) in dle_func_en() argument
1355 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, in dle_func_en()
1358 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, in dle_func_en()
1362 static void dle_clk_en(struct rtw89_dev *rtwdev, bool enable) in dle_clk_en() argument
1365 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, in dle_clk_en()
1368 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, in dle_clk_en()
1372 static int dle_mix_cfg(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) in dle_mix_cfg() argument
1378 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); in dle_mix_cfg()
1392 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); in dle_mix_cfg()
1399 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); in dle_mix_cfg()
1401 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); in dle_mix_cfg()
1409 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); in dle_mix_cfg()
1424 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); in dle_mix_cfg()
1436 rtw89_write32(rtwdev, \
1443 static void wde_quota_cfg(struct rtw89_dev *rtwdev, in wde_quota_cfg() argument
1458 static void ple_quota_cfg(struct rtw89_dev *rtwdev, in ple_quota_cfg() argument
1475 if (rtwdev->chip->chip_id == RTL8852C) in ple_quota_cfg()
1481 static void dle_quota_cfg(struct rtw89_dev *rtwdev, in dle_quota_cfg() argument
1485 wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); in dle_quota_cfg()
1486 ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); in dle_quota_cfg()
1489 static int dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, in dle_init() argument
1497 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); in dle_init()
1501 cfg = get_dle_mem_cfg(rtwdev, mode); in dle_init()
1503 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); in dle_init()
1509 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); in dle_init()
1511 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", in dle_init()
1520 dle_expected_used_size(rtwdev, mode)) { in dle_init()
1521 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); in dle_init()
1526 dle_func_en(rtwdev, false); in dle_init()
1527 dle_clk_en(rtwdev, true); in dle_init()
1529 ret = dle_mix_cfg(rtwdev, cfg); in dle_init()
1531 rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); in dle_init()
1534 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); in dle_init()
1536 dle_func_en(rtwdev, true); in dle_init()
1540 2000, false, rtwdev, R_AX_WDE_INI_STATUS); in dle_init()
1542 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); in dle_init()
1548 2000, false, rtwdev, R_AX_PLE_INI_STATUS); in dle_init()
1550 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); in dle_init()
1556 dle_func_en(rtwdev, false); in dle_init()
1557 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", in dle_init()
1558 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); in dle_init()
1559 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", in dle_init()
1560 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); in dle_init()
1565 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, in preload_init_set() argument
1574 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); in preload_init_set()
1575 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); in preload_init_set()
1580 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); in preload_init_set()
1581 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); in preload_init_set()
1586 static bool is_qta_poh(struct rtw89_dev *rtwdev) in is_qta_poh() argument
1588 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; in is_qta_poh()
1591 static int preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, in preload_init() argument
1594 const struct rtw89_chip_info *chip = rtwdev->chip; in preload_init()
1596 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || !is_qta_poh(rtwdev)) in preload_init()
1599 return preload_init_set(rtwdev, mac_idx, mode); in preload_init()
1602 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) in dle_is_txq_empty() argument
1620 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); in dle_is_txq_empty()
1628 static void _patch_ss2f_path(struct rtw89_dev *rtwdev) in _patch_ss2f_path() argument
1630 const struct rtw89_chip_info *chip = rtwdev->chip; in _patch_ss2f_path()
1635 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, in _patch_ss2f_path()
1639 static int sta_sch_init(struct rtw89_dev *rtwdev) in sta_sch_init() argument
1645 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); in sta_sch_init()
1649 val = rtw89_read8(rtwdev, R_AX_SS_CTRL); in sta_sch_init()
1651 rtw89_write8(rtwdev, R_AX_SS_CTRL, val); in sta_sch_init()
1654 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); in sta_sch_init()
1656 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); in sta_sch_init()
1660 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); in sta_sch_init()
1661 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); in sta_sch_init()
1663 _patch_ss2f_path(rtwdev); in sta_sch_init()
1668 static int mpdu_proc_init(struct rtw89_dev *rtwdev) in mpdu_proc_init() argument
1672 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); in mpdu_proc_init()
1676 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); in mpdu_proc_init()
1677 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); in mpdu_proc_init()
1678 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, in mpdu_proc_init()
1680 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); in mpdu_proc_init()
1685 static int sec_eng_init(struct rtw89_dev *rtwdev) in sec_eng_init() argument
1687 const struct rtw89_chip_info *chip = rtwdev->chip; in sec_eng_init()
1691 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); in sec_eng_init()
1695 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); in sec_eng_init()
1703 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); in sec_eng_init()
1706 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); in sec_eng_init()
1710 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); in sec_eng_init()
1713 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, in sec_eng_init()
1719 static int dmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) in dmac_init() argument
1723 ret = dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); in dmac_init()
1725 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); in dmac_init()
1729 ret = preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); in dmac_init()
1731 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); in dmac_init()
1735 ret = hfc_init(rtwdev, true, true, true); in dmac_init()
1737 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); in dmac_init()
1741 ret = sta_sch_init(rtwdev); in dmac_init()
1743 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); in dmac_init()
1747 ret = mpdu_proc_init(rtwdev); in dmac_init()
1749 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); in dmac_init()
1753 ret = sec_eng_init(rtwdev); in dmac_init()
1755 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); in dmac_init()
1762 static int addr_cam_init(struct rtw89_dev *rtwdev, u8 mac_idx) in addr_cam_init() argument
1768 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in addr_cam_init()
1774 val = rtw89_read32(rtwdev, reg); in addr_cam_init()
1777 rtw89_write32(rtwdev, reg, val); in addr_cam_init()
1780 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); in addr_cam_init()
1782 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); in addr_cam_init()
1789 static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx) in scheduler_init() argument
1795 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in scheduler_init()
1800 if (rtwdev->chip->chip_id == RTL8852C) in scheduler_init()
1801 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, in scheduler_init()
1804 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, in scheduler_init()
1807 if (rtwdev->chip->chip_id == RTL8852B) { in scheduler_init()
1809 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); in scheduler_init()
1813 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); in scheduler_init()
1816 if (rtwdev->chip->chip_id == RTL8852C) { in scheduler_init()
1817 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, in scheduler_init()
1820 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, in scheduler_init()
1823 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, in scheduler_init()
1830 static int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev, in rtw89_mac_typ_fltr_opt() argument
1849 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); in rtw89_mac_typ_fltr_opt()
1864 rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); in rtw89_mac_typ_fltr_opt()
1867 rtw89_write32(rtwdev, reg, val); in rtw89_mac_typ_fltr_opt()
1872 static int rx_fltr_init(struct rtw89_dev *rtwdev, u8 mac_idx) in rx_fltr_init() argument
1877 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in rx_fltr_init()
1882 ret = rtw89_mac_typ_fltr_opt(rtwdev, i, RTW89_FWD_TO_HOST, in rx_fltr_init()
1887 mac_ftlr = rtwdev->hal.rx_fltr; in rx_fltr_init()
1892 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx), in rx_fltr_init()
1894 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx), in rx_fltr_init()
1900 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) in _patch_dis_resp_chk() argument
1911 switch (rtwdev->chip->chip_id) { in _patch_dis_resp_chk()
1915 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; in _patch_dis_resp_chk()
1916 rtw89_write32(rtwdev, reg, val32); in _patch_dis_resp_chk()
1919 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; in _patch_dis_resp_chk()
1920 rtw89_write32(rtwdev, reg, val32); in _patch_dis_resp_chk()
1924 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; in _patch_dis_resp_chk()
1925 rtw89_write32(rtwdev, reg, val32); in _patch_dis_resp_chk()
1928 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; in _patch_dis_resp_chk()
1929 rtw89_write32(rtwdev, reg, val32); in _patch_dis_resp_chk()
1934 static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx) in cca_ctrl_init() argument
1939 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in cca_ctrl_init()
1944 val = rtw89_read32(rtwdev, reg); in cca_ctrl_init()
1959 rtw89_write32(rtwdev, reg, val); in cca_ctrl_init()
1961 _patch_dis_resp_chk(rtwdev, mac_idx); in cca_ctrl_init()
1966 static int nav_ctrl_init(struct rtw89_dev *rtwdev) in nav_ctrl_init() argument
1968 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | in nav_ctrl_init()
1971 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); in nav_ctrl_init()
1976 static int spatial_reuse_init(struct rtw89_dev *rtwdev, u8 mac_idx) in spatial_reuse_init() argument
1981 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in spatial_reuse_init()
1985 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); in spatial_reuse_init()
1990 static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) in tmac_init() argument
1995 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in tmac_init()
2000 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); in tmac_init()
2003 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); in tmac_init()
2006 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); in tmac_init()
2007 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); in tmac_init()
2012 static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) in trxptcl_init() argument
2014 const struct rtw89_chip_info *chip = rtwdev->chip; in trxptcl_init()
2019 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in trxptcl_init()
2024 val = rtw89_read32(rtwdev, reg); in trxptcl_init()
2028 switch (rtwdev->chip->chip_id) { in trxptcl_init()
2041 rtw89_write32(rtwdev, reg, val); in trxptcl_init()
2044 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); in trxptcl_init()
2047 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); in trxptcl_init()
2049 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); in trxptcl_init()
2054 static void rst_bacam(struct rtw89_dev *rtwdev) in rst_bacam() argument
2059 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, in rst_bacam()
2064 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); in rst_bacam()
2066 rtw89_warn(rtwdev, "failed to reset BA CAM\n"); in rst_bacam()
2069 static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) in rmac_init() argument
2080 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in rmac_init()
2085 rst_bacam(rtwdev); in rmac_init()
2088 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); in rmac_init()
2091 val = rtw89_read16(rtwdev, reg); in rmac_init()
2096 rtw89_write16(rtwdev, reg, val); in rmac_init()
2099 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); in rmac_init()
2103 rx_qta = rtwdev->mac.dle_info.c0_rx_qta; in rmac_init()
2105 rx_qta = rtwdev->mac.dle_info.c1_rx_qta; in rmac_init()
2107 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; in rmac_init()
2110 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); in rmac_init()
2112 if (rtwdev->chip->chip_id == RTL8852A && in rmac_init()
2113 rtwdev->hal.cv == CHIP_CBV) { in rmac_init()
2114 rtw89_write16_mask(rtwdev, in rmac_init()
2117 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx), in rmac_init()
2122 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); in rmac_init()
2127 static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx) in cmac_com_init() argument
2129 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; in cmac_com_init()
2133 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in cmac_com_init()
2138 val = rtw89_read32(rtwdev, reg); in cmac_com_init()
2142 rtw89_write32(rtwdev, reg, val); in cmac_com_init()
2146 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); in cmac_com_init()
2152 static bool is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) in is_qta_dbcc() argument
2156 cfg = get_dle_mem_cfg(rtwdev, mode); in is_qta_dbcc()
2158 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); in is_qta_dbcc()
2165 static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) in ptcl_init() argument
2170 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in ptcl_init()
2174 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { in ptcl_init()
2176 val = rtw89_read32(rtwdev, reg); in ptcl_init()
2182 rtw89_write32(rtwdev, reg, val); in ptcl_init()
2185 val = rtw89_read32(rtwdev, reg); in ptcl_init()
2188 rtw89_write32(rtwdev, reg, val); in ptcl_init()
2192 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, in ptcl_init()
2194 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, in ptcl_init()
2198 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, in ptcl_init()
2201 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, in ptcl_init()
2208 static int cmac_dma_init(struct rtw89_dev *rtwdev, u8 mac_idx) in cmac_dma_init() argument
2210 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; in cmac_dma_init()
2217 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in cmac_dma_init()
2222 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); in cmac_dma_init()
2227 static int cmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) in cmac_init() argument
2231 ret = scheduler_init(rtwdev, mac_idx); in cmac_init()
2233 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); in cmac_init()
2237 ret = addr_cam_init(rtwdev, mac_idx); in cmac_init()
2239 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, in cmac_init()
2244 ret = rx_fltr_init(rtwdev, mac_idx); in cmac_init()
2246 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, in cmac_init()
2251 ret = cca_ctrl_init(rtwdev, mac_idx); in cmac_init()
2253 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, in cmac_init()
2258 ret = nav_ctrl_init(rtwdev); in cmac_init()
2260 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, in cmac_init()
2265 ret = spatial_reuse_init(rtwdev, mac_idx); in cmac_init()
2267 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", in cmac_init()
2272 ret = tmac_init(rtwdev, mac_idx); in cmac_init()
2274 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); in cmac_init()
2278 ret = trxptcl_init(rtwdev, mac_idx); in cmac_init()
2280 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); in cmac_init()
2284 ret = rmac_init(rtwdev, mac_idx); in cmac_init()
2286 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); in cmac_init()
2290 ret = cmac_com_init(rtwdev, mac_idx); in cmac_init()
2292 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); in cmac_init()
2296 ret = ptcl_init(rtwdev, mac_idx); in cmac_init()
2298 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); in cmac_init()
2302 ret = cmac_dma_init(rtwdev, mac_idx); in cmac_init()
2304 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); in cmac_init()
2311 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, in rtw89_mac_read_phycap() argument
2320 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); in rtw89_mac_read_phycap()
2330 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) in rtw89_mac_setup_phycap() argument
2332 struct rtw89_hal *hal = &rtwdev->hal; in rtw89_mac_setup_phycap()
2333 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_mac_setup_phycap()
2341 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); in rtw89_mac_setup_phycap()
2363 rtw89_debug(rtwdev, RTW89_DBG_FW, in rtw89_mac_setup_phycap()
2367 rtw89_debug(rtwdev, RTW89_DBG_FW, in rtw89_mac_setup_phycap()
2370 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); in rtw89_mac_setup_phycap()
2375 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, in rtw89_hw_sch_tx_en_h2c() argument
2390 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); in rtw89_hw_sch_tx_en_h2c()
2400 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, in rtw89_set_hw_sch_tx_en() argument
2407 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in rtw89_set_hw_sch_tx_en()
2411 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) in rtw89_set_hw_sch_tx_en()
2412 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, in rtw89_set_hw_sch_tx_en()
2415 val = rtw89_read16(rtwdev, reg); in rtw89_set_hw_sch_tx_en()
2417 rtw89_write16(rtwdev, reg, val); in rtw89_set_hw_sch_tx_en()
2422 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, in rtw89_set_hw_sch_tx_en_v1() argument
2429 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in rtw89_set_hw_sch_tx_en_v1()
2433 val = rtw89_read32(rtwdev, reg); in rtw89_set_hw_sch_tx_en_v1()
2435 rtw89_write32(rtwdev, reg, val); in rtw89_set_hw_sch_tx_en_v1()
2440 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, in rtw89_mac_stop_sch_tx() argument
2445 *tx_en = rtw89_read16(rtwdev, in rtw89_mac_stop_sch_tx()
2450 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, in rtw89_mac_stop_sch_tx()
2456 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, in rtw89_mac_stop_sch_tx()
2462 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, in rtw89_mac_stop_sch_tx()
2468 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, in rtw89_mac_stop_sch_tx()
2481 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, in rtw89_mac_stop_sch_tx_v1() argument
2486 *tx_en = rtw89_read32(rtwdev, in rtw89_mac_stop_sch_tx_v1()
2491 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, in rtw89_mac_stop_sch_tx_v1()
2497 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, in rtw89_mac_stop_sch_tx_v1()
2503 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, in rtw89_mac_stop_sch_tx_v1()
2509 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, in rtw89_mac_stop_sch_tx_v1()
2522 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) in rtw89_mac_resume_sch_tx() argument
2526 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); in rtw89_mac_resume_sch_tx()
2534 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) in rtw89_mac_resume_sch_tx_v1() argument
2538 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, in rtw89_mac_resume_sch_tx_v1()
2547 u16 rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, bool wd) in rtw89_mac_dle_buf_req() argument
2555 rtw89_write32(rtwdev, reg, val); in rtw89_mac_dle_buf_req()
2560 1, 2000, false, rtwdev, reg); in rtw89_mac_dle_buf_req()
2567 int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev, in rtw89_mac_set_cpuio() argument
2581 rtw89_write32(rtwdev, reg, val); in rtw89_mac_set_cpuio()
2593 rtw89_write32(rtwdev, reg, val); in rtw89_mac_set_cpuio()
2604 rtw89_write32(rtwdev, reg, val); in rtw89_mac_set_cpuio()
2609 1, 2000, false, rtwdev, reg); in rtw89_mac_set_cpuio()
2620 static int dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) in dle_quota_change() argument
2627 cfg = get_dle_mem_cfg(rtwdev, mode); in dle_quota_change()
2629 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); in dle_quota_change()
2634 dle_expected_used_size(rtwdev, mode)) { in dle_quota_change()
2635 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); in dle_quota_change()
2639 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); in dle_quota_change()
2641 pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, true); in dle_quota_change()
2643 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); in dle_quota_change()
2653 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true); in dle_quota_change()
2655 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); in dle_quota_change()
2659 pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, false); in dle_quota_change()
2661 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); in dle_quota_change()
2671 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, false); in dle_quota_change()
2673 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); in dle_quota_change()
2680 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) in band_idle_ck_b() argument
2686 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in band_idle_ck_b()
2696 false, rtwdev, reg); in band_idle_ck_b()
2703 static int band1_enable(struct rtw89_dev *rtwdev) in band1_enable() argument
2710 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); in band1_enable()
2712 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); in band1_enable()
2717 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); in band1_enable()
2718 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); in band1_enable()
2719 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); in band1_enable()
2720 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); in band1_enable()
2723 ret = band_idle_ck_b(rtwdev, 0); in band1_enable()
2725 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); in band1_enable()
2729 ret = dle_quota_change(rtwdev, rtwdev->mac.qta_mode); in band1_enable()
2731 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); in band1_enable()
2736 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); in band1_enable()
2737 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); in band1_enable()
2740 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); in band1_enable()
2742 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); in band1_enable()
2746 ret = cmac_func_en(rtwdev, 1, true); in band1_enable()
2748 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); in band1_enable()
2752 ret = cmac_init(rtwdev, 1); in band1_enable()
2754 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); in band1_enable()
2758 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, in band1_enable()
2764 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) in rtw89_wdrls_imr_enable() argument
2766 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; in rtw89_wdrls_imr_enable()
2768 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); in rtw89_wdrls_imr_enable()
2769 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); in rtw89_wdrls_imr_enable()
2772 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) in rtw89_wsec_imr_enable() argument
2774 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; in rtw89_wsec_imr_enable()
2776 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); in rtw89_wsec_imr_enable()
2779 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) in rtw89_mpdu_trx_imr_enable() argument
2781 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; in rtw89_mpdu_trx_imr_enable()
2782 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; in rtw89_mpdu_trx_imr_enable()
2784 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, in rtw89_mpdu_trx_imr_enable()
2791 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, in rtw89_mpdu_trx_imr_enable()
2796 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, in rtw89_mpdu_trx_imr_enable()
2799 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, in rtw89_mpdu_trx_imr_enable()
2803 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, in rtw89_mpdu_trx_imr_enable()
2807 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) in rtw89_sta_sch_imr_enable() argument
2809 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; in rtw89_sta_sch_imr_enable()
2811 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, in rtw89_sta_sch_imr_enable()
2815 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, in rtw89_sta_sch_imr_enable()
2819 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) in rtw89_txpktctl_imr_enable() argument
2821 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; in rtw89_txpktctl_imr_enable()
2823 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, in rtw89_txpktctl_imr_enable()
2825 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, in rtw89_txpktctl_imr_enable()
2827 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, in rtw89_txpktctl_imr_enable()
2829 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, in rtw89_txpktctl_imr_enable()
2833 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) in rtw89_wde_imr_enable() argument
2835 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; in rtw89_wde_imr_enable()
2837 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); in rtw89_wde_imr_enable()
2838 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); in rtw89_wde_imr_enable()
2841 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) in rtw89_ple_imr_enable() argument
2843 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; in rtw89_ple_imr_enable()
2845 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); in rtw89_ple_imr_enable()
2846 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); in rtw89_ple_imr_enable()
2849 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) in rtw89_pktin_imr_enable() argument
2851 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, in rtw89_pktin_imr_enable()
2855 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) in rtw89_dispatcher_imr_enable() argument
2857 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; in rtw89_dispatcher_imr_enable()
2859 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, in rtw89_dispatcher_imr_enable()
2861 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, in rtw89_dispatcher_imr_enable()
2863 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, in rtw89_dispatcher_imr_enable()
2865 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, in rtw89_dispatcher_imr_enable()
2867 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, in rtw89_dispatcher_imr_enable()
2869 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, in rtw89_dispatcher_imr_enable()
2873 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) in rtw89_cpuio_imr_enable() argument
2875 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); in rtw89_cpuio_imr_enable()
2876 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); in rtw89_cpuio_imr_enable()
2879 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) in rtw89_bbrpt_imr_enable() argument
2881 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; in rtw89_bbrpt_imr_enable()
2883 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, in rtw89_bbrpt_imr_enable()
2885 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, in rtw89_bbrpt_imr_enable()
2887 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, in rtw89_bbrpt_imr_enable()
2889 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, in rtw89_bbrpt_imr_enable()
2891 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); in rtw89_bbrpt_imr_enable()
2894 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) in rtw89_scheduler_imr_enable() argument
2899 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | in rtw89_scheduler_imr_enable()
2901 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); in rtw89_scheduler_imr_enable()
2904 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) in rtw89_ptcl_imr_enable() argument
2906 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; in rtw89_ptcl_imr_enable()
2910 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); in rtw89_ptcl_imr_enable()
2911 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); in rtw89_ptcl_imr_enable()
2914 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) in rtw89_cdma_imr_enable() argument
2916 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; in rtw89_cdma_imr_enable()
2917 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; in rtw89_cdma_imr_enable()
2921 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); in rtw89_cdma_imr_enable()
2922 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); in rtw89_cdma_imr_enable()
2926 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); in rtw89_cdma_imr_enable()
2927 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); in rtw89_cdma_imr_enable()
2931 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) in rtw89_phy_intf_imr_enable() argument
2933 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; in rtw89_phy_intf_imr_enable()
2937 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); in rtw89_phy_intf_imr_enable()
2938 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); in rtw89_phy_intf_imr_enable()
2941 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) in rtw89_rmac_imr_enable() argument
2943 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; in rtw89_rmac_imr_enable()
2947 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); in rtw89_rmac_imr_enable()
2948 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); in rtw89_rmac_imr_enable()
2951 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) in rtw89_tmac_imr_enable() argument
2953 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; in rtw89_tmac_imr_enable()
2957 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); in rtw89_tmac_imr_enable()
2958 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); in rtw89_tmac_imr_enable()
2961 static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx, in rtw89_mac_enable_imr() argument
2966 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); in rtw89_mac_enable_imr()
2968 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", in rtw89_mac_enable_imr()
2974 rtw89_wdrls_imr_enable(rtwdev); in rtw89_mac_enable_imr()
2975 rtw89_wsec_imr_enable(rtwdev); in rtw89_mac_enable_imr()
2976 rtw89_mpdu_trx_imr_enable(rtwdev); in rtw89_mac_enable_imr()
2977 rtw89_sta_sch_imr_enable(rtwdev); in rtw89_mac_enable_imr()
2978 rtw89_txpktctl_imr_enable(rtwdev); in rtw89_mac_enable_imr()
2979 rtw89_wde_imr_enable(rtwdev); in rtw89_mac_enable_imr()
2980 rtw89_ple_imr_enable(rtwdev); in rtw89_mac_enable_imr()
2981 rtw89_pktin_imr_enable(rtwdev); in rtw89_mac_enable_imr()
2982 rtw89_dispatcher_imr_enable(rtwdev); in rtw89_mac_enable_imr()
2983 rtw89_cpuio_imr_enable(rtwdev); in rtw89_mac_enable_imr()
2984 rtw89_bbrpt_imr_enable(rtwdev); in rtw89_mac_enable_imr()
2986 rtw89_scheduler_imr_enable(rtwdev, mac_idx); in rtw89_mac_enable_imr()
2987 rtw89_ptcl_imr_enable(rtwdev, mac_idx); in rtw89_mac_enable_imr()
2988 rtw89_cdma_imr_enable(rtwdev, mac_idx); in rtw89_mac_enable_imr()
2989 rtw89_phy_intf_imr_enable(rtwdev, mac_idx); in rtw89_mac_enable_imr()
2990 rtw89_rmac_imr_enable(rtwdev, mac_idx); in rtw89_mac_enable_imr()
2991 rtw89_tmac_imr_enable(rtwdev, mac_idx); in rtw89_mac_enable_imr()
2999 static void rtw89_mac_err_imr_ctrl(struct rtw89_dev *rtwdev, bool en) in rtw89_mac_err_imr_ctrl() argument
3001 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; in rtw89_mac_err_imr_ctrl()
3003 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, in rtw89_mac_err_imr_ctrl()
3005 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, in rtw89_mac_err_imr_ctrl()
3007 if (chip_id != RTL8852B && rtwdev->mac.dle_info.c1_rx_qta) in rtw89_mac_err_imr_ctrl()
3008 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, in rtw89_mac_err_imr_ctrl()
3012 static int rtw89_mac_dbcc_enable(struct rtw89_dev *rtwdev, bool enable) in rtw89_mac_dbcc_enable() argument
3017 ret = band1_enable(rtwdev); in rtw89_mac_dbcc_enable()
3019 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); in rtw89_mac_dbcc_enable()
3023 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); in rtw89_mac_dbcc_enable()
3025 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); in rtw89_mac_dbcc_enable()
3029 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); in rtw89_mac_dbcc_enable()
3036 static int set_host_rpr(struct rtw89_dev *rtwdev) in set_host_rpr() argument
3038 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { in set_host_rpr()
3039 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, in set_host_rpr()
3041 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, in set_host_rpr()
3044 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, in set_host_rpr()
3046 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, in set_host_rpr()
3050 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); in set_host_rpr()
3051 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); in set_host_rpr()
3056 static int rtw89_mac_trx_init(struct rtw89_dev *rtwdev) in rtw89_mac_trx_init() argument
3058 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; in rtw89_mac_trx_init()
3061 ret = dmac_init(rtwdev, 0); in rtw89_mac_trx_init()
3063 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); in rtw89_mac_trx_init()
3067 ret = cmac_init(rtwdev, 0); in rtw89_mac_trx_init()
3069 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); in rtw89_mac_trx_init()
3073 if (is_qta_dbcc(rtwdev, qta_mode)) { in rtw89_mac_trx_init()
3074 ret = rtw89_mac_dbcc_enable(rtwdev, true); in rtw89_mac_trx_init()
3076 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); in rtw89_mac_trx_init()
3081 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); in rtw89_mac_trx_init()
3083 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); in rtw89_mac_trx_init()
3087 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); in rtw89_mac_trx_init()
3089 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); in rtw89_mac_trx_init()
3093 rtw89_mac_err_imr_ctrl(rtwdev, true); in rtw89_mac_trx_init()
3095 ret = set_host_rpr(rtwdev); in rtw89_mac_trx_init()
3097 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); in rtw89_mac_trx_init()
3104 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) in rtw89_disable_fw_watchdog() argument
3108 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, in rtw89_disable_fw_watchdog()
3111 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); in rtw89_disable_fw_watchdog()
3114 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); in rtw89_disable_fw_watchdog()
3117 static void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev) in rtw89_mac_disable_cpu() argument
3119 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); in rtw89_mac_disable_cpu()
3121 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); in rtw89_mac_disable_cpu()
3122 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | in rtw89_mac_disable_cpu()
3124 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); in rtw89_mac_disable_cpu()
3126 rtw89_disable_fw_watchdog(rtwdev); in rtw89_mac_disable_cpu()
3128 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); in rtw89_mac_disable_cpu()
3129 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); in rtw89_mac_disable_cpu()
3132 static int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, in rtw89_mac_enable_cpu() argument
3138 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) in rtw89_mac_enable_cpu()
3141 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); in rtw89_mac_enable_cpu()
3142 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); in rtw89_mac_enable_cpu()
3143 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); in rtw89_mac_enable_cpu()
3144 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); in rtw89_mac_enable_cpu()
3146 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); in rtw89_mac_enable_cpu()
3148 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); in rtw89_mac_enable_cpu()
3156 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); in rtw89_mac_enable_cpu()
3157 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, in rtw89_mac_enable_cpu()
3159 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); in rtw89_mac_enable_cpu()
3164 ret = rtw89_fw_check_rdy(rtwdev); in rtw89_mac_enable_cpu()
3172 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) in rtw89_mac_dmac_pre_init() argument
3174 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; in rtw89_mac_dmac_pre_init()
3184 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); in rtw89_mac_dmac_pre_init()
3187 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); in rtw89_mac_dmac_pre_init()
3192 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); in rtw89_mac_dmac_pre_init()
3196 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); in rtw89_mac_dmac_pre_init()
3198 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, in rtw89_mac_dmac_pre_init()
3203 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); in rtw89_mac_dmac_pre_init()
3204 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); in rtw89_mac_dmac_pre_init()
3207 ret = dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); in rtw89_mac_dmac_pre_init()
3209 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); in rtw89_mac_dmac_pre_init()
3213 ret = hfc_init(rtwdev, true, false, true); in rtw89_mac_dmac_pre_init()
3215 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); in rtw89_mac_dmac_pre_init()
3222 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) in rtw89_mac_enable_bb_rf() argument
3224 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, in rtw89_mac_enable_bb_rf()
3226 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, in rtw89_mac_enable_bb_rf()
3229 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); in rtw89_mac_enable_bb_rf()
3235 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) in rtw89_mac_disable_bb_rf() argument
3237 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, in rtw89_mac_disable_bb_rf()
3239 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, in rtw89_mac_disable_bb_rf()
3242 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); in rtw89_mac_disable_bb_rf()
3248 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev) in rtw89_mac_partial_init() argument
3252 ret = rtw89_mac_power_switch(rtwdev, true); in rtw89_mac_partial_init()
3254 rtw89_mac_power_switch(rtwdev, false); in rtw89_mac_partial_init()
3255 ret = rtw89_mac_power_switch(rtwdev, true); in rtw89_mac_partial_init()
3260 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); in rtw89_mac_partial_init()
3262 ret = rtw89_mac_dmac_pre_init(rtwdev); in rtw89_mac_partial_init()
3266 if (rtwdev->hci.ops->mac_pre_init) { in rtw89_mac_partial_init()
3267 ret = rtwdev->hci.ops->mac_pre_init(rtwdev); in rtw89_mac_partial_init()
3272 rtw89_mac_disable_cpu(rtwdev); in rtw89_mac_partial_init()
3273 ret = rtw89_mac_enable_cpu(rtwdev, 0, true); in rtw89_mac_partial_init()
3277 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL); in rtw89_mac_partial_init()
3284 int rtw89_mac_init(struct rtw89_dev *rtwdev) in rtw89_mac_init() argument
3288 ret = rtw89_mac_partial_init(rtwdev); in rtw89_mac_init()
3292 ret = rtw89_chip_enable_bb_rf(rtwdev); in rtw89_mac_init()
3296 ret = rtw89_mac_sys_init(rtwdev); in rtw89_mac_init()
3300 ret = rtw89_mac_trx_init(rtwdev); in rtw89_mac_init()
3304 if (rtwdev->hci.ops->mac_post_init) { in rtw89_mac_init()
3305 ret = rtwdev->hci.ops->mac_post_init(rtwdev); in rtw89_mac_init()
3310 rtw89_fw_send_all_early_h2c(rtwdev); in rtw89_mac_init()
3311 rtw89_fw_h2c_set_ofld_cfg(rtwdev); in rtw89_mac_init()
3315 rtw89_mac_power_switch(rtwdev, false); in rtw89_mac_init()
3320 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) in rtw89_mac_dmac_tbl_init() argument
3325 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, in rtw89_mac_dmac_tbl_init()
3327 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); in rtw89_mac_dmac_tbl_init()
3331 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) in rtw89_mac_cmac_tbl_init() argument
3333 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, in rtw89_mac_cmac_tbl_init()
3335 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); in rtw89_mac_cmac_tbl_init()
3336 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); in rtw89_mac_cmac_tbl_init()
3337 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); in rtw89_mac_cmac_tbl_init()
3338 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); in rtw89_mac_cmac_tbl_init()
3339 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); in rtw89_mac_cmac_tbl_init()
3340 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); in rtw89_mac_cmac_tbl_init()
3341 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); in rtw89_mac_cmac_tbl_init()
3342 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); in rtw89_mac_cmac_tbl_init()
3345 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) in rtw89_mac_set_macid_pause() argument
3351 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); in rtw89_mac_set_macid_pause()
3355 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); in rtw89_mac_set_macid_pause()
3387 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_func_sw() argument
3393 if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN)) in rtw89_mac_port_cfg_func_sw()
3396 rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK); in rtw89_mac_port_cfg_func_sw()
3397 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1); in rtw89_mac_port_cfg_func_sw()
3398 rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK); in rtw89_mac_port_cfg_func_sw()
3399 rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK); in rtw89_mac_port_cfg_func_sw()
3403 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN | in rtw89_mac_port_cfg_func_sw()
3405 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST); in rtw89_mac_port_cfg_func_sw()
3406 rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0); in rtw89_mac_port_cfg_func_sw()
3409 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_tx_rpt() argument
3415 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); in rtw89_mac_port_cfg_tx_rpt()
3417 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); in rtw89_mac_port_cfg_tx_rpt()
3420 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_rx_rpt() argument
3426 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); in rtw89_mac_port_cfg_rx_rpt()
3428 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); in rtw89_mac_port_cfg_rx_rpt()
3431 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_net_type() argument
3436 rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK, in rtw89_mac_port_cfg_net_type()
3440 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_bcn_prct() argument
3448 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits); in rtw89_mac_port_cfg_bcn_prct()
3450 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits); in rtw89_mac_port_cfg_bcn_prct()
3453 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_rx_sw() argument
3462 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit); in rtw89_mac_port_cfg_rx_sw()
3464 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit); in rtw89_mac_port_cfg_rx_sw()
3467 static void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_rx_sync() argument
3475 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); in rtw89_mac_port_cfg_rx_sync()
3477 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); in rtw89_mac_port_cfg_rx_sync()
3480 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_tx_sw() argument
3488 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); in rtw89_mac_port_cfg_tx_sw()
3490 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); in rtw89_mac_port_cfg_tx_sw()
3493 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_bcn_intv() argument
3500 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, in rtw89_mac_port_cfg_bcn_intv()
3504 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_hiq_win() argument
3517 rtw89_write8(rtwdev, reg, win); in rtw89_mac_port_cfg_hiq_win()
3520 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_hiq_dtim() argument
3528 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); in rtw89_mac_port_cfg_hiq_dtim()
3530 rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, in rtw89_mac_port_cfg_hiq_dtim()
3534 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_bcn_setup_time() argument
3539 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, in rtw89_mac_port_cfg_bcn_setup_time()
3543 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_bcn_hold_time() argument
3548 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, in rtw89_mac_port_cfg_bcn_hold_time()
3552 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_bcn_mask_area() argument
3557 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, in rtw89_mac_port_cfg_bcn_mask_area()
3561 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_tbtt_early() argument
3566 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, in rtw89_mac_port_cfg_tbtt_early()
3570 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_bss_color() argument
3587 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); in rtw89_mac_port_cfg_bss_color()
3590 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_mbssid() argument
3601 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); in rtw89_mac_port_cfg_mbssid()
3605 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_hiq_drop() argument
3613 val = rtw89_read32(rtwdev, reg); in rtw89_mac_port_cfg_hiq_drop()
3617 rtw89_write32(rtwdev, reg, val); in rtw89_mac_port_cfg_hiq_drop()
3620 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_func_en() argument
3625 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN); in rtw89_mac_port_cfg_func_en()
3628 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_bcn_early() argument
3633 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, in rtw89_mac_port_cfg_bcn_early()
3637 static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_tbtt_shift() argument
3643 if (rtwdev->chip->chip_id != RTL8852C) in rtw89_mac_port_cfg_tbtt_shift()
3653 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_shift, in rtw89_mac_port_cfg_tbtt_shift()
3657 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) in rtw89_mac_vif_init() argument
3661 ret = rtw89_mac_port_update(rtwdev, rtwvif); in rtw89_mac_vif_init()
3665 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id); in rtw89_mac_vif_init()
3666 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id); in rtw89_mac_vif_init()
3668 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false); in rtw89_mac_vif_init()
3672 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE); in rtw89_mac_vif_init()
3676 ret = rtw89_cam_init(rtwdev, rtwvif); in rtw89_mac_vif_init()
3680 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); in rtw89_mac_vif_init()
3684 ret = rtw89_fw_h2c_default_cmac_tbl(rtwdev, rtwvif); in rtw89_mac_vif_init()
3691 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) in rtw89_mac_vif_deinit() argument
3695 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE); in rtw89_mac_vif_deinit()
3699 rtw89_cam_deinit(rtwdev, rtwvif); in rtw89_mac_vif_deinit()
3701 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); in rtw89_mac_vif_deinit()
3708 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) in rtw89_mac_port_update() argument
3715 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); in rtw89_mac_port_update()
3716 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false); in rtw89_mac_port_update()
3717 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false); in rtw89_mac_port_update()
3718 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif); in rtw89_mac_port_update()
3719 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif); in rtw89_mac_port_update()
3720 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif); in rtw89_mac_port_update()
3721 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif); in rtw89_mac_port_update()
3722 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif); in rtw89_mac_port_update()
3723 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif); in rtw89_mac_port_update()
3724 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif); in rtw89_mac_port_update()
3725 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif); in rtw89_mac_port_update()
3726 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif); in rtw89_mac_port_update()
3727 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif); in rtw89_mac_port_update()
3728 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif); in rtw89_mac_port_update()
3729 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif); in rtw89_mac_port_update()
3730 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif); in rtw89_mac_port_update()
3731 rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif); in rtw89_mac_port_update()
3732 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif); in rtw89_mac_port_update()
3733 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif); in rtw89_mac_port_update()
3734 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif); in rtw89_mac_port_update()
3736 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif); in rtw89_mac_port_update()
3760 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, in rtw89_mac_set_he_obss_narrow_bw_ru() argument
3764 struct ieee80211_hw *hw = rtwdev->hw; in rtw89_mac_set_he_obss_narrow_bw_ru()
3780 rtw89_write32_clr(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); in rtw89_mac_set_he_obss_narrow_bw_ru()
3782 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); in rtw89_mac_set_he_obss_narrow_bw_ru()
3785 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) in rtw89_mac_add_vif() argument
3789 rtwvif->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, in rtw89_mac_add_vif()
3794 ret = rtw89_mac_vif_init(rtwdev, rtwvif); in rtw89_mac_add_vif()
3801 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); in rtw89_mac_add_vif()
3806 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) in rtw89_mac_remove_vif() argument
3810 ret = rtw89_mac_vif_deinit(rtwdev, rtwvif); in rtw89_mac_remove_vif()
3811 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); in rtw89_mac_remove_vif()
3817 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) in rtw89_mac_c2h_macid_pause() argument
3821 static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) in rtw89_is_op_chan() argument
3823 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info; in rtw89_is_op_chan()
3829 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h, in rtw89_mac_c2h_scanofld_rsp() argument
3832 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; in rtw89_mac_c2h_scanofld_rsp()
3836 u32 last_chan = rtwdev->scan_info.last_chan_idx; in rtw89_mac_c2h_scanofld_rsp()
3847 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) in rtw89_mac_c2h_scanofld_rsp()
3850 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, in rtw89_mac_c2h_scanofld_rsp()
3856 if (rtw89_is_op_chan(rtwdev, band, chan)) in rtw89_mac_c2h_scanofld_rsp()
3857 ieee80211_stop_queues(rtwdev->hw); in rtw89_mac_c2h_scanofld_rsp()
3862 ret = rtw89_hw_scan_offload(rtwdev, vif, true); in rtw89_mac_c2h_scanofld_rsp()
3864 rtw89_hw_scan_abort(rtwdev, vif); in rtw89_mac_c2h_scanofld_rsp()
3865 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); in rtw89_mac_c2h_scanofld_rsp()
3868 rtw89_hw_scan_complete(rtwdev, vif, false); in rtw89_mac_c2h_scanofld_rsp()
3873 rtw89_assign_entity_chan(rtwdev, RTW89_SUB_ENTITY_0, &new); in rtw89_mac_c2h_scanofld_rsp()
3874 if (rtw89_is_op_chan(rtwdev, band, chan)) { in rtw89_mac_c2h_scanofld_rsp()
3875 rtw89_store_op_chan(rtwdev, false); in rtw89_mac_c2h_scanofld_rsp()
3876 ieee80211_wake_queues(rtwdev->hw); in rtw89_mac_c2h_scanofld_rsp()
3885 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) in rtw89_mac_c2h_rec_ack() argument
3887 rtw89_debug(rtwdev, RTW89_DBG_FW, in rtw89_mac_c2h_rec_ack()
3896 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) in rtw89_mac_c2h_done_ack() argument
3898 rtw89_debug(rtwdev, RTW89_DBG_FW, in rtw89_mac_c2h_done_ack()
3908 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) in rtw89_mac_c2h_log() argument
3910 rtw89_info(rtwdev, "%*s", RTW89_GET_C2H_LOG_LEN(len), in rtw89_mac_c2h_log()
3915 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) in rtw89_mac_c2h_bcn_cnt() argument
3920 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h, in rtw89_mac_c2h_pkt_ofld_rsp() argument
3926 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, in rtw89_mac_c2h_tsf32_toggle_rpt() argument
3932 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev,
3944 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev,
3952 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, in rtw89_mac_c2h_handle() argument
3955 void (*handler)(struct rtw89_dev *rtwdev, in rtw89_mac_c2h_handle()
3970 rtw89_info(rtwdev, "c2h class %d not support\n", class); in rtw89_mac_c2h_handle()
3974 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, in rtw89_mac_c2h_handle()
3978 handler(rtwdev, skb, len); in rtw89_mac_c2h_handle()
3981 bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev, in rtw89_mac_get_txpwr_cr() argument
3985 const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem; in rtw89_mac_get_txpwr_cr()
3990 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", in rtw89_mac_get_txpwr_cr()
3997 rtw89_err(rtwdev, in rtw89_mac_get_txpwr_cr()
4007 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", in rtw89_mac_get_txpwr_cr()
4014 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) in rtw89_mac_cfg_ppdu_status() argument
4019 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in rtw89_mac_cfg_ppdu_status()
4024 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); in rtw89_mac_cfg_ppdu_status()
4028 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | in rtw89_mac_cfg_ppdu_status()
4032 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, in rtw89_mac_cfg_ppdu_status()
4039 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) in rtw89_mac_update_rts_threshold() argument
4047 struct ieee80211_hw *hw = rtwdev->hw; in rtw89_mac_update_rts_threshold()
4064 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); in rtw89_mac_update_rts_threshold()
4065 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); in rtw89_mac_update_rts_threshold()
4068 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) in rtw89_mac_flush_txq() argument
4073 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) in rtw89_mac_flush_txq()
4077 10000, 200000, false, rtwdev); in rtw89_mac_flush_txq()
4078 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) in rtw89_mac_flush_txq()
4079 rtw89_info(rtwdev, "timed out to flush queues\n"); in rtw89_mac_flush_txq()
4082 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) in rtw89_mac_coex_init() argument
4089 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); in rtw89_mac_coex_init()
4090 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); in rtw89_mac_coex_init()
4091 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); in rtw89_mac_coex_init()
4092 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); in rtw89_mac_coex_init()
4093 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); in rtw89_mac_coex_init()
4094 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); in rtw89_mac_coex_init()
4096 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); in rtw89_mac_coex_init()
4098 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); in rtw89_mac_coex_init()
4100 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); in rtw89_mac_coex_init()
4102 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); in rtw89_mac_coex_init()
4106 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); in rtw89_mac_coex_init()
4108 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); in rtw89_mac_coex_init()
4114 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); in rtw89_mac_coex_init()
4117 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); in rtw89_mac_coex_init()
4119 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); in rtw89_mac_coex_init()
4120 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); in rtw89_mac_coex_init()
4122 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); in rtw89_mac_coex_init()
4125 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); in rtw89_mac_coex_init()
4128 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); in rtw89_mac_coex_init()
4131 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); in rtw89_mac_coex_init()
4133 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); in rtw89_mac_coex_init()
4141 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); in rtw89_mac_coex_init()
4143 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); in rtw89_mac_coex_init()
4151 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); in rtw89_mac_coex_init()
4153 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); in rtw89_mac_coex_init()
4156 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); in rtw89_mac_coex_init()
4158 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); in rtw89_mac_coex_init()
4161 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); in rtw89_mac_coex_init()
4163 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); in rtw89_mac_coex_init()
4173 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, in rtw89_mac_coex_init_v1() argument
4176 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, in rtw89_mac_coex_init_v1()
4178 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); in rtw89_mac_coex_init_v1()
4179 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); in rtw89_mac_coex_init_v1()
4180 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); in rtw89_mac_coex_init_v1()
4184 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, in rtw89_mac_coex_init_v1()
4186 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, in rtw89_mac_coex_init_v1()
4190 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, in rtw89_mac_coex_init_v1()
4201 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, in rtw89_mac_cfg_gnt() argument
4230 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); in rtw89_mac_cfg_gnt()
4232 rtw89_err(rtwdev, "Write LTE fail!\n"); in rtw89_mac_cfg_gnt()
4240 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, in rtw89_mac_cfg_gnt_v1() argument
4281 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); in rtw89_mac_cfg_gnt_v1()
4287 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) in rtw89_mac_cfg_plt() argument
4293 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); in rtw89_mac_cfg_plt()
4307 rtw89_write16(rtwdev, reg, val); in rtw89_mac_cfg_plt()
4312 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) in rtw89_mac_cfg_sb() argument
4316 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); in rtw89_mac_cfg_sb()
4319 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) in rtw89_mac_cfg_sb()
4327 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); in rtw89_mac_cfg_sb()
4331 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) in rtw89_mac_get_sb() argument
4333 return rtw89_read32(rtwdev, R_AX_SCOREBOARD); in rtw89_mac_get_sb()
4336 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) in rtw89_mac_cfg_ctrl_path() argument
4338 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); in rtw89_mac_cfg_ctrl_path()
4341 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); in rtw89_mac_cfg_ctrl_path()
4347 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) in rtw89_mac_cfg_ctrl_path_v1() argument
4349 struct rtw89_btc *btc = &rtwdev->btc; in rtw89_mac_cfg_ctrl_path_v1()
4364 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); in rtw89_mac_cfg_ctrl_path_v1()
4368 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) in rtw89_mac_get_ctrl_path() argument
4370 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); in rtw89_mac_get_ctrl_path()
4375 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) in rtw89_mac_get_plt_cnt() argument
4381 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); in rtw89_mac_get_plt_cnt()
4382 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); in rtw89_mac_get_plt_cnt()
4387 static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) in rtw89_mac_bfee_ctrl() argument
4393 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); in rtw89_mac_bfee_ctrl()
4396 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); in rtw89_mac_bfee_ctrl()
4397 rtw89_write32_set(rtwdev, reg, mask); in rtw89_mac_bfee_ctrl()
4399 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); in rtw89_mac_bfee_ctrl()
4400 rtw89_write32_clr(rtwdev, reg, mask); in rtw89_mac_bfee_ctrl()
4404 static int rtw89_mac_init_bfee(struct rtw89_dev *rtwdev, u8 mac_idx) in rtw89_mac_init_bfee() argument
4410 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in rtw89_mac_init_bfee()
4417 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); in rtw89_mac_init_bfee()
4420 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); in rtw89_mac_init_bfee()
4425 rtw89_write32(rtwdev, reg, val32); in rtw89_mac_init_bfee()
4426 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); in rtw89_mac_init_bfee()
4429 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | in rtw89_mac_init_bfee()
4434 rtw89_write32(rtwdev, reg, in rtw89_mac_init_bfee()
4440 rtw89_write32_set(rtwdev, reg, in rtw89_mac_init_bfee()
4446 static int rtw89_mac_set_csi_para_reg(struct rtw89_dev *rtwdev, in rtw89_mac_set_csi_para_reg() argument
4460 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in rtw89_mac_set_csi_para_reg()
4484 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); in rtw89_mac_set_csi_para_reg()
4499 rtw89_write16(rtwdev, reg, val); in rtw89_mac_set_csi_para_reg()
4504 static int rtw89_mac_csi_rrsc(struct rtw89_dev *rtwdev, in rtw89_mac_csi_rrsc() argument
4514 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in rtw89_mac_csi_rrsc()
4534 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); in rtw89_mac_csi_rrsc()
4535 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); in rtw89_mac_csi_rrsc()
4536 rtw89_write32(rtwdev, in rtw89_mac_csi_rrsc()
4543 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, in rtw89_mac_bf_assoc() argument
4549 rtw89_debug(rtwdev, RTW89_DBG_BF, in rtw89_mac_bf_assoc()
4551 rtw89_mac_init_bfee(rtwdev, rtwvif->mac_idx); in rtw89_mac_bf_assoc()
4552 rtw89_mac_set_csi_para_reg(rtwdev, vif, sta); in rtw89_mac_bf_assoc()
4553 rtw89_mac_csi_rrsc(rtwdev, vif, sta); in rtw89_mac_bf_assoc()
4557 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, in rtw89_mac_bf_disassoc() argument
4562 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false); in rtw89_mac_bf_disassoc()
4565 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, in rtw89_mac_bf_set_gid_table() argument
4572 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); in rtw89_mac_bf_set_gid_table()
4575 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN0, mac_idx), in rtw89_mac_bf_set_gid_table()
4577 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN1, mac_idx), in rtw89_mac_bf_set_gid_table()
4581 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION0, mac_idx), in rtw89_mac_bf_set_gid_table()
4583 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION1, mac_idx), in rtw89_mac_bf_set_gid_table()
4585 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION2, mac_idx), in rtw89_mac_bf_set_gid_table()
4587 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION3, mac_idx), in rtw89_mac_bf_set_gid_table()
4592 struct rtw89_dev *rtwdev; member
4612 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, in rtw89_mac_bf_monitor_calc() argument
4617 data.rtwdev = rtwdev; in rtw89_mac_bf_monitor_calc()
4620 ieee80211_iterate_stations_atomic(rtwdev->hw, in rtw89_mac_bf_monitor_calc()
4624 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); in rtw89_mac_bf_monitor_calc()
4626 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); in rtw89_mac_bf_monitor_calc()
4628 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); in rtw89_mac_bf_monitor_calc()
4631 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) in _rtw89_mac_bf_monitor_track() argument
4633 struct rtw89_traffic_stats *stats = &rtwdev->stats; in _rtw89_mac_bf_monitor_track()
4636 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); in _rtw89_mac_bf_monitor_track()
4641 rtw89_for_each_rtwvif(rtwdev, rtwvif) in _rtw89_mac_bf_monitor_track()
4642 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en); in _rtw89_mac_bf_monitor_track()
4646 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, in __rtw89_mac_set_tx_time() argument
4657 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); in __rtw89_mac_set_tx_time()
4659 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in __rtw89_mac_set_tx_time()
4661 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); in __rtw89_mac_set_tx_time()
4666 rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, in __rtw89_mac_set_tx_time()
4673 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, in rtw89_mac_set_tx_time() argument
4680 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); in rtw89_mac_set_tx_time()
4682 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); in rtw89_mac_set_tx_time()
4689 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, in rtw89_mac_get_tx_time() argument
4699 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in rtw89_mac_get_tx_time()
4701 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); in rtw89_mac_get_tx_time()
4706 *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; in rtw89_mac_get_tx_time()
4712 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, in rtw89_mac_set_tx_retry_limit() argument
4722 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); in rtw89_mac_set_tx_retry_limit()
4724 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); in rtw89_mac_set_tx_retry_limit()
4731 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, in rtw89_mac_get_tx_retry_limit() argument
4741 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in rtw89_mac_get_tx_retry_limit()
4743 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); in rtw89_mac_get_tx_retry_limit()
4748 *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); in rtw89_mac_get_tx_retry_limit()
4754 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, in rtw89_mac_set_hw_muedca_ctrl() argument
4762 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in rtw89_mac_set_hw_muedca_ctrl()
4768 rtw89_write16_set(rtwdev, reg, set); in rtw89_mac_set_hw_muedca_ctrl()
4770 rtw89_write16_clr(rtwdev, reg, set); in rtw89_mac_set_hw_muedca_ctrl()
4775 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) in rtw89_mac_write_xtal_si() argument
4785 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); in rtw89_mac_write_xtal_si()
4788 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); in rtw89_mac_write_xtal_si()
4790 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", in rtw89_mac_write_xtal_si()
4799 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val) in rtw89_mac_read_xtal_si() argument
4809 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); in rtw89_mac_read_xtal_si()
4812 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); in rtw89_mac_read_xtal_si()
4814 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); in rtw89_mac_read_xtal_si()
4818 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); in rtw89_mac_read_xtal_si()
4824 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) in rtw89_mac_pkt_drop_sta() argument
4844 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); in rtw89_mac_pkt_drop_sta()
4852 struct rtw89_dev *rtwdev = rtwvif->rtwdev; in rtw89_mac_pkt_drop_vif_iter() local
4858 rtw89_mac_pkt_drop_sta(rtwdev, rtwsta); in rtw89_mac_pkt_drop_vif_iter()
4861 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) in rtw89_mac_pkt_drop_vif() argument
4863 ieee80211_iterate_stations_atomic(rtwdev->hw, in rtw89_mac_pkt_drop_vif()