1168 			rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en);  in cmac_func_en()
1171 			rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,  in cmac_func_en()
1174 		rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en);  in cmac_func_en()
1175 		rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en);  in cmac_func_en()
1182 			rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,  in cmac_func_en()
1228 		rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0,  in chip_func_en()
1355 		rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,  in dle_func_en()
1365 		rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN,  in dle_clk_en()
1575 	rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN);  in preload_init_set()
1660 	rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG);  in sta_sch_init()
1678 	rtw89_write32_set(rtwdev, R_AX_MPDU_PROC,  in mpdu_proc_init()
1809 		rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV);  in scheduler_init()
1968 	rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN |  in nav_ctrl_init()
2044 	rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN);  in trxptcl_init()
2758 	rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,  in band1_enable()
2769 	rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set);  in rtw89_wdrls_imr_enable()
2776 	rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set);  in rtw89_wsec_imr_enable()
2796 	rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR,  in rtw89_mpdu_trx_imr_enable()
2803 	rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR,  in rtw89_mpdu_trx_imr_enable()
2815 	rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR,  in rtw89_sta_sch_imr_enable()
2825 	rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg,  in rtw89_txpktctl_imr_enable()
2829 	rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg,  in rtw89_txpktctl_imr_enable()
2838 	rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set);  in rtw89_wde_imr_enable()
2846 	rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set);  in rtw89_ple_imr_enable()
2851 	rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR,  in rtw89_pktin_imr_enable()
2861 	rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR,  in rtw89_dispatcher_imr_enable()
2865 	rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR,  in rtw89_dispatcher_imr_enable()
2869 	rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR,  in rtw89_dispatcher_imr_enable()
2876 	rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET);  in rtw89_cpuio_imr_enable()
2883 	rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg,  in rtw89_bbrpt_imr_enable()
2887 	rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg,  in rtw89_bbrpt_imr_enable()
2889 	rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg,  in rtw89_bbrpt_imr_enable()
2891 	rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR);  in rtw89_bbrpt_imr_enable()
2901 	rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN);  in rtw89_scheduler_imr_enable()
2911 	rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set);  in rtw89_ptcl_imr_enable()
2922 	rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set);  in rtw89_cdma_imr_enable()
2927 		rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set);  in rtw89_cdma_imr_enable()
2938 	rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set);  in rtw89_phy_intf_imr_enable()
2948 	rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set);  in rtw89_rmac_imr_enable()
2958 	rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set);  in rtw89_tmac_imr_enable()
3041 		rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0,  in set_host_rpr()
3129 	rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);  in rtw89_mac_disable_cpu()
3146 	rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN);  in rtw89_mac_enable_cpu()
3159 	rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN);  in rtw89_mac_enable_cpu()
3204 	rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN);  in rtw89_mac_dmac_pre_init()
3226 	rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL,  in rtw89_mac_enable_bb_rf()
3782 		rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_RU26_DIS);  in rtw89_mac_set_he_obss_narrow_bw_ru()
4176 	rtw89_write32_set(rtwdev, R_AX_BTC_CFG,  in rtw89_mac_coex_init_v1()
4178 	rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN);  in rtw89_mac_coex_init_v1()
4397 		rtw89_write32_set(rtwdev, reg, mask);  in rtw89_mac_bfee_ctrl()
4417 	rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN);  in rtw89_mac_init_bfee()
4429 	rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL |  in rtw89_mac_init_bfee()
4440 	rtw89_write32_set(rtwdev, reg,  in rtw89_mac_init_bfee()
4484 	rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL);  in rtw89_mac_set_csi_para_reg()
4534 	rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL);  in rtw89_mac_csi_rrsc()