Lines Matching +full:0 +full:x4f000
21 #define IQK_DONE_8822C 0xaa
44 efuse->country_code[0] = map->country_code[0]; in rtw8822c_read_efuse()
47 efuse->regd = map->rf_board_option & 0x7; in rtw8822c_read_efuse()
52 efuse->power_track_type = (map->tx_pwr_calibrate_rate >> 4) & 0xf; in rtw8822c_read_efuse()
54 for (i = 0; i < 4; i++) in rtw8822c_read_efuse()
66 return 0; in rtw8822c_read_efuse()
96 u32 rf_addr[DACK_RF_8822C] = {0x8f}; in rtw8822c_dac_backup_reg()
97 u32 addrs[DACK_REG_8822C] = {0x180c, 0x1810, 0x410c, 0x4110, in rtw8822c_dac_backup_reg()
98 0x1c3c, 0x1c24, 0x1d70, 0x9b4, in rtw8822c_dac_backup_reg()
99 0x1a00, 0x1a14, 0x1d58, 0x1c38, in rtw8822c_dac_backup_reg()
100 0x1e24, 0x1e28, 0x1860, 0x4160}; in rtw8822c_dac_backup_reg()
102 for (i = 0; i < DACK_REG_8822C; i++) { in rtw8822c_dac_backup_reg()
108 for (path = 0; path < DACK_PATH_8822C; path++) { in rtw8822c_dac_backup_reg()
109 for (i = 0; i < DACK_RF_8822C; i++) { in rtw8822c_dac_backup_reg()
128 for (path = 0; path < DACK_PATH_8822C; path++) { in rtw8822c_dac_restore_reg()
129 for (i = 0; i < DACK_RF_8822C; i++) { in rtw8822c_dac_restore_reg()
140 if (value >= 0x200) { in rtw8822c_rf_minmax_cmp()
141 if (*min >= 0x200) { in rtw8822c_rf_minmax_cmp()
147 if (*max >= 0x200) { in rtw8822c_rf_minmax_cmp()
152 if (*min < 0x200) { in rtw8822c_rf_minmax_cmp()
157 if (*max >= 0x200) { in rtw8822c_rf_minmax_cmp()
168 if (*v1 >= 0x200 && *v2 >= 0x200) { in __rtw8822c_dac_iq_sort()
171 } else if (*v1 < 0x200 && *v2 < 0x200) { in __rtw8822c_dac_iq_sort()
174 } else if (*v1 < 0x200 && *v2 >= 0x200) { in __rtw8822c_dac_iq_sort()
183 for (i = 0; i < DACK_SN_8822C - 1; i++) { in rtw8822c_dac_iq_sort()
184 for (j = 0; j < (DACK_SN_8822C - 1 - i) ; j++) { in rtw8822c_dac_iq_sort()
195 m = 0; in rtw8822c_dac_iq_offset()
196 p = 0; in rtw8822c_dac_iq_offset()
198 if (vec[i] > 0x200) in rtw8822c_dac_iq_offset()
199 m = (0x400 - vec[i]) + m; in rtw8822c_dac_iq_offset()
210 if (t != 0x0) in rtw8822c_dac_iq_offset()
211 t = 0x400 - t; in rtw8822c_dac_iq_offset()
223 base_addr = 0x1800; in rtw8822c_get_path_write_addr()
226 base_addr = 0x4100; in rtw8822c_get_path_write_addr()
242 base_addr = 0x2800; in rtw8822c_get_path_read_addr()
245 base_addr = 0x4500; in rtw8822c_get_path_read_addr()
259 if ((value >= 0x200 && (0x400 - value) > 0x64) || in rtw8822c_dac_iq_check()
260 (value < 0x200 && value > 0x64)) { in rtw8822c_dac_iq_check()
271 int i = 0, cnt = 0; in rtw8822c_dac_cal_iq_sample()
275 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); in rtw8822c_dac_cal_iq_sample()
276 iv[i] = (temp & 0x3ff000) >> 12; in rtw8822c_dac_cal_iq_sample()
277 qv[i] = temp & 0x3ff; in rtw8822c_dac_cal_iq_sample()
289 u32 i_max = 0, q_max = 0, i_min = 0, q_min = 0; in rtw8822c_dac_cal_iq_search()
292 int i, cnt = 0; in rtw8822c_dac_cal_iq_search()
295 i_min = iv[0]; in rtw8822c_dac_cal_iq_search()
296 i_max = iv[0]; in rtw8822c_dac_cal_iq_search()
297 q_min = qv[0]; in rtw8822c_dac_cal_iq_search()
298 q_max = qv[0]; in rtw8822c_dac_cal_iq_search()
299 for (i = 0; i < DACK_SN_8822C; i++) { in rtw8822c_dac_cal_iq_search()
304 if (i_max < 0x200 && i_min < 0x200) in rtw8822c_dac_cal_iq_search()
306 else if (i_max >= 0x200 && i_min >= 0x200) in rtw8822c_dac_cal_iq_search()
309 i_delta = i_max + (0x400 - i_min); in rtw8822c_dac_cal_iq_search()
311 if (q_max < 0x200 && q_min < 0x200) in rtw8822c_dac_cal_iq_search()
313 else if (q_max >= 0x200 && q_min >= 0x200) in rtw8822c_dac_cal_iq_search()
316 q_delta = q_max + (0x400 - q_min); in rtw8822c_dac_cal_iq_search()
319 "[DACK] i: min=0x%08x, max=0x%08x, delta=0x%08x\n", in rtw8822c_dac_cal_iq_search()
322 "[DACK] q: min=0x%08x, max=0x%08x, delta=0x%08x\n", in rtw8822c_dac_cal_iq_search()
328 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); in rtw8822c_dac_cal_iq_search()
329 iv[0] = (temp & 0x3ff000) >> 12; in rtw8822c_dac_cal_iq_search()
330 qv[0] = temp & 0x3ff; in rtw8822c_dac_cal_iq_search()
331 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); in rtw8822c_dac_cal_iq_search()
332 iv[DACK_SN_8822C - 1] = (temp & 0x3ff000) >> 12; in rtw8822c_dac_cal_iq_search()
333 qv[DACK_SN_8822C - 1] = temp & 0x3ff; in rtw8822c_dac_cal_iq_search()
349 rf_a = rtw_read_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK); in rtw8822c_dac_cal_rf_mode()
350 rf_b = rtw_read_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK); in rtw8822c_dac_cal_rf_mode()
352 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-A=0x%05x\n", rf_a); in rtw8822c_dac_cal_rf_mode()
353 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-B=0x%05x\n", rf_b); in rtw8822c_dac_cal_rf_mode()
361 rtw_write32_mask(rtwdev, 0x1d58, 0xff8, 0x1ff); in rtw8822c_dac_bb_setting()
362 rtw_write32_mask(rtwdev, 0x1a00, 0x3, 0x2); in rtw8822c_dac_bb_setting()
363 rtw_write32_mask(rtwdev, 0x1a14, 0x300, 0x3); in rtw8822c_dac_bb_setting()
364 rtw_write32(rtwdev, 0x1d70, 0x7e7e7e7e); in rtw8822c_dac_bb_setting()
365 rtw_write32_mask(rtwdev, 0x180c, 0x3, 0x0); in rtw8822c_dac_bb_setting()
366 rtw_write32_mask(rtwdev, 0x410c, 0x3, 0x0); in rtw8822c_dac_bb_setting()
367 rtw_write32(rtwdev, 0x1b00, 0x00000008); in rtw8822c_dac_bb_setting()
368 rtw_write8(rtwdev, 0x1bcc, 0x3f); in rtw8822c_dac_bb_setting()
369 rtw_write32(rtwdev, 0x1b00, 0x0000000a); in rtw8822c_dac_bb_setting()
370 rtw_write8(rtwdev, 0x1bcc, 0x3f); in rtw8822c_dac_bb_setting()
371 rtw_write32_mask(rtwdev, 0x1e24, BIT(31), 0x0); in rtw8822c_dac_bb_setting()
372 rtw_write32_mask(rtwdev, 0x1e28, 0xf, 0x3); in rtw8822c_dac_bb_setting()
379 u32 ic = 0, qc = 0, temp = 0; in rtw8822c_dac_cal_adc()
389 path_sel = 0xa0000; in rtw8822c_dac_cal_adc()
392 path_sel = 0x80000; in rtw8822c_dac_cal_adc()
400 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x0); in rtw8822c_dac_cal_adc()
402 rtw_write32(rtwdev, base_addr + 0x30, 0x30db8041); in rtw8822c_dac_cal_adc()
403 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0); in rtw8822c_dac_cal_adc()
404 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); in rtw8822c_dac_cal_adc()
405 rtw_write32(rtwdev, base_addr + 0x10, 0x02dd08c4); in rtw8822c_dac_cal_adc()
406 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260); in rtw8822c_dac_cal_adc()
407 rtw_write_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK, 0x10000); in rtw8822c_dac_cal_adc()
408 rtw_write_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK, 0x10000); in rtw8822c_dac_cal_adc()
409 for (i = 0; i < 10; i++) { in rtw8822c_dac_cal_adc()
411 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8003); in rtw8822c_dac_cal_adc()
412 rtw_write32(rtwdev, 0x1c24, 0x00010002); in rtw8822c_dac_cal_adc()
415 "[DACK] before: i=0x%x, q=0x%x\n", ic, qc); in rtw8822c_dac_cal_adc()
418 if (ic != 0x0) { in rtw8822c_dac_cal_adc()
419 ic = 0x400 - ic; in rtw8822c_dac_cal_adc()
422 if (qc != 0x0) { in rtw8822c_dac_cal_adc()
423 qc = 0x400 - qc; in rtw8822c_dac_cal_adc()
426 temp = (ic & 0x3ff) | ((qc & 0x3ff) << 10); in rtw8822c_dac_cal_adc()
427 rtw_write32(rtwdev, base_addr + 0x68, temp); in rtw8822c_dac_cal_adc()
429 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK 0x%08x=0x08%x\n", in rtw8822c_dac_cal_adc()
430 base_addr + 0x68, temp); in rtw8822c_dac_cal_adc()
432 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8103); in rtw8822c_dac_cal_adc()
435 "[DACK] after: i=0x%08x, q=0x%08x\n", ic, qc); in rtw8822c_dac_cal_adc()
436 if (ic >= 0x200) in rtw8822c_dac_cal_adc()
437 ic = 0x400 - ic; in rtw8822c_dac_cal_adc()
438 if (qc >= 0x200) in rtw8822c_dac_cal_adc()
439 qc = 0x400 - qc; in rtw8822c_dac_cal_adc()
445 rtw_write32(rtwdev, 0x1c3c, 0x00000003); in rtw8822c_dac_cal_adc()
446 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260); in rtw8822c_dac_cal_adc()
447 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4); in rtw8822c_dac_cal_adc()
450 rtw_write_rf(rtwdev, path, 0x8f, BIT(13), 0x1); in rtw8822c_dac_cal_adc()
462 rtw_write32(rtwdev, base_addr + 0x68, dm_info->dack_adck[path]); in rtw8822c_dac_cal_step1()
463 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); in rtw8822c_dac_cal_step1()
465 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0); in rtw8822c_dac_cal_step1()
466 rtw_write32(rtwdev, 0x1c38, 0xffffffff); in rtw8822c_dac_cal_step1()
468 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); in rtw8822c_dac_cal_step1()
469 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); in rtw8822c_dac_cal_step1()
470 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88); in rtw8822c_dac_cal_step1()
471 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff81); in rtw8822c_dac_cal_step1()
472 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208); in rtw8822c_dac_cal_step1()
473 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88); in rtw8822c_dac_cal_step1()
474 rtw_write32(rtwdev, base_addr + 0xd8, 0x0008ff81); in rtw8822c_dac_cal_step1()
475 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208); in rtw8822c_dac_cal_step1()
476 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000); in rtw8822c_dac_cal_step1()
478 rtw_write32(rtwdev, base_addr + 0xbc, 0x000aff8d); in rtw8822c_dac_cal_step1()
480 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89); in rtw8822c_dac_cal_step1()
481 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89); in rtw8822c_dac_cal_step1()
483 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000); in rtw8822c_dac_cal_step1()
484 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000); in rtw8822c_dac_cal_step1()
486 if (!check_hw_ready(rtwdev, read_addr + 0x08, 0x7fff80, 0xffff) || in rtw8822c_dac_cal_step1()
487 !check_hw_ready(rtwdev, read_addr + 0x34, 0x7fff80, 0xffff)) in rtw8822c_dac_cal_step1()
489 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000); in rtw8822c_dac_cal_step1()
491 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87); in rtw8822c_dac_cal_step1()
492 rtw_write32(rtwdev, 0x9b4, 0xdb6db600); in rtw8822c_dac_cal_step1()
493 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); in rtw8822c_dac_cal_step1()
494 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87); in rtw8822c_dac_cal_step1()
495 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000); in rtw8822c_dac_cal_step1()
505 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, 0x0); in rtw8822c_dac_cal_step2()
506 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, 0x8); in rtw8822c_dac_cal_step2()
507 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, 0x0); in rtw8822c_dac_cal_step2()
508 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, 0x8); in rtw8822c_dac_cal_step2()
510 rtw_write32(rtwdev, 0x1b00, 0x00000008); in rtw8822c_dac_cal_step2()
511 rtw_write8(rtwdev, 0x1bcc, 0x03f); in rtw8822c_dac_cal_step2()
512 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); in rtw8822c_dac_cal_step2()
513 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); in rtw8822c_dac_cal_step2()
514 rtw_write32(rtwdev, 0x1c3c, 0x00088103); in rtw8822c_dac_cal_step2()
521 if (ic != 0x0) in rtw8822c_dac_cal_step2()
522 ic = 0x400 - ic; in rtw8822c_dac_cal_step2()
523 if (qc != 0x0) in rtw8822c_dac_cal_step2()
524 qc = 0x400 - qc; in rtw8822c_dac_cal_step2()
525 if (ic < 0x300) { in rtw8822c_dac_cal_step2()
527 ic = ic + 0x80; in rtw8822c_dac_cal_step2()
529 ic = (0x400 - ic) * 2 * 6 / 5; in rtw8822c_dac_cal_step2()
530 ic = 0x7f - ic; in rtw8822c_dac_cal_step2()
532 if (qc < 0x300) { in rtw8822c_dac_cal_step2()
534 qc = qc + 0x80; in rtw8822c_dac_cal_step2()
536 qc = (0x400 - qc) * 2 * 6 / 5; in rtw8822c_dac_cal_step2()
537 qc = 0x7f - qc; in rtw8822c_dac_cal_step2()
543 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] before i=0x%x, q=0x%x\n", ic_in, qc_in); in rtw8822c_dac_cal_step2()
544 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] after i=0x%x, q=0x%x\n", ic, qc); in rtw8822c_dac_cal_step2()
562 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); in rtw8822c_dac_cal_step3()
563 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); in rtw8822c_dac_cal_step3()
564 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); in rtw8822c_dac_cal_step3()
565 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88); in rtw8822c_dac_cal_step3()
566 rtw_write32(rtwdev, base_addr + 0xbc, 0xc008ff81); in rtw8822c_dac_cal_step3()
567 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208); in rtw8822c_dac_cal_step3()
568 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, ic & 0xf); in rtw8822c_dac_cal_step3()
569 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, (ic & 0xf0) >> 4); in rtw8822c_dac_cal_step3()
570 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88); in rtw8822c_dac_cal_step3()
571 rtw_write32(rtwdev, base_addr + 0xd8, 0xe008ff81); in rtw8822c_dac_cal_step3()
572 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208); in rtw8822c_dac_cal_step3()
573 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, qc & 0xf); in rtw8822c_dac_cal_step3()
574 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, (qc & 0xf0) >> 4); in rtw8822c_dac_cal_step3()
575 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000); in rtw8822c_dac_cal_step3()
577 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x6); in rtw8822c_dac_cal_step3()
579 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89); in rtw8822c_dac_cal_step3()
580 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89); in rtw8822c_dac_cal_step3()
582 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000); in rtw8822c_dac_cal_step3()
583 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000); in rtw8822c_dac_cal_step3()
585 if (!check_hw_ready(rtwdev, read_addr + 0x24, 0x07f80000, ic) || in rtw8822c_dac_cal_step3()
586 !check_hw_ready(rtwdev, read_addr + 0x50, 0x07f80000, qc)) in rtw8822c_dac_cal_step3()
588 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000); in rtw8822c_dac_cal_step3()
590 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x3); in rtw8822c_dac_cal_step3()
591 rtw_write32(rtwdev, 0x9b4, 0xdb6db600); in rtw8822c_dac_cal_step3()
594 temp = ((adc_ic + 0x10) & 0x3ff) | (((adc_qc + 0x10) & 0x3ff) << 10); in rtw8822c_dac_cal_step3()
595 rtw_write32(rtwdev, base_addr + 0x68, temp); in rtw8822c_dac_cal_step3()
596 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); in rtw8822c_dac_cal_step3()
597 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000); in rtw8822c_dac_cal_step3()
599 if (ic >= 0x10) in rtw8822c_dac_cal_step3()
600 ic = ic - 0x10; in rtw8822c_dac_cal_step3()
602 ic = 0x400 - (0x10 - ic); in rtw8822c_dac_cal_step3()
604 if (qc >= 0x10) in rtw8822c_dac_cal_step3()
605 qc = qc - 0x10; in rtw8822c_dac_cal_step3()
607 qc = 0x400 - (0x10 - qc); in rtw8822c_dac_cal_step3()
612 if (ic >= 0x200) in rtw8822c_dac_cal_step3()
613 ic = 0x400 - ic; in rtw8822c_dac_cal_step3()
614 if (qc >= 0x200) in rtw8822c_dac_cal_step3()
615 qc = 0x400 - qc; in rtw8822c_dac_cal_step3()
621 "[DACK] after DACK i=0x%x, q=0x%x\n", *i_out, *q_out); in rtw8822c_dac_cal_step3()
628 rtw_write32(rtwdev, base_addr + 0x68, 0x0); in rtw8822c_dac_cal_step4()
629 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4); in rtw8822c_dac_cal_step4()
630 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0x1, 0x0); in rtw8822c_dac_cal_step4()
631 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x1); in rtw8822c_dac_cal_step4()
644 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { in rtw8822c_dac_cal_backup_vec()
645 rtw_write32_mask(rtwdev, w_addr, 0xf0000000, i); in rtw8822c_dac_cal_backup_vec()
646 val = (u16)rtw_read32_mask(rtwdev, r_addr, 0x7fc0000); in rtw8822c_dac_cal_backup_vec()
653 u32 w_off = 0x1c; in rtw8822c_dac_cal_backup_path()
654 u32 r_off = 0x2c; in rtw8822c_dac_cal_backup_path()
661 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0; in rtw8822c_dac_cal_backup_path()
662 r_addr = rtw8822c_get_path_read_addr(path) + 0x10; in rtw8822c_dac_cal_backup_path()
663 rtw8822c_dac_cal_backup_vec(rtwdev, path, 0, w_addr, r_addr); in rtw8822c_dac_cal_backup_path()
666 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off; in rtw8822c_dac_cal_backup_path()
667 r_addr = rtw8822c_get_path_read_addr(path) + 0x10 + r_off; in rtw8822c_dac_cal_backup_path()
676 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000); in rtw8822c_dac_cal_backup_dck()
677 dm_info->dack_dck[RF_PATH_A][0][0] = val; in rtw8822c_dac_cal_backup_dck()
678 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_1, 0xf); in rtw8822c_dac_cal_backup_dck()
679 dm_info->dack_dck[RF_PATH_A][0][1] = val; in rtw8822c_dac_cal_backup_dck()
680 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000); in rtw8822c_dac_cal_backup_dck()
681 dm_info->dack_dck[RF_PATH_A][1][0] = val; in rtw8822c_dac_cal_backup_dck()
682 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_1, 0xf); in rtw8822c_dac_cal_backup_dck()
685 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000); in rtw8822c_dac_cal_backup_dck()
686 dm_info->dack_dck[RF_PATH_B][0][0] = val; in rtw8822c_dac_cal_backup_dck()
687 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_1, 0xf); in rtw8822c_dac_cal_backup_dck()
688 dm_info->dack_dck[RF_PATH_B][1][0] = val; in rtw8822c_dac_cal_backup_dck()
689 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000); in rtw8822c_dac_cal_backup_dck()
690 dm_info->dack_dck[RF_PATH_B][0][1] = val; in rtw8822c_dac_cal_backup_dck()
691 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_1, 0xf); in rtw8822c_dac_cal_backup_dck()
699 temp[0] = rtw_read32(rtwdev, 0x1860); in rtw8822c_dac_cal_backup()
700 temp[1] = rtw_read32(rtwdev, 0x4160); in rtw8822c_dac_cal_backup()
701 temp[2] = rtw_read32(rtwdev, 0x9b4); in rtw8822c_dac_cal_backup()
704 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); in rtw8822c_dac_cal_backup()
707 rtw_write32_clr(rtwdev, 0x1830, BIT(30)); in rtw8822c_dac_cal_backup()
708 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c); in rtw8822c_dac_cal_backup()
712 rtw_write32_clr(rtwdev, 0x4130, BIT(30)); in rtw8822c_dac_cal_backup()
713 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c); in rtw8822c_dac_cal_backup()
717 rtw_write32_set(rtwdev, 0x1830, BIT(30)); in rtw8822c_dac_cal_backup()
718 rtw_write32_set(rtwdev, 0x4130, BIT(30)); in rtw8822c_dac_cal_backup()
720 rtw_write32(rtwdev, 0x1860, temp[0]); in rtw8822c_dac_cal_backup()
721 rtw_write32(rtwdev, 0x4160, temp[1]); in rtw8822c_dac_cal_backup()
722 rtw_write32(rtwdev, 0x9b4, temp[2]); in rtw8822c_dac_cal_backup()
731 val = dm_info->dack_dck[RF_PATH_A][0][0]; in rtw8822c_dac_cal_restore_dck()
732 rtw_write32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000, val); in rtw8822c_dac_cal_restore_dck()
733 val = dm_info->dack_dck[RF_PATH_A][0][1]; in rtw8822c_dac_cal_restore_dck()
734 rtw_write32_mask(rtwdev, REG_DCKA_I_1, 0xf, val); in rtw8822c_dac_cal_restore_dck()
737 val = dm_info->dack_dck[RF_PATH_A][1][0]; in rtw8822c_dac_cal_restore_dck()
738 rtw_write32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000, val); in rtw8822c_dac_cal_restore_dck()
740 rtw_write32_mask(rtwdev, REG_DCKA_Q_1, 0xf, val); in rtw8822c_dac_cal_restore_dck()
743 val = dm_info->dack_dck[RF_PATH_B][0][0]; in rtw8822c_dac_cal_restore_dck()
744 rtw_write32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000, val); in rtw8822c_dac_cal_restore_dck()
745 val = dm_info->dack_dck[RF_PATH_B][0][1]; in rtw8822c_dac_cal_restore_dck()
746 rtw_write32_mask(rtwdev, REG_DCKB_I_1, 0xf, val); in rtw8822c_dac_cal_restore_dck()
749 val = dm_info->dack_dck[RF_PATH_B][1][0]; in rtw8822c_dac_cal_restore_dck()
750 rtw_write32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000, val); in rtw8822c_dac_cal_restore_dck()
752 rtw_write32_mask(rtwdev, REG_DCKB_Q_1, 0xf, val); in rtw8822c_dac_cal_restore_dck()
757 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); in rtw8822c_dac_cal_restore_prepare()
759 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x0); in rtw8822c_dac_cal_restore_prepare()
760 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x0); in rtw8822c_dac_cal_restore_prepare()
761 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x0); in rtw8822c_dac_cal_restore_prepare()
762 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x0); in rtw8822c_dac_cal_restore_prepare()
764 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x0); in rtw8822c_dac_cal_restore_prepare()
765 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c); in rtw8822c_dac_cal_restore_prepare()
766 rtw_write32_mask(rtwdev, 0x18b4, BIT(0), 0x1); in rtw8822c_dac_cal_restore_prepare()
767 rtw_write32_mask(rtwdev, 0x18d0, BIT(0), 0x1); in rtw8822c_dac_cal_restore_prepare()
769 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x0); in rtw8822c_dac_cal_restore_prepare()
770 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c); in rtw8822c_dac_cal_restore_prepare()
771 rtw_write32_mask(rtwdev, 0x41b4, BIT(0), 0x1); in rtw8822c_dac_cal_restore_prepare()
772 rtw_write32_mask(rtwdev, 0x41d0, BIT(0), 0x1); in rtw8822c_dac_cal_restore_prepare()
774 rtw_write32_mask(rtwdev, 0x18b0, 0xf00, 0x0); in rtw8822c_dac_cal_restore_prepare()
775 rtw_write32_mask(rtwdev, 0x18c0, BIT(14), 0x0); in rtw8822c_dac_cal_restore_prepare()
776 rtw_write32_mask(rtwdev, 0x18cc, 0xf00, 0x0); in rtw8822c_dac_cal_restore_prepare()
777 rtw_write32_mask(rtwdev, 0x18dc, BIT(14), 0x0); in rtw8822c_dac_cal_restore_prepare()
779 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x0); in rtw8822c_dac_cal_restore_prepare()
780 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x0); in rtw8822c_dac_cal_restore_prepare()
781 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x1); in rtw8822c_dac_cal_restore_prepare()
782 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x1); in rtw8822c_dac_cal_restore_prepare()
786 rtw_write32_mask(rtwdev, 0x18c0, 0x38000, 0x7); in rtw8822c_dac_cal_restore_prepare()
787 rtw_write32_mask(rtwdev, 0x18dc, 0x38000, 0x7); in rtw8822c_dac_cal_restore_prepare()
788 rtw_write32_mask(rtwdev, 0x41c0, 0x38000, 0x7); in rtw8822c_dac_cal_restore_prepare()
789 rtw_write32_mask(rtwdev, 0x41dc, 0x38000, 0x7); in rtw8822c_dac_cal_restore_prepare()
791 rtw_write32_mask(rtwdev, 0x18b8, BIT(26) | BIT(25), 0x1); in rtw8822c_dac_cal_restore_prepare()
792 rtw_write32_mask(rtwdev, 0x18d4, BIT(26) | BIT(25), 0x1); in rtw8822c_dac_cal_restore_prepare()
794 rtw_write32_mask(rtwdev, 0x41b0, 0xf00, 0x0); in rtw8822c_dac_cal_restore_prepare()
795 rtw_write32_mask(rtwdev, 0x41c0, BIT(14), 0x0); in rtw8822c_dac_cal_restore_prepare()
796 rtw_write32_mask(rtwdev, 0x41cc, 0xf00, 0x0); in rtw8822c_dac_cal_restore_prepare()
797 rtw_write32_mask(rtwdev, 0x41dc, BIT(14), 0x0); in rtw8822c_dac_cal_restore_prepare()
799 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x0); in rtw8822c_dac_cal_restore_prepare()
800 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x0); in rtw8822c_dac_cal_restore_prepare()
801 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x1); in rtw8822c_dac_cal_restore_prepare()
802 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x1); in rtw8822c_dac_cal_restore_prepare()
804 rtw_write32_mask(rtwdev, 0x41b8, BIT(26) | BIT(25), 0x1); in rtw8822c_dac_cal_restore_prepare()
805 rtw_write32_mask(rtwdev, 0x41d4, BIT(26) | BIT(25), 0x1); in rtw8822c_dac_cal_restore_prepare()
811 u32 cnt = 0; in rtw8822c_dac_cal_restore_wait()
814 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x0); in rtw8822c_dac_cal_restore_wait()
815 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x2); in rtw8822c_dac_cal_restore_wait()
817 if (rtw_read32_mask(rtwdev, target_addr, 0xf) == 0x6) in rtw8822c_dac_cal_restore_wait()
828 u32 w_off = 0x1c; in rtw8822c_dac_cal_restore_path()
829 u32 r_off = 0x2c; in rtw8822c_dac_cal_restore_path()
834 w_i = rtw8822c_get_path_write_addr(path) + 0xb0; in rtw8822c_dac_cal_restore_path()
835 r_i = rtw8822c_get_path_read_addr(path) + 0x08; in rtw8822c_dac_cal_restore_path()
836 w_q = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off; in rtw8822c_dac_cal_restore_path()
837 r_q = rtw8822c_get_path_read_addr(path) + 0x08 + r_off; in rtw8822c_dac_cal_restore_path()
839 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_i, w_i + 0x8)) in rtw8822c_dac_cal_restore_path()
842 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { in rtw8822c_dac_cal_restore_path()
843 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0); in rtw8822c_dac_cal_restore_path()
844 value = dm_info->dack_msbk[path][0][i]; in rtw8822c_dac_cal_restore_path()
845 rtw_write32_mask(rtwdev, w_i + 0x4, 0xff8, value); in rtw8822c_dac_cal_restore_path()
846 rtw_write32_mask(rtwdev, w_i, 0xf0000000, i); in rtw8822c_dac_cal_restore_path()
847 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x1); in rtw8822c_dac_cal_restore_path()
850 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0); in rtw8822c_dac_cal_restore_path()
852 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_q, w_q + 0x8)) in rtw8822c_dac_cal_restore_path()
855 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { in rtw8822c_dac_cal_restore_path()
856 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0); in rtw8822c_dac_cal_restore_path()
858 rtw_write32_mask(rtwdev, w_q + 0x4, 0xff8, value); in rtw8822c_dac_cal_restore_path()
859 rtw_write32_mask(rtwdev, w_q, 0xf0000000, i); in rtw8822c_dac_cal_restore_path()
860 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x1); in rtw8822c_dac_cal_restore_path()
862 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0); in rtw8822c_dac_cal_restore_path()
864 rtw_write32_mask(rtwdev, w_i + 0x8, BIT(26) | BIT(25), 0x0); in rtw8822c_dac_cal_restore_path()
865 rtw_write32_mask(rtwdev, w_q + 0x8, BIT(26) | BIT(25), 0x0); in rtw8822c_dac_cal_restore_path()
866 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(0), 0x0); in rtw8822c_dac_cal_restore_path()
867 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(0), 0x0); in rtw8822c_dac_cal_restore_path()
889 if (dm_info->dack_msbk[RF_PATH_A][0][0] == 0 && in rtw8822c_dac_cal_restore()
890 dm_info->dack_msbk[RF_PATH_A][1][0] == 0 && in rtw8822c_dac_cal_restore()
891 dm_info->dack_msbk[RF_PATH_B][0][0] == 0 && in rtw8822c_dac_cal_restore()
892 dm_info->dack_msbk[RF_PATH_B][1][0] == 0) in rtw8822c_dac_cal_restore()
895 temp[0] = rtw_read32(rtwdev, 0x1860); in rtw8822c_dac_cal_restore()
896 temp[1] = rtw_read32(rtwdev, 0x4160); in rtw8822c_dac_cal_restore()
897 temp[2] = rtw_read32(rtwdev, 0x9b4); in rtw8822c_dac_cal_restore()
900 if (!check_hw_ready(rtwdev, 0x2808, 0x7fff80, 0xffff) || in rtw8822c_dac_cal_restore()
901 !check_hw_ready(rtwdev, 0x2834, 0x7fff80, 0xffff) || in rtw8822c_dac_cal_restore()
902 !check_hw_ready(rtwdev, 0x4508, 0x7fff80, 0xffff) || in rtw8822c_dac_cal_restore()
903 !check_hw_ready(rtwdev, 0x4534, 0x7fff80, 0xffff)) in rtw8822c_dac_cal_restore()
911 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x1); in rtw8822c_dac_cal_restore()
912 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1); in rtw8822c_dac_cal_restore()
913 rtw_write32(rtwdev, 0x1860, temp[0]); in rtw8822c_dac_cal_restore()
914 rtw_write32(rtwdev, 0x4160, temp[1]); in rtw8822c_dac_cal_restore()
915 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x1); in rtw8822c_dac_cal_restore()
916 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x1); in rtw8822c_dac_cal_restore()
917 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x1); in rtw8822c_dac_cal_restore()
918 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x1); in rtw8822c_dac_cal_restore()
919 rtw_write32(rtwdev, 0x9b4, temp[2]); in rtw8822c_dac_cal_restore()
928 u32 ic = 0, qc = 0, i; in rtw8822c_rf_dac_cal()
929 u32 i_a = 0x0, q_a = 0x0, i_b = 0x0, q_b = 0x0; in rtw8822c_rf_dac_cal()
930 u32 ic_a = 0x0, qc_a = 0x0, ic_b = 0x0, qc_b = 0x0; in rtw8822c_rf_dac_cal()
931 u32 adc_ic_a = 0x0, adc_qc_a = 0x0, adc_ic_b = 0x0, adc_qc_b = 0x0; in rtw8822c_rf_dac_cal()
944 for (i = 0; i < 10; i++) { in rtw8822c_rf_dac_cal()
960 for (i = 0; i < 10; i++) { in rtw8822c_rf_dac_cal()
974 rtw_write32(rtwdev, 0x1b00, 0x00000008); in rtw8822c_rf_dac_cal()
975 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1); in rtw8822c_rf_dac_cal()
976 rtw_write8(rtwdev, 0x1bcc, 0x0); in rtw8822c_rf_dac_cal()
977 rtw_write32(rtwdev, 0x1b00, 0x0000000a); in rtw8822c_rf_dac_cal()
978 rtw_write8(rtwdev, 0x1bcc, 0x0); in rtw8822c_rf_dac_cal()
985 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: ic=0x%x, qc=0x%x\n", ic_a, qc_a); in rtw8822c_rf_dac_cal()
986 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: ic=0x%x, qc=0x%x\n", ic_b, qc_b); in rtw8822c_rf_dac_cal()
987 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: i=0x%x, q=0x%x\n", i_a, q_a); in rtw8822c_rf_dac_cal()
988 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: i=0x%x, q=0x%x\n", i_b, q_b); in rtw8822c_rf_dac_cal()
996 x2k_busy = rtw_read_rf(rtwdev, RF_PATH_A, 0xb8, BIT(15)); in rtw8822c_rf_x2_check()
998 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0xC4440); in rtw8822c_rf_x2_check()
999 rtw_write_rf(rtwdev, RF_PATH_A, 0xba, RFREG_MASK, 0x6840D); in rtw8822c_rf_x2_check()
1000 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0x80440); in rtw8822c_rf_x2_check()
1009 rtw_write_rf(rtwdev, _path, 0x33, RFREG_MASK, _seq); \ in rtw8822c_set_power_trim()
1010 rtw_write_rf(rtwdev, _path, 0x3f, RFREG_MASK, \ in rtw8822c_set_power_trim()
1012 } while (0) in rtw8822c_set_power_trim()
1015 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8822c_set_power_trim()
1016 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 1); in rtw8822c_set_power_trim()
1017 RF_SET_POWER_TRIM(path, 0x0, 0); in rtw8822c_set_power_trim()
1018 RF_SET_POWER_TRIM(path, 0x1, 1); in rtw8822c_set_power_trim()
1019 RF_SET_POWER_TRIM(path, 0x2, 2); in rtw8822c_set_power_trim()
1020 RF_SET_POWER_TRIM(path, 0x3, 2); in rtw8822c_set_power_trim()
1021 RF_SET_POWER_TRIM(path, 0x4, 3); in rtw8822c_set_power_trim()
1022 RF_SET_POWER_TRIM(path, 0x5, 4); in rtw8822c_set_power_trim()
1023 RF_SET_POWER_TRIM(path, 0x6, 5); in rtw8822c_set_power_trim()
1024 RF_SET_POWER_TRIM(path, 0x7, 6); in rtw8822c_set_power_trim()
1025 RF_SET_POWER_TRIM(path, 0x8, 7); in rtw8822c_set_power_trim()
1026 RF_SET_POWER_TRIM(path, 0x9, 3); in rtw8822c_set_power_trim()
1027 RF_SET_POWER_TRIM(path, 0xa, 4); in rtw8822c_set_power_trim()
1028 RF_SET_POWER_TRIM(path, 0xb, 5); in rtw8822c_set_power_trim()
1029 RF_SET_POWER_TRIM(path, 0xc, 6); in rtw8822c_set_power_trim()
1030 RF_SET_POWER_TRIM(path, 0xd, 7); in rtw8822c_set_power_trim()
1031 RF_SET_POWER_TRIM(path, 0xe, 7); in rtw8822c_set_power_trim()
1032 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 0); in rtw8822c_set_power_trim()
1039 u8 pg_pwr = 0xff, i, path, idx; in rtw8822c_power_trim()
1048 for (i = 0; i < ARRAY_SIZE(rf_efuse_2g); i++) { in rtw8822c_power_trim()
1057 for (i = 0; i < ARRAY_SIZE(rf_efuse_5g[0]); i++) { in rtw8822c_power_trim()
1058 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8822c_power_trim()
1077 u8 pg_therm = 0xff, thermal[2] = {0}, path; in rtw8822c_thermal_trim()
1079 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8822c_thermal_trim()
1083 /* Efuse value of BIT(0) shall be move to BIT(3), and the value in rtw8822c_thermal_trim()
1087 thermal[path] |= FIELD_PREP(BIT(3), pg_therm & BIT(0)); in rtw8822c_thermal_trim()
1088 rtw_write_rf(rtwdev, path, 0x43, RF_THEMAL_MASK, thermal[path]); in rtw8822c_thermal_trim()
1096 u8 pg_pa_bias = 0xff, path; in rtw8822c_pa_bias()
1098 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8822c_pa_bias()
1106 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8822c_pa_bias()
1127 u4b_tmp == 0, 20, 600000, false, in rtw8822c_rfk_handshake()
1165 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8822c_rfk_power_save()
1168 is_power_save ? 0 : 1); in rtw8822c_rfk_power_save()
1177 for (i = 0; i < reg_num; i++) { in rtw8822c_txgapk_backup_bb_reg()
1180 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] Backup BB 0x%x = 0x%x\n", in rtw8822c_txgapk_backup_bb_reg()
1191 for (i = 0; i < reg_num; i++) { in rtw8822c_txgapk_reload_bb_reg()
1193 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] Reload BB 0x%x = 0x%x\n", in rtw8822c_txgapk_reload_bb_reg()
1219 rtw_write32_mask(rtwdev, REG_TX_FIFO, BIT_STOP_TX, 0x2); in rtw8822c_txgapk_tx_pause()
1233 rtw_write32_mask(rtwdev, REG_ENFN, BIT_IQK_DPK_EN, 0x1); in rtw8822c_txgapk_bb_dpk()
1235 BIT_IQK_DPK_CLOCK_SRC, 0x1); in rtw8822c_txgapk_bb_dpk()
1237 BIT_IQK_DPK_RESET_SRC, 0x1); in rtw8822c_txgapk_bb_dpk()
1238 rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2, BIT_EN_IOQ_IQK_DPK, 0x1); in rtw8822c_txgapk_bb_dpk()
1239 rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2, BIT_TST_IQK2SET_SRC, 0x0); in rtw8822c_txgapk_bb_dpk()
1240 rtw_write32_mask(rtwdev, REG_CCA_OFF, BIT_CCA_ON_BY_PW, 0x1ff); in rtw8822c_txgapk_bb_dpk()
1244 BIT_RFTXEN_GCK_FORCE_ON, 0x1); in rtw8822c_txgapk_bb_dpk()
1245 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_DIS_SHARERX_TXGAT, 0x1); in rtw8822c_txgapk_bb_dpk()
1247 BIT_TX_SCALE_0DB, 0x1); in rtw8822c_txgapk_bb_dpk()
1248 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_3WIRE_EN, 0x0); in rtw8822c_txgapk_bb_dpk()
1251 BIT_RFTXEN_GCK_FORCE_ON, 0x1); in rtw8822c_txgapk_bb_dpk()
1253 BIT_DIS_SHARERX_TXGAT, 0x1); in rtw8822c_txgapk_bb_dpk()
1255 BIT_TX_SCALE_0DB, 0x1); in rtw8822c_txgapk_bb_dpk()
1256 rtw_write32_mask(rtwdev, REG_3WIRE2, BIT_3WIRE_EN, 0x0); in rtw8822c_txgapk_bb_dpk()
1258 rtw_write32_mask(rtwdev, REG_CCKSB, BIT_BBMODE, 0x2); in rtw8822c_txgapk_bb_dpk()
1277 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700f0001); in rtw8822c_txgapk_afe_dpk()
1278 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700f0001); in rtw8822c_txgapk_afe_dpk()
1279 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x701f0001); in rtw8822c_txgapk_afe_dpk()
1280 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x702f0001); in rtw8822c_txgapk_afe_dpk()
1281 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x703f0001); in rtw8822c_txgapk_afe_dpk()
1282 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x704f0001); in rtw8822c_txgapk_afe_dpk()
1283 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x705f0001); in rtw8822c_txgapk_afe_dpk()
1284 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x706f0001); in rtw8822c_txgapk_afe_dpk()
1285 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x707f0001); in rtw8822c_txgapk_afe_dpk()
1286 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x708f0001); in rtw8822c_txgapk_afe_dpk()
1287 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x709f0001); in rtw8822c_txgapk_afe_dpk()
1288 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70af0001); in rtw8822c_txgapk_afe_dpk()
1289 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70bf0001); in rtw8822c_txgapk_afe_dpk()
1290 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70cf0001); in rtw8822c_txgapk_afe_dpk()
1291 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70df0001); in rtw8822c_txgapk_afe_dpk()
1292 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ef0001); in rtw8822c_txgapk_afe_dpk()
1293 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ff0001); in rtw8822c_txgapk_afe_dpk()
1294 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ff0001); in rtw8822c_txgapk_afe_dpk()
1311 rtw_write32_mask(rtwdev, REG_IQK_CTRL, MASKDWORD, 0xffa1005e); in rtw8822c_txgapk_afe_dpk_restore()
1312 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700b8041); in rtw8822c_txgapk_afe_dpk_restore()
1313 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70144041); in rtw8822c_txgapk_afe_dpk_restore()
1314 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70244041); in rtw8822c_txgapk_afe_dpk_restore()
1315 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70344041); in rtw8822c_txgapk_afe_dpk_restore()
1316 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70444041); in rtw8822c_txgapk_afe_dpk_restore()
1317 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x705b8041); in rtw8822c_txgapk_afe_dpk_restore()
1318 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70644041); in rtw8822c_txgapk_afe_dpk_restore()
1319 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x707b8041); in rtw8822c_txgapk_afe_dpk_restore()
1320 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x708b8041); in rtw8822c_txgapk_afe_dpk_restore()
1321 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x709b8041); in rtw8822c_txgapk_afe_dpk_restore()
1322 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ab8041); in rtw8822c_txgapk_afe_dpk_restore()
1323 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70bb8041); in rtw8822c_txgapk_afe_dpk_restore()
1324 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70cb8041); in rtw8822c_txgapk_afe_dpk_restore()
1325 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70db8041); in rtw8822c_txgapk_afe_dpk_restore()
1326 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70eb8041); in rtw8822c_txgapk_afe_dpk_restore()
1327 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70fb8041); in rtw8822c_txgapk_afe_dpk_restore()
1334 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1335 rtw_write_rf(rtwdev, path, RF_DIS_BYPASS_TXBB, BIT_TIA_BYPASS, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1336 rtw_write_rf(rtwdev, path, RF_DIS_BYPASS_TXBB, BIT_TXBB, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1338 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1339 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1340 rtw_write32_mask(rtwdev, REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1341 rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, 0x00); in rtw8822c_txgapk_bb_dpk_restore()
1342 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x1); in rtw8822c_txgapk_bb_dpk_restore()
1343 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1344 rtw_write32_mask(rtwdev, REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1345 rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, 0x00); in rtw8822c_txgapk_bb_dpk_restore()
1346 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1347 rtw_write32_mask(rtwdev, REG_CCA_OFF, BIT_CCA_ON_BY_PW, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1351 BIT_RFTXEN_GCK_FORCE_ON, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1352 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_DIS_SHARERX_TXGAT, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1354 BIT_TX_SCALE_0DB, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1355 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_3WIRE_EN, 0x3); in rtw8822c_txgapk_bb_dpk_restore()
1358 BIT_RFTXEN_GCK_FORCE_ON, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1360 BIT_DIS_SHARERX_TXGAT, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1362 BIT_TX_SCALE_0DB, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1363 rtw_write32_mask(rtwdev, REG_3WIRE2, BIT_3WIRE_EN, 0x3); in rtw8822c_txgapk_bb_dpk_restore()
1366 rtw_write32_mask(rtwdev, REG_CCKSB, BIT_BBMODE, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1367 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_CFIR_EN, 0x5); in rtw8822c_txgapk_bb_dpk_restore()
1372 if ((FIELD_GET(BIT_GAIN_TX_PAD_H, gain) >= 0xc) && in _rtw8822c_txgapk_gain_valid()
1373 (FIELD_GET(BIT_GAIN_TX_PAD_L, gain) >= 0xe)) in _rtw8822c_txgapk_gain_valid()
1383 u32 v, tmp_3f = 0; in _rtw8822c_txgapk_write_gain_bb_table()
1390 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x0); in _rtw8822c_txgapk_write_gain_bb_table()
1393 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x2); in _rtw8822c_txgapk_write_gain_bb_table()
1396 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x3); in _rtw8822c_txgapk_write_gain_bb_table()
1399 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x4); in _rtw8822c_txgapk_write_gain_bb_table()
1405 rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, MASKBYTE0, 0x88); in _rtw8822c_txgapk_write_gain_bb_table()
1407 check_txgain = 0; in _rtw8822c_txgapk_write_gain_bb_table()
1408 for (gain = 0; gain < RF_GAIN_NUM; gain++) { in _rtw8822c_txgapk_write_gain_bb_table()
1416 "[TXGAPK] tx_gain=0x%03X >= 0xCEX\n", in _rtw8822c_txgapk_write_gain_bb_table()
1424 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_GAIN_RST, 0x1); in _rtw8822c_txgapk_write_gain_bb_table()
1425 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_GAIN_RST, 0x0); in _rtw8822c_txgapk_write_gain_bb_table()
1428 "[TXGAPK] Band=%d 0x1b98[11:0]=0x%03X path=%d\n", in _rtw8822c_txgapk_write_gain_bb_table()
1440 for (band = 0; band < RF_BAND_MAX; band++) { in rtw8822c_txgapk_write_gain_bb_table()
1441 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8822c_txgapk_write_gain_bb_table()
1450 static const u32 cfg1_1b00[2] = {0x00000d18, 0x00000d2a}; in rtw8822c_txgapk_read_offset()
1451 static const u32 cfg2_1b00[2] = {0x00000d19, 0x00000d2b}; in rtw8822c_txgapk_read_offset()
1468 rtw_write32_mask(rtwdev, REG_TXLGMAP, MASKDWORD, 0xe4e40000); in rtw8822c_txgapk_read_offset()
1469 rtw_write32_mask(rtwdev, REG_TXANTSEG, BIT_ANTSEG, 0x3); in rtw8822c_txgapk_read_offset()
1470 rtw_write32_mask(rtwdev, path_setting[path], MASK20BITS, 0x33312); in rtw8822c_txgapk_read_offset()
1471 rtw_write32_mask(rtwdev, path_setting[path], BIT_PATH_EN, 0x1); in rtw8822c_txgapk_read_offset()
1472 rtw_write32_mask(rtwdev, set_pi[path], BITS_RFC_DIRECT, 0x0); in rtw8822c_txgapk_read_offset()
1473 rtw_write_rf(rtwdev, path, RF_LUTDBG, BIT_TXA_TANK, 0x1); in rtw8822c_txgapk_read_offset()
1474 rtw_write_rf(rtwdev, path, RF_IDAC, BIT_TX_MODE, 0x820); in rtw8822c_txgapk_read_offset()
1476 rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x0); in rtw8822c_txgapk_read_offset()
1478 rtw_write32_mask(rtwdev, REG_TX_TONE_IDX, MASKBYTE0, 0x018); in rtw8822c_txgapk_read_offset()
1490 val == 0x55, 1000, 100000, false, in rtw8822c_txgapk_read_offset()
1493 rtw_write32_mask(rtwdev, set_pi[path], BITS_RFC_DIRECT, 0x2); in rtw8822c_txgapk_read_offset()
1495 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_EN, 0x1); in rtw8822c_txgapk_read_offset()
1496 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x12); in rtw8822c_txgapk_read_offset()
1497 rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, BIT_GAPK_RPT_IDX, 0x3); in rtw8822c_txgapk_read_offset()
1500 txgapk->offset[0][path] = (s8)FIELD_GET(BIT_GAPK_RPT0, val); in rtw8822c_txgapk_read_offset()
1509 rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, BIT_GAPK_RPT_IDX, 0x4); in rtw8822c_txgapk_read_offset()
1515 for (i = 0; i < RF_HW_OFFSET_NUM; i++) in rtw8822c_txgapk_read_offset()
1518 0xf0; in rtw8822c_txgapk_read_offset()
1519 for (i = 0; i < RF_HW_OFFSET_NUM; i++) in rtw8822c_txgapk_read_offset()
1531 u32 reg_backup[ARRAY_SIZE(bb_reg)] = {0}; in rtw8822c_txgapk_calculate_offset()
1541 REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0); in rtw8822c_txgapk_calculate_offset()
1543 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x3f); in rtw8822c_txgapk_calculate_offset()
1544 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); in rtw8822c_txgapk_calculate_offset()
1545 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1); in rtw8822c_txgapk_calculate_offset()
1546 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x5000f); in rtw8822c_txgapk_calculate_offset()
1547 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_RF_GAIN, 0x0); in rtw8822c_txgapk_calculate_offset()
1548 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x1); in rtw8822c_txgapk_calculate_offset()
1549 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0f); in rtw8822c_txgapk_calculate_offset()
1550 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1); in rtw8822c_txgapk_calculate_offset()
1551 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1); in rtw8822c_txgapk_calculate_offset()
1552 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0); in rtw8822c_txgapk_calculate_offset()
1553 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x1); in rtw8822c_txgapk_calculate_offset()
1555 rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x00); in rtw8822c_txgapk_calculate_offset()
1556 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x0); in rtw8822c_txgapk_calculate_offset()
1563 REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0); in rtw8822c_txgapk_calculate_offset()
1565 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x3f); in rtw8822c_txgapk_calculate_offset()
1566 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); in rtw8822c_txgapk_calculate_offset()
1567 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1); in rtw8822c_txgapk_calculate_offset()
1568 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50011); in rtw8822c_txgapk_calculate_offset()
1569 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x3); in rtw8822c_txgapk_calculate_offset()
1570 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x3); in rtw8822c_txgapk_calculate_offset()
1571 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1); in rtw8822c_txgapk_calculate_offset()
1573 RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0x2); in rtw8822c_txgapk_calculate_offset()
1574 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0x12); in rtw8822c_txgapk_calculate_offset()
1575 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1); in rtw8822c_txgapk_calculate_offset()
1576 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0); in rtw8822c_txgapk_calculate_offset()
1577 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x1); in rtw8822c_txgapk_calculate_offset()
1578 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RF_MODE, 0x5); in rtw8822c_txgapk_calculate_offset()
1580 rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x0); in rtw8822c_txgapk_calculate_offset()
1584 REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x2); in rtw8822c_txgapk_calculate_offset()
1587 REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x3); in rtw8822c_txgapk_calculate_offset()
1590 REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x4); in rtw8822c_txgapk_calculate_offset()
1606 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RF_MODE, 0x3); in rtw8822c_txgapk_rf_restore()
1607 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x0); in rtw8822c_txgapk_rf_restore()
1608 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x0); in rtw8822c_txgapk_rf_restore()
1620 "[TXGAPK] gain=0x%03X(>=0xCEX) offset=%d new_gain=0x%03X\n", in rtw8822c_txgapk_cal_gain()
1626 new_gain = (gain_x2 >> 1) | (gain_x2 & BIT(0) ? BIT_GAIN_EXT : 0); in rtw8822c_txgapk_cal_gain()
1629 "[TXGAPK] gain=0x%X offset=%d new_gain=0x%X\n", in rtw8822c_txgapk_cal_gain()
1638 u32 i, j, tmp = 0x20, tmp_3f, v; in rtw8822c_txgapk_write_tx_gain()
1639 s8 offset_tmp[RF_GAIN_NUM] = {0}; in rtw8822c_txgapk_write_tx_gain()
1645 tmp = 0x20; in rtw8822c_txgapk_write_tx_gain()
1648 tmp = 0x200; in rtw8822c_txgapk_write_tx_gain()
1651 tmp = 0x280; in rtw8822c_txgapk_write_tx_gain()
1654 tmp = 0x300; in rtw8822c_txgapk_write_tx_gain()
1661 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8822c_txgapk_write_tx_gain()
1662 for (i = 0; i < RF_GAIN_NUM; i++) { in rtw8822c_txgapk_write_tx_gain()
1663 offset_tmp[i] = 0; in rtw8822c_txgapk_write_tx_gain()
1676 "[TXGAPK] tx_gain=0x%03X >= 0xCEX\n", in rtw8822c_txgapk_write_tx_gain()
1686 rtw_write_rf(rtwdev, path, RF_LUTWE2, RFREG_MASK, 0x10000); in rtw8822c_txgapk_write_tx_gain()
1687 for (i = 0; i < RF_GAIN_NUM; i++) { in rtw8822c_txgapk_write_tx_gain()
1698 "[TXGAPK] 0x33=0x%05X 0x3f=0x%04X\n", in rtw8822c_txgapk_write_tx_gain()
1701 rtw_write_rf(rtwdev, path, RF_LUTWE2, RFREG_MASK, 0x0); in rtw8822c_txgapk_write_tx_gain()
1710 static const u8 band_num[RF_BAND_MAX] = {0x0, 0x0, 0x1, 0x3, 0x5}; in rtw8822c_txgapk_save_all_tx_gain_table()
1711 static const u8 cck[RF_BAND_MAX] = {0x1, 0x0, 0x0, 0x0, 0x0}; in rtw8822c_txgapk_save_all_tx_gain_table()
1727 for (band = 0; band < RF_BAND_MAX; band++) { in rtw8822c_txgapk_save_all_tx_gain_table()
1728 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8822c_txgapk_save_all_tx_gain_table()
1732 three_wire[path], BIT_3WIRE_EN, 0x0); in rtw8822c_txgapk_save_all_tx_gain_table()
1741 gain = 0; in rtw8822c_txgapk_save_all_tx_gain_table()
1750 "[TXGAPK] 0x5f=0x%03X band=%d path=%d\n", in rtw8822c_txgapk_save_all_tx_gain_table()
1757 three_wire[path], BIT_3WIRE_EN, 0x3); in rtw8822c_txgapk_save_all_tx_gain_table()
1775 if (txgapk->read_txgain == 0) { in rtw8822c_txgapk()
1777 "[TXGAPK] txgapk->read_txgain == 0 return!!!\n"); in rtw8822c_txgapk()
1791 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8822c_txgapk()
1834 dm_info->delta_power_index[path] = 0; in rtw8822c_pwrtrack_init()
1836 dm_info->thermal_avg[path] = 0xff; in rtw8822c_pwrtrack_init()
1849 u8 cck_gi_u_bnd_msb = 0; in rtw8822c_phy_set_param()
1850 u8 cck_gi_u_bnd_lsb = 0; in rtw8822c_phy_set_param()
1851 u8 cck_gi_l_bnd_msb = 0; in rtw8822c_phy_set_param()
1852 u8 cck_gi_l_bnd_lsb = 0; in rtw8822c_phy_set_param()
1870 crystal_cap = rtwdev->efuse.crystal_cap & 0x7f; in rtw8822c_phy_set_param()
1871 rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, 0xfffc00, in rtw8822c_phy_set_param()
1882 cck_gi_u_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc000); in rtw8822c_phy_set_param()
1883 cck_gi_u_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1aa8, 0xf0000); in rtw8822c_phy_set_param()
1884 cck_gi_l_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc0); in rtw8822c_phy_set_param()
1885 cck_gi_l_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1a70, 0x0f000000); in rtw8822c_phy_set_param()
1896 #define WLAN_TXQ_RPT_EN 0x1F
1897 #define WLAN_SLOT_TIME 0x09
1898 #define WLAN_PIFS_TIME 0x1C
1899 #define WLAN_SIFS_CCK_CONT_TX 0x0A
1900 #define WLAN_SIFS_OFDM_CONT_TX 0x0E
1901 #define WLAN_SIFS_CCK_TRX 0x0A
1902 #define WLAN_SIFS_OFDM_TRX 0x10
1903 #define WLAN_NAV_MAX 0xC8
1904 #define WLAN_RDG_NAV 0x05
1905 #define WLAN_TXOP_NAV 0x1B
1906 #define WLAN_CCK_RX_TSF 0x30
1907 #define WLAN_OFDM_RX_TSF 0x30
1908 #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */
1909 #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */
1910 #define WLAN_DRV_EARLY_INT 0x04
1911 #define WLAN_BCN_CTRL_CLT0 0x10
1912 #define WLAN_BCN_DMA_TIME 0x02
1913 #define WLAN_BCN_MAX_ERR 0xFF
1914 #define WLAN_SIFS_CCK_DUR_TUNE 0x0A
1915 #define WLAN_SIFS_OFDM_DUR_TUNE 0x10
1916 #define WLAN_SIFS_CCK_CTX 0x0A
1917 #define WLAN_SIFS_CCK_IRX 0x0A
1918 #define WLAN_SIFS_OFDM_CTX 0x0E
1919 #define WLAN_SIFS_OFDM_IRX 0x0E
1920 #define WLAN_EIFS_DUR_TUNE 0x40
1921 #define WLAN_EDCA_VO_PARAM 0x002FA226
1922 #define WLAN_EDCA_VI_PARAM 0x005EA328
1923 #define WLAN_EDCA_BE_PARAM 0x005EA42B
1924 #define WLAN_EDCA_BK_PARAM 0x0000A44F
1926 #define WLAN_RX_FILTER0 0xFFFFFFFF
1927 #define WLAN_RX_FILTER2 0xFFFF
1928 #define WLAN_RCR_CFG 0xE400220E
1932 #define WLAN_AMPDU_MAX_TIME 0x70
1933 #define WLAN_RTS_LEN_TH 0xFF
1934 #define WLAN_RTS_TX_TIME_TH 0x08
1935 #define WLAN_MAX_AGG_PKT_LIMIT 0x3f
1936 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x3f
1937 #define WLAN_PRE_TXCNT_TIME_TH 0x1E0
1938 #define FAST_EDCA_VO_TH 0x06
1939 #define FAST_EDCA_VI_TH 0x06
1940 #define FAST_EDCA_BE_TH 0x06
1941 #define FAST_EDCA_BK_TH 0x06
1942 #define WLAN_BAR_RETRY_LIMIT 0x01
1943 #define WLAN_BAR_ACK_TYPE 0x05
1944 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08
1945 #define WLAN_RESP_TXRATE 0x84
1946 #define WLAN_ACK_TO 0x21
1947 #define WLAN_ACK_TO_CCK 0x6A
1948 #define WLAN_DATA_RATE_FB_CNT_1_4 0x01000000
1949 #define WLAN_DATA_RATE_FB_CNT_5_8 0x08070504
1950 #define WLAN_RTS_RATE_FB_CNT_5_8 0x08070504
1951 #define WLAN_DATA_RATE_FB_RATE0 0xFE01F010
1952 #define WLAN_DATA_RATE_FB_RATE0_H 0x40000000
1953 #define WLAN_RTS_RATE_FB_RATE1 0x003FF010
1954 #define WLAN_RTS_RATE_FB_RATE1_H 0x40000000
1955 #define WLAN_RTS_RATE_FB_RATE4 0x0600F010
1956 #define WLAN_RTS_RATE_FB_RATE4_H 0x400003E0
1957 #define WLAN_RTS_RATE_FB_RATE5 0x0600F015
1958 #define WLAN_RTS_RATE_FB_RATE5_H 0x000000E0
1959 #define WLAN_MULTI_ADDR 0xFFFFFFFF
1961 #define WLAN_TX_FUNC_CFG1 0x30
1962 #define WLAN_TX_FUNC_CFG2 0x30
1963 #define WLAN_MAC_OPT_NORM_FUNC1 0x98
1964 #define WLAN_MAC_OPT_LB_FUNC1 0x80
1965 #define WLAN_MAC_OPT_FUNC2 0xb0810041
1966 #define WLAN_MAC_INT_MIG_CFG 0x33330000
1983 #define EFUSE_PCB_INFO_OFFSET 0xCA
2020 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF)); in rtw8822c_mac_init()
2055 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000); in rtw8822c_mac_init()
2088 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL + 2) & 0xF00F; in rtw8822c_mac_init()
2092 value16 = 0; in rtw8822c_mac_init()
2098 rtw_write32(rtwdev, REG_RXPSF_TYPE_CTRL, 0xFFFFFFFF); in rtw8822c_mac_init()
2103 value16 = BIT_SET_RXPSF_ERRTHR(value16, 0x07); in rtw8822c_mac_init()
2111 return 0; in rtw8822c_mac_init()
2114 #define FWCD_SIZE_REG_8822C 0x2000
2115 #define FWCD_SIZE_DMEM_8822C 0x10000
2116 #define FWCD_SIZE_IMEM_8822C 0x10000
2117 #define FWCD_SIZE_EMEM_8822C 0x20000
2118 #define FWCD_SIZE_ROM_8822C 0x10000
2140 ret = rtw_dump_reg(rtwdev, 0x0, FWCD_SIZE_REG_8822C); in rtw8822c_dump_fw_crash()
2156 return 0; in rtw8822c_dump_fw_crash()
2164 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x1); in rtw8822c_rstb_3wire()
2165 rtw_write32_mask(rtwdev, REG_ANAPAR_A, BIT_ANAPAR_UPDATE, 0x1); in rtw8822c_rstb_3wire()
2166 rtw_write32_mask(rtwdev, REG_ANAPAR_B, BIT_ANAPAR_UPDATE, 0x1); in rtw8822c_rstb_3wire()
2168 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x0); in rtw8822c_rstb_3wire()
2175 #define RF18_BAND_2G (0) in rtw8822c_set_channel_rf()
2186 u32 rf_reg18 = 0; in rtw8822c_set_channel_rf()
2187 u32 rf_rxbb = 0; in rtw8822c_set_channel_rf()
2189 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); in rtw8822c_set_channel_rf()
2207 rf_rxbb = 0x18; in rtw8822c_set_channel_rf()
2212 rf_rxbb = 0x10; in rtw8822c_set_channel_rf()
2216 rf_rxbb = 0x8; in rtw8822c_set_channel_rf()
2222 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x01); in rtw8822c_set_channel_rf()
2223 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, 0x1f, 0x12); in rtw8822c_set_channel_rf()
2224 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, 0xfffff, rf_rxbb); in rtw8822c_set_channel_rf()
2225 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x00); in rtw8822c_set_channel_rf()
2227 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x01); in rtw8822c_set_channel_rf()
2228 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWA, 0x1f, 0x12); in rtw8822c_set_channel_rf()
2229 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWD0, 0xfffff, rf_rxbb); in rtw8822c_set_channel_rf()
2230 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x00); in rtw8822c_set_channel_rf()
2242 igi = rtw_read32_mask(rtwdev, REG_RXIGI, 0x7f); in rtw8822c_toggle_igi()
2243 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi - 2); in rtw8822c_toggle_igi()
2244 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi - 2); in rtw8822c_toggle_igi()
2245 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi); in rtw8822c_toggle_igi()
2246 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi); in rtw8822c_toggle_igi()
2257 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0xF); in rtw8822c_set_channel_bb()
2262 0x5); in rtw8822c_set_channel_bb()
2264 0x5); in rtw8822c_set_channel_bb()
2266 0x6); in rtw8822c_set_channel_bb()
2268 0x6); in rtw8822c_set_channel_bb()
2272 0x4); in rtw8822c_set_channel_bb()
2274 0x4); in rtw8822c_set_channel_bb()
2276 0x0); in rtw8822c_set_channel_bb()
2278 0x0); in rtw8822c_set_channel_bb()
2282 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x969); in rtw8822c_set_channel_bb()
2284 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x96a); in rtw8822c_set_channel_bb()
2286 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x9aa); in rtw8822c_set_channel_bb()
2288 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x3da0); in rtw8822c_set_channel_bb()
2290 0x4962c931); in rtw8822c_set_channel_bb()
2291 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x6aa3); in rtw8822c_set_channel_bb()
2292 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xaa7b); in rtw8822c_set_channel_bb()
2293 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xf3d7); in rtw8822c_set_channel_bb()
2294 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 0x0); in rtw8822c_set_channel_bb()
2296 0xff012455); in rtw8822c_set_channel_bb()
2297 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 0xffff); in rtw8822c_set_channel_bb()
2299 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x5284); in rtw8822c_set_channel_bb()
2301 0x3e18fec8); in rtw8822c_set_channel_bb()
2302 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x0a88); in rtw8822c_set_channel_bb()
2303 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xacc4); in rtw8822c_set_channel_bb()
2304 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xc8b2); in rtw8822c_set_channel_bb()
2306 0x00faf0de); in rtw8822c_set_channel_bb()
2308 0x00122344); in rtw8822c_set_channel_bb()
2310 0x0fffffff); in rtw8822c_set_channel_bb()
2313 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3); in rtw8822c_set_channel_bb()
2315 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x1); in rtw8822c_set_channel_bb()
2321 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0x22); in rtw8822c_set_channel_bb()
2322 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3); in rtw8822c_set_channel_bb()
2325 0x1); in rtw8822c_set_channel_bb()
2327 0x1); in rtw8822c_set_channel_bb()
2330 0x2); in rtw8822c_set_channel_bb()
2332 0x2); in rtw8822c_set_channel_bb()
2335 0x3); in rtw8822c_set_channel_bb()
2337 0x3); in rtw8822c_set_channel_bb()
2341 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x494); in rtw8822c_set_channel_bb()
2343 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x493); in rtw8822c_set_channel_bb()
2345 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x453); in rtw8822c_set_channel_bb()
2347 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x452); in rtw8822c_set_channel_bb()
2349 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x412); in rtw8822c_set_channel_bb()
2351 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x411); in rtw8822c_set_channel_bb()
2356 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x19B); in rtw8822c_set_channel_bb()
2357 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); in rtw8822c_set_channel_bb()
2358 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x0); in rtw8822c_set_channel_bb()
2359 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x7); in rtw8822c_set_channel_bb()
2360 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x6); in rtw8822c_set_channel_bb()
2361 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); in rtw8822c_set_channel_bb()
2362 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); in rtw8822c_set_channel_bb()
2363 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); in rtw8822c_set_channel_bb()
2367 (primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0)); in rtw8822c_set_channel_bb()
2368 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x5); in rtw8822c_set_channel_bb()
2369 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0); in rtw8822c_set_channel_bb()
2370 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00, in rtw8822c_set_channel_bb()
2372 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x1); in rtw8822c_set_channel_bb()
2373 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); in rtw8822c_set_channel_bb()
2374 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1); in rtw8822c_set_channel_bb()
2377 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0xa); in rtw8822c_set_channel_bb()
2378 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0); in rtw8822c_set_channel_bb()
2379 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00, in rtw8822c_set_channel_bb()
2381 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x6); in rtw8822c_set_channel_bb()
2382 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1); in rtw8822c_set_channel_bb()
2385 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB); in rtw8822c_set_channel_bb()
2386 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); in rtw8822c_set_channel_bb()
2387 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x1); in rtw8822c_set_channel_bb()
2388 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x4); in rtw8822c_set_channel_bb()
2389 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x4); in rtw8822c_set_channel_bb()
2390 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); in rtw8822c_set_channel_bb()
2391 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); in rtw8822c_set_channel_bb()
2392 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); in rtw8822c_set_channel_bb()
2395 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB); in rtw8822c_set_channel_bb()
2396 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); in rtw8822c_set_channel_bb()
2397 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x2); in rtw8822c_set_channel_bb()
2398 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x6); in rtw8822c_set_channel_bb()
2399 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x5); in rtw8822c_set_channel_bb()
2400 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); in rtw8822c_set_channel_bb()
2401 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); in rtw8822c_set_channel_bb()
2402 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); in rtw8822c_set_channel_bb()
2419 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x0); in rtw8822c_config_cck_rx_path()
2420 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x0); in rtw8822c_config_cck_rx_path()
2422 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x1); in rtw8822c_config_cck_rx_path()
2423 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x1); in rtw8822c_config_cck_rx_path()
2427 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x0); in rtw8822c_config_cck_rx_path()
2429 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x5); in rtw8822c_config_cck_rx_path()
2431 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x1); in rtw8822c_config_cck_rx_path()
2437 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x0); in rtw8822c_config_ofdm_rx_path()
2438 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x0); in rtw8822c_config_ofdm_rx_path()
2439 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x0); in rtw8822c_config_ofdm_rx_path()
2440 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x0); in rtw8822c_config_ofdm_rx_path()
2441 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x0); in rtw8822c_config_ofdm_rx_path()
2443 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x1); in rtw8822c_config_ofdm_rx_path()
2444 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x1); in rtw8822c_config_ofdm_rx_path()
2445 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x1); in rtw8822c_config_ofdm_rx_path()
2446 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x1); in rtw8822c_config_ofdm_rx_path()
2447 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x1); in rtw8822c_config_ofdm_rx_path()
2450 rtw_write32_mask(rtwdev, 0x824, 0x0f000000, rx_path); in rtw8822c_config_ofdm_rx_path()
2451 rtw_write32_mask(rtwdev, 0x824, 0x000f0000, rx_path); in rtw8822c_config_ofdm_rx_path()
2464 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8); in rtw8822c_config_cck_tx_path()
2466 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x4); in rtw8822c_config_cck_tx_path()
2469 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0xc); in rtw8822c_config_cck_tx_path()
2471 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8); in rtw8822c_config_cck_tx_path()
2480 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x11); in rtw8822c_config_ofdm_tx_path()
2481 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0); in rtw8822c_config_ofdm_tx_path()
2483 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x12); in rtw8822c_config_ofdm_tx_path()
2484 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0); in rtw8822c_config_ofdm_tx_path()
2487 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x33); in rtw8822c_config_ofdm_tx_path()
2488 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0404); in rtw8822c_config_ofdm_tx_path()
2490 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x32); in rtw8822c_config_ofdm_tx_path()
2491 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400); in rtw8822c_config_ofdm_tx_path()
2493 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x31); in rtw8822c_config_ofdm_tx_path()
2494 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400); in rtw8822c_config_ofdm_tx_path()
2514 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x33312); in rtw8822c_config_trx_mode()
2516 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x11111); in rtw8822c_config_trx_mode()
2518 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x33312); in rtw8822c_config_trx_mode()
2520 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x11111); in rtw8822c_config_trx_mode()
2560 if (channel == 0) in query_phy_status_page0()
2567 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { in query_phy_status_page0()
2586 u8 evm_dbm = 0; in query_phy_status_page1()
2625 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { in query_phy_status_page1()
2640 if (rx_evm < 0) { in query_phy_status_page1()
2642 evm_dbm = 0; in query_phy_status_page1()
2656 page = *phy_status & 0xf; in query_phy_status()
2659 case 0: in query_phy_status()
2679 memset(pkt_stat, 0, sizeof(*pkt_stat)); in rtw8822c_query_rx_desc()
2718 u32 txref_cck[2] = {0x18a0, 0x41a0}; in rtw8822c_set_write_tx_power_ref()
2719 u32 txref_ofdm[2] = {0x18e8, 0x41e8}; in rtw8822c_set_write_tx_power_ref()
2722 for (path = 0; path < hal->rf_path_num; path++) { in rtw8822c_set_write_tx_power_ref()
2723 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0); in rtw8822c_set_write_tx_power_ref()
2724 rtw_write32_mask(rtwdev, txref_cck[path], 0x7f0000, in rtw8822c_set_write_tx_power_ref()
2727 for (path = 0; path < hal->rf_path_num; path++) { in rtw8822c_set_write_tx_power_ref()
2728 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0); in rtw8822c_set_write_tx_power_ref()
2729 rtw_write32_mask(rtwdev, txref_ofdm[path], 0x1fc00, in rtw8822c_set_write_tx_power_ref()
2737 u32 offset_txagc = 0x3a00; in rtw8822c_set_tx_power_diff()
2738 u8 rate_idx = rate & 0xfc; in rtw8822c_set_tx_power_diff()
2743 for (i = 0; i < 4; i++) in rtw8822c_set_tx_power_diff()
2744 pwr_idx[i] = diff_idx[i] & 0x7f; in rtw8822c_set_tx_power_diff()
2746 phy_pwr_idx = pwr_idx[0] | in rtw8822c_set_tx_power_diff()
2751 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0x0); in rtw8822c_set_tx_power_diff()
2769 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) { in rtw8822c_set_tx_power_index()
2770 for (j = 0; j < rtw_rate_size[rs]; j++) { in rtw8822c_set_tx_power_index()
2774 if (rs == 0) { in rtw8822c_set_tx_power_index()
2775 diff_a = (s8)pwr_a - (s8)pwr_ref_cck[0]; in rtw8822c_set_tx_power_index()
2778 diff_a = (s8)pwr_a - (s8)pwr_ref_ofdm[0]; in rtw8822c_set_tx_power_index()
2801 rtw_warn(rtwdev, "unsupported tx path 0x%x\n", antenna_tx); in rtw8822c_set_antenna()
2811 rtw_warn(rtwdev, "unsupported rx path 0x%x\n", antenna_rx); in rtw8822c_set_antenna()
2820 return 0; in rtw8822c_set_antenna()
2854 rate_illegal = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt2); in rtw8822c_false_alarm_statistics()
2856 crc8_fail_vhta = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt3); in rtw8822c_false_alarm_statistics()
2857 mcs_fail = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt4); in rtw8822c_false_alarm_statistics()
2859 fast_fsync = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt5); in rtw8822c_false_alarm_statistics()
2868 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0; in rtw8822c_false_alarm_statistics()
2870 crc32_cnt = rtw_read32(rtwdev, 0x2c04); in rtw8822c_false_alarm_statistics()
2871 dm_info->cck_ok_cnt = crc32_cnt & 0xffff; in rtw8822c_false_alarm_statistics()
2872 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16; in rtw8822c_false_alarm_statistics()
2873 crc32_cnt = rtw_read32(rtwdev, 0x2c14); in rtw8822c_false_alarm_statistics()
2874 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff; in rtw8822c_false_alarm_statistics()
2875 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16; in rtw8822c_false_alarm_statistics()
2876 crc32_cnt = rtw_read32(rtwdev, 0x2c10); in rtw8822c_false_alarm_statistics()
2877 dm_info->ht_ok_cnt = crc32_cnt & 0xffff; in rtw8822c_false_alarm_statistics()
2878 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; in rtw8822c_false_alarm_statistics()
2879 crc32_cnt = rtw_read32(rtwdev, 0x2c0c); in rtw8822c_false_alarm_statistics()
2880 dm_info->vht_ok_cnt = crc32_cnt & 0xffff; in rtw8822c_false_alarm_statistics()
2881 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; in rtw8822c_false_alarm_statistics()
2883 cca32_cnt = rtw_read32(rtwdev, 0x2c08); in rtw8822c_false_alarm_statistics()
2884 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16); in rtw8822c_false_alarm_statistics()
2885 dm_info->cck_cca_cnt = cca32_cnt & 0xffff; in rtw8822c_false_alarm_statistics()
2890 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 0); in rtw8822c_false_alarm_statistics()
2892 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 0); in rtw8822c_false_alarm_statistics()
2906 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_CTRL, RFREG_MASK, 0x80010); in rtw8822c_do_lck()
2907 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_PFD, RFREG_MASK, 0x1F0FA); in rtw8822c_do_lck()
2909 rtw_write_rf(rtwdev, RF_PATH_A, RF_AAC_CTRL, RFREG_MASK, 0x80000); in rtw8822c_do_lck()
2910 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_AAC, RFREG_MASK, 0x80001); in rtw8822c_do_lck()
2911 read_poll_timeout(rtw_read_rf, val, val != 0x1, 1000, 100000, in rtw8822c_do_lck()
2912 true, rtwdev, RF_PATH_A, RF_AAC_CTRL, 0x1000); in rtw8822c_do_lck()
2913 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_PFD, RFREG_MASK, 0x1F0F8); in rtw8822c_do_lck()
2914 rtw_write_rf(rtwdev, RF_PATH_B, RF_SYN_CTRL, RFREG_MASK, 0x80010); in rtw8822c_do_lck()
2916 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x0f000); in rtw8822c_do_lck()
2917 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x4f000); in rtw8822c_do_lck()
2919 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x0f000); in rtw8822c_do_lck()
2924 struct rtw_iqk_para para = {0}; in rtw8822c_do_iqk()
2936 rtw_write8(rtwdev, REG_IQKSTAT, 0x0); in rtw8822c_do_iqk()
2946 /* 0x790[5:0]=0x5 */ in rtw8822c_coex_cfg_init()
2947 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); in rtw8822c_coex_cfg_init()
2950 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); in rtw8822c_coex_cfg_init()
2966 rtw_write_rf(rtwdev, RF_PATH_B, RF_MODOPT, 0xfffff, 0x40000); in rtw8822c_coex_cfg_init()
2981 if ((coex_stat->kt_ver == 0 && coex->under_5g) || coex->freerun) in rtw8822c_coex_cfg_gnt_fix()
2982 rf_0x1 = 0x40021; in rtw8822c_coex_cfg_gnt_fix()
2984 rf_0x1 = 0x40000; in rtw8822c_coex_cfg_gnt_fix()
2990 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, rf_0x1); in rtw8822c_coex_cfg_gnt_fix()
2994 * disable:0x1860[3] = 1, enable:0x1860[3] = 0 in rtw8822c_coex_cfg_gnt_fix()
2996 * enable "DAC off if GNT_WL = 0" for non-shared-antenna in rtw8822c_coex_cfg_gnt_fix()
2997 * disable 0x1c30[22] = 0, in rtw8822c_coex_cfg_gnt_fix()
2998 * enable: 0x1c30[22] = 1, 0x1c38[12] = 0, 0x1c38[28] = 1 in rtw8822c_coex_cfg_gnt_fix()
3002 BIT_ANAPAR_BTPS >> 16, 0); in rtw8822c_coex_cfg_gnt_fix()
3007 BIT_DAC_OFF_ENABLE, 0); in rtw8822c_coex_cfg_gnt_fix()
3030 BIT_PI_IGNORE_GNT_BT, 0); in rtw8822c_coex_cfg_gnt_fix()
3040 BIT_PI_IGNORE_GNT_BT, 0); in rtw8822c_coex_cfg_gnt_fix()
3043 BIT_NOMASK_TXBT_ENABLE, 0); in rtw8822c_coex_cfg_gnt_fix()
3050 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0); in rtw8822c_coex_cfg_gnt_debug()
3051 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0); in rtw8822c_coex_cfg_gnt_debug()
3052 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0); in rtw8822c_coex_cfg_gnt_debug()
3053 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0); in rtw8822c_coex_cfg_gnt_debug()
3054 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0); in rtw8822c_coex_cfg_gnt_debug()
3064 coex_rfe->ant_switch_polarity = 0; in rtw8822c_coex_cfg_rfe_type()
3075 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0); in rtw8822c_coex_cfg_rfe_type()
3076 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff); in rtw8822c_coex_cfg_rfe_type()
3077 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff); in rtw8822c_coex_cfg_rfe_type()
3105 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, RFREG_MASK, 0x22); in rtw8822c_coex_cfg_wl_rx_gain()
3106 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, RFREG_MASK, 0x36); in rtw8822c_coex_cfg_wl_rx_gain()
3107 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, RFREG_MASK, 0x22); in rtw8822c_coex_cfg_wl_rx_gain()
3108 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, RFREG_MASK, 0x36); in rtw8822c_coex_cfg_wl_rx_gain()
3114 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, RFREG_MASK, 0x20); in rtw8822c_coex_cfg_wl_rx_gain()
3115 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, RFREG_MASK, 0x0); in rtw8822c_coex_cfg_wl_rx_gain()
3116 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, RFREG_MASK, 0x20); in rtw8822c_coex_cfg_wl_rx_gain()
3117 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, RFREG_MASK, 0x0); in rtw8822c_coex_cfg_wl_rx_gain()
3125 u8 csi_rsc = 0; in rtw8822c_bf_enable_bfee_su()
3138 rtw_write32(rtwdev, REG_CSI_RRSR, 0x550); in rtw8822c_bf_enable_bfee_su()
3195 dpk_info->gnt_control = rtw_read32(rtwdev, 0x70); in rtw8822c_dpk_set_gnt_wl()
3196 dpk_info->gnt_value = rtw_coex_read_indirect_reg(rtwdev, 0x38); in rtw8822c_dpk_set_gnt_wl()
3197 rtw_write32_mask(rtwdev, 0x70, BIT(26), 0x1); in rtw8822c_dpk_set_gnt_wl()
3198 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKBYTE1, 0x77); in rtw8822c_dpk_set_gnt_wl()
3200 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKDWORD, in rtw8822c_dpk_set_gnt_wl()
3202 rtw_write32(rtwdev, 0x70, dpk_info->gnt_control); in rtw8822c_dpk_set_gnt_wl()
3211 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); in rtw8822c_dpk_restore_registers()
3212 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0x4); in rtw8822c_dpk_restore_registers()
3221 for (i = 0; i < reg_num; i++) { in rtw8822c_dpk_backup_registers()
3234 for (i = 0; i < DPK_RF_REG_NUM; i++) { in rtw8822c_dpk_backup_rf_registers()
3248 for (i = 0; i < DPK_RF_REG_NUM; i++) { in rtw8822c_dpk_reload_rf_registers()
3262 reg = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); in rtw8822c_dpk_information()
3266 dpk_info->dpk_ch = FIELD_GET(0xff, reg); in rtw8822c_dpk_information()
3267 dpk_info->dpk_bw = FIELD_GET(0x3000, reg); in rtw8822c_dpk_information()
3272 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800); in rtw8822c_dpk_rxbb_dc_cal()
3274 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84801); in rtw8822c_dpk_rxbb_dc_cal()
3276 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800); in rtw8822c_dpk_rxbb_dc_cal()
3284 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000900f0); in rtw8822c_dpk_dc_corr_check()
3286 dc_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(11, 0)); in rtw8822c_dpk_dc_corr_check()
3289 dc_i = 0x1000 - dc_i; in rtw8822c_dpk_dc_corr_check()
3291 dc_q = 0x1000 - dc_q; in rtw8822c_dpk_dc_corr_check()
3293 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); in rtw8822c_dpk_dc_corr_check()
3294 corr_idx = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(7, 0)); in rtw8822c_dpk_dc_corr_check()
3300 return 0; in rtw8822c_dpk_dc_corr_check()
3307 u16 count = 0; in rtw8822c_dpk_tx_pause()
3309 rtw_write8(rtwdev, 0x522, 0xff); in rtw8822c_dpk_tx_pause()
3310 rtw_write32_mask(rtwdev, 0x1e70, 0xf, 0x2); in rtw8822c_dpk_tx_pause()
3313 reg_a = (u8)rtw_read_rf(rtwdev, RF_PATH_A, 0x00, 0xf0000); in rtw8822c_dpk_tx_pause()
3314 reg_b = (u8)rtw_read_rf(rtwdev, RF_PATH_B, 0x00, 0xf0000); in rtw8822c_dpk_tx_pause()
3338 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8822c_dpk_pre_setting()
3339 rtw_write_rf(rtwdev, path, RF_RXAGC_OFFSET, RFREG_MASK, 0x0); in rtw8822c_dpk_pre_setting()
3340 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1)); in rtw8822c_dpk_pre_setting()
3342 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f100000); in rtw8822c_dpk_pre_setting()
3344 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f0d0000); in rtw8822c_dpk_pre_setting()
3345 rtw_write32_mask(rtwdev, REG_DPD_LUT0, BIT_GLOSS_DB, 0x4); in rtw8822c_dpk_pre_setting()
3346 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x3); in rtw8822c_dpk_pre_setting()
3348 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); in rtw8822c_dpk_pre_setting()
3349 rtw_write32(rtwdev, REG_DPD_CTL11, 0x3b23170b); in rtw8822c_dpk_pre_setting()
3350 rtw_write32(rtwdev, REG_DPD_CTL12, 0x775f5347); in rtw8822c_dpk_pre_setting()
3357 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50017); in rtw8822c_dpk_rf_setting()
3360 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1); in rtw8822c_dpk_rf_setting()
3361 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_PWR_TRIM, 0x1); in rtw8822c_dpk_rf_setting()
3362 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_BB_GAIN, 0x0); in rtw8822c_dpk_rf_setting()
3366 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_RF_GAIN, 0x1); in rtw8822c_dpk_rf_setting()
3367 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x0); in rtw8822c_dpk_rf_setting()
3369 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x0); in rtw8822c_dpk_rf_setting()
3370 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x6); in rtw8822c_dpk_rf_setting()
3371 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1); in rtw8822c_dpk_rf_setting()
3372 rtw_write_rf(rtwdev, path, RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0); in rtw8822c_dpk_rf_setting()
3375 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf); in rtw8822c_dpk_rf_setting()
3376 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1); in rtw8822c_dpk_rf_setting()
3377 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0); in rtw8822c_dpk_rf_setting()
3380 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x2); in rtw8822c_dpk_rf_setting()
3382 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1); in rtw8822c_dpk_rf_setting()
3384 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT(1), 0x1); in rtw8822c_dpk_rf_setting()
3388 return ori_txbb & 0x1f; in rtw8822c_dpk_rf_setting()
3394 u8 bw = rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80 ? 2 : 0; in rtw8822c_dpk_get_cmd()
3398 cmd = 0x14 + path; in rtw8822c_dpk_get_cmd()
3401 cmd = 0x16 + path + bw; in rtw8822c_dpk_get_cmd()
3404 cmd = 0x1a + path; in rtw8822c_dpk_get_cmd()
3407 cmd = 0x1c + path + bw; in rtw8822c_dpk_get_cmd()
3410 return 0; in rtw8822c_dpk_get_cmd()
3413 return (cmd << 8) | 0x48; in rtw8822c_dpk_get_cmd()
3419 u8 result = 0; in rtw8822c_dpk_one_shot()
3424 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x1); in rtw8822c_dpk_one_shot()
3425 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x0); in rtw8822c_dpk_one_shot()
3426 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0); in rtw8822c_dpk_one_shot()
3428 if (!check_hw_ready(rtwdev, REG_STAT_RPT, BIT(31), 0x1)) { in rtw8822c_dpk_one_shot()
3434 0x8 | (path << 1)); in rtw8822c_dpk_one_shot()
3435 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9); in rtw8822c_dpk_one_shot()
3441 if (!check_hw_ready(rtwdev, 0x2d9c, 0xff, 0x55)) { in rtw8822c_dpk_one_shot()
3446 0x8 | (path << 1)); in rtw8822c_dpk_one_shot()
3447 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0); in rtw8822c_dpk_one_shot()
3452 rtw_write8(rtwdev, 0x1b10, 0x0); in rtw8822c_dpk_one_shot()
3461 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); in rtw8822c_dpk_dgain_read()
3462 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, 0x00ff0000, 0x0); in rtw8822c_dpk_dgain_read()
3471 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1); in rtw8822c_dpk_thermal_read()
3472 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x0); in rtw8822c_dpk_thermal_read()
3473 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1); in rtw8822c_dpk_thermal_read()
3476 return (u8)rtw_read_rf(rtwdev, path, RF_T_METER, 0x0007e); in rtw8822c_dpk_thermal_read()
3483 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1)); in rtw8822c_dpk_pas_read()
3484 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0); in rtw8822c_dpk_pas_read()
3485 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060001); in rtw8822c_dpk_pas_read()
3486 rtw_write32(rtwdev, 0x1b4c, 0x00000000); in rtw8822c_dpk_pas_read()
3487 rtw_write32(rtwdev, 0x1b4c, 0x00080000); in rtw8822c_dpk_pas_read()
3493 i_val = 0x10000 - i_val; in rtw8822c_dpk_pas_read()
3495 q_val = 0x10000 - q_val; in rtw8822c_dpk_pas_read()
3497 rtw_write32(rtwdev, 0x1b4c, 0x00000000); in rtw8822c_dpk_pas_read()
3506 u32 table_fraction[21] = {0, 432, 332, 274, 232, 200, 174, in rtw8822c_psd_log2base()
3508 42, 32, 23, 15, 7, 0}; in rtw8822c_psd_log2base()
3510 if (val == 0) in rtw8822c_psd_log2base()
3511 return 0; in rtw8822c_psd_log2base()
3532 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); in rtw8822c_dpk_gainloss_result()
3533 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x1); in rtw8822c_dpk_gainloss_result()
3534 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060000); in rtw8822c_dpk_gainloss_result()
3536 result = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, 0x000000f0); in rtw8822c_dpk_gainloss_result()
3538 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0); in rtw8822c_dpk_gainloss_result()
3546 u8 result = 0; in rtw8822c_dpk_agc_gain_chk()
3565 if (loss < 0x4000000) in rtw8822c_dpk_agc_loss_chk()
3622 if (pga > 0xe) in rtw8822c_gain_large_state()
3623 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc); in rtw8822c_gain_large_state()
3624 else if (pga > 0xb && pga < 0xf) in rtw8822c_gain_large_state()
3625 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0); in rtw8822c_gain_large_state()
3626 else if (pga < 0xc) in rtw8822c_gain_large_state()
3637 if (pga < 0xc) in rtw8822c_gain_less_state()
3638 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc); in rtw8822c_gain_less_state()
3639 else if (pga > 0xb && pga < 0xf) in rtw8822c_gain_less_state()
3640 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf); in rtw8822c_gain_less_state()
3641 else if (pga > 0xe) in rtw8822c_gain_less_state()
3650 u8 txbb_bound[] = {0x1f, 0}; in rtw8822c_gl_state()
3661 data->limited_pga = 0; in rtw8822c_gl_state()
3675 return rtw8822c_gl_state(rtwdev, data, 0); in rtw8822c_gl_less_state()
3699 struct rtw8822c_dpk_data data = {0}; in rtw8822c_dpk_pas_agc()
3720 if (coef_i == 0x1000 || coef_i == 0x0fff || in rtw8822c_dpk_coef_iq_check()
3721 coef_q == 0x1000 || coef_q == 0x0fff) in rtw8822c_dpk_coef_iq_check()
3729 u32 reg = 0; in rtw8822c_dpk_coef_transfer()
3730 u16 coef_i = 0, coef_q = 0; in rtw8822c_dpk_coef_transfer()
3734 coef_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD) & 0x1fff; in rtw8822c_dpk_coef_transfer()
3735 coef_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD) & 0x1fff; in rtw8822c_dpk_coef_transfer()
3737 coef_q = ((0x2000 - coef_q) & 0x1fff) - 1; in rtw8822c_dpk_coef_transfer()
3745 0x000400f0, 0x040400f0, 0x080400f0, 0x010400f0, 0x050400f0,
3746 0x090400f0, 0x020400f0, 0x060400f0, 0x0a0400f0, 0x030400f0,
3747 0x070400f0, 0x0b0400f0, 0x0c0400f0, 0x100400f0, 0x0d0400f0,
3748 0x110400f0, 0x0e0400f0, 0x120400f0, 0x0f0400f0, 0x130400f0,
3756 for (i = 0; i < 20; i++) { in rtw8822c_dpk_coef_tbl_apply()
3765 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c); in rtw8822c_dpk_get_coef()
3768 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x0); in rtw8822c_dpk_get_coef()
3769 rtw_write32(rtwdev, REG_DPD_CTL0_S0, 0x30000080); in rtw8822c_dpk_get_coef()
3771 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x1); in rtw8822c_dpk_get_coef()
3772 rtw_write32(rtwdev, REG_DPD_CTL0_S1, 0x30000080); in rtw8822c_dpk_get_coef()
3784 for (addr = 0; addr < 20; addr++) { in rtw8822c_dpk_coef_read()
3785 coef_i = FIELD_GET(0x1fff0000, dpk_info->coef[path][addr]); in rtw8822c_dpk_coef_read()
3786 coef_q = FIELD_GET(0x1fff, dpk_info->coef[path][addr]); in rtw8822c_dpk_coef_read()
3789 result = 0; in rtw8822c_dpk_coef_read()
3799 u16 reg[DPK_RF_PATH_NUM] = {0x1b0c, 0x1b64}; in rtw8822c_dpk_coef_write()
3803 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c); in rtw8822c_dpk_coef_write()
3804 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); in rtw8822c_dpk_coef_write()
3806 for (addr = 0; addr < 20; addr++) { in rtw8822c_dpk_coef_write()
3807 if (result == 0) { in rtw8822c_dpk_coef_write()
3809 coef = 0x04001fff; in rtw8822c_dpk_coef_write()
3811 coef = 0x00001fff; in rtw8822c_dpk_coef_write()
3824 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); in rtw8822c_dpk_fill_result()
3829 rtw_write8(rtwdev, REG_DPD_AGC, 0x00); in rtw8822c_dpk_fill_result()
3860 tx_bb = 0; in rtw8822c_dpk_gainloss()
3881 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); in rtw8822c_dpk_by_path()
3885 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x33e14); in rtw8822c_dpk_by_path()
3895 u32 tmp_gs = 0; in rtw8822c_dpk_cal_gs()
3897 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); in rtw8822c_dpk_cal_gs()
3898 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_BYPASS_DPD, 0x0); in rtw8822c_dpk_cal_gs()
3899 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); in rtw8822c_dpk_cal_gs()
3900 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9); in rtw8822c_dpk_cal_gs()
3901 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x1); in rtw8822c_dpk_cal_gs()
3902 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); in rtw8822c_dpk_cal_gs()
3903 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0xf); in rtw8822c_dpk_cal_gs()
3907 0x1066680); in rtw8822c_dpk_cal_gs()
3908 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN, 0x1); in rtw8822c_dpk_cal_gs()
3911 0x1066680); in rtw8822c_dpk_cal_gs()
3912 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN, 0x1); in rtw8822c_dpk_cal_gs()
3916 rtw_write32(rtwdev, REG_DPD_CTL16, 0x80001310); in rtw8822c_dpk_cal_gs()
3917 rtw_write32(rtwdev, REG_DPD_CTL16, 0x00001310); in rtw8822c_dpk_cal_gs()
3918 rtw_write32(rtwdev, REG_DPD_CTL16, 0x810000db); in rtw8822c_dpk_cal_gs()
3919 rtw_write32(rtwdev, REG_DPD_CTL16, 0x010000db); in rtw8822c_dpk_cal_gs()
3920 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428); in rtw8822c_dpk_cal_gs()
3922 0x05020000 | (BIT(path) << 28)); in rtw8822c_dpk_cal_gs()
3924 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8200190c); in rtw8822c_dpk_cal_gs()
3925 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0200190c); in rtw8822c_dpk_cal_gs()
3926 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8301ee14); in rtw8822c_dpk_cal_gs()
3927 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0301ee14); in rtw8822c_dpk_cal_gs()
3928 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428); in rtw8822c_dpk_cal_gs()
3930 0x05020008 | (BIT(path) << 28)); in rtw8822c_dpk_cal_gs()
3933 rtw_write32_mask(rtwdev, REG_DPD_CTL0, MASKBYTE3, 0x8 | path); in rtw8822c_dpk_cal_gs()
3937 rtw_write32_mask(rtwdev, REG_DPD_CTL15, MASKBYTE3, 0x0); in rtw8822c_dpk_cal_gs()
3938 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); in rtw8822c_dpk_cal_gs()
3939 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0); in rtw8822c_dpk_cal_gs()
3940 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x0); in rtw8822c_dpk_cal_gs()
3941 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); in rtw8822c_dpk_cal_gs()
3944 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 0x5b); in rtw8822c_dpk_cal_gs()
3946 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 0x5b); in rtw8822c_dpk_cal_gs()
3948 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0); in rtw8822c_dpk_cal_gs()
3965 u32 offset[DPK_RF_PATH_NUM] = {0, 0x58}; in rtw8822c_dpk_cal_coef1()
3969 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c); in rtw8822c_dpk_cal_coef1()
3970 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); in rtw8822c_dpk_cal_coef1()
3971 rtw_write32(rtwdev, REG_NCTL0, 0x00001148); in rtw8822c_dpk_cal_coef1()
3972 rtw_write32(rtwdev, REG_NCTL0, 0x00001149); in rtw8822c_dpk_cal_coef1()
3974 check_hw_ready(rtwdev, 0x2d9c, MASKBYTE0, 0x55); in rtw8822c_dpk_cal_coef1()
3976 rtw_write8(rtwdev, 0x1b10, 0x0); in rtw8822c_dpk_cal_coef1()
3977 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c); in rtw8822c_dpk_cal_coef1()
3979 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8822c_dpk_cal_coef1()
3980 i_scaling = 0x16c00 / dpk_info->dpk_gs[path]; in rtw8822c_dpk_cal_coef1()
3982 rtw_write32_mask(rtwdev, 0x1b18 + offset[path], MASKHWORD, in rtw8822c_dpk_cal_coef1()
3985 GENMASK(31, 28), 0x9); in rtw8822c_dpk_cal_coef1()
3987 GENMASK(31, 28), 0x1); in rtw8822c_dpk_cal_coef1()
3989 GENMASK(31, 28), 0x0); in rtw8822c_dpk_cal_coef1()
3991 BIT(14), 0x0); in rtw8822c_dpk_cal_coef1()
4001 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); in rtw8822c_dpk_on()
4002 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); in rtw8822c_dpk_on()
4032 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8822c_dpk_result_reset()
4035 0x8 | (path << 1)); in rtw8822c_dpk_result_reset()
4036 rtw_write32_mask(rtwdev, 0x1b58, 0x0000007f, 0x0); in rtw8822c_dpk_result_reset()
4038 dpk_info->dpk_txagc[path] = 0; in rtw8822c_dpk_result_reset()
4039 dpk_info->result[path] = 0; in rtw8822c_dpk_result_reset()
4040 dpk_info->dpk_gs[path] = 0x5b; in rtw8822c_dpk_result_reset()
4041 dpk_info->pre_pwsf[path] = 0; in rtw8822c_dpk_result_reset()
4082 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); in rtw8822c_dpk_enable_disable()
4090 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, mask, 0x0); in rtw8822c_dpk_enable_disable()
4094 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, mask, 0x0); in rtw8822c_dpk_enable_disable()
4106 dpk_info->dpk_ch == 0) in rtw8822c_dpk_reload_data()
4109 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8822c_dpk_reload_data()
4111 0x8 | (path << 1)); in rtw8822c_dpk_reload_data()
4113 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f100000); in rtw8822c_dpk_reload_data()
4115 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f0d0000); in rtw8822c_dpk_reload_data()
4124 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); in rtw8822c_dpk_reload_data()
4143 channel = (u8)(rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK) & 0xff); in rtw8822c_dpk_reload()
4161 0x520, 0x820, 0x824, 0x1c3c, 0x1d58, 0x1864, in rtw8822c_do_dpk()
4162 0x4164, 0x180c, 0x410c, 0x186c, 0x416c, in rtw8822c_do_dpk()
4163 0x1a14, 0x1e70, 0x80c, 0x1d70, 0x1e7c, 0x18a4, 0x41a4}; in rtw8822c_do_dpk()
4165 0x0, 0x1a, 0x55, 0x63, 0x87, 0x8f, 0xde}; in rtw8822c_do_dpk()
4192 for (path = 0; path < rtwdev->hal.rf_path_num; path++) in rtw8822c_do_dpk()
4210 u8 thermal_value[DPK_RF_PATH_NUM] = {0}; in rtw8822c_dpk_track()
4213 if (dpk_info->thermal_dpk[0] == 0 && dpk_info->thermal_dpk[1] == 0) in rtw8822c_dpk_track()
4216 for (path = 0; path < DPK_RF_PATH_NUM; path++) { in rtw8822c_dpk_track()
4226 offset[path] &= 0x7f; in rtw8822c_dpk_track()
4230 0x8 | (path << 1)); in rtw8822c_dpk_track()
4231 rtw_write32_mask(rtwdev, 0x1b58, GENMASK(6, 0), in rtw8822c_dpk_track()
4243 u32 val = 0; in rtw8822c_set_crystal_cap_reg()
4288 s32 cfo_avg, cfo_path_sum = 0, cfo_rpt_sum; in rtw8822c_cfo_calc_avg()
4291 for (i = 0; i < path_num; i++) { in rtw8822c_cfo_calc_avg()
4297 cfo_avg = 0; in rtw8822c_cfo_calc_avg()
4302 for (i = 0; i < path_num; i++) { in rtw8822c_cfo_calc_avg()
4303 cfo->cfo_tail[i] = 0; in rtw8822c_cfo_calc_avg()
4304 cfo->cfo_cnt[i] = 0; in rtw8822c_cfo_calc_avg()
4335 s32 cfo_avg = 0; in rtw8822c_cfo_track()
4355 crystal_cap = clamp_t(s8, crystal_cap, 0, XCAP_MASK); in rtw8822c_cfo_track()
4363 {0x1ac8, 0x00ff, 0x1ad0, 0x01f},
4364 {0x1ac8, 0xff00, 0x1ad0, 0x3e0}
4367 {0x1acc, 0x00ff, 0x1ad0, 0x01F00000},
4368 {0x1acc, 0xff00, 0x1ad0, 0x3E000000}
4409 "is_linked=%d, bw=%d, nrx=%d, cs_ratio=0x%x, pd_th=0x%x\n", in rtw8822c_phy_cck_pd_set_reg()
4416 s8 pd_lvl[CCK_PD_LV_MAX] = {0, 2, 4, 6, 8}; in rtw8822c_phy_cck_pd_set()
4417 s8 cs_lvl[CCK_PD_LV_MAX] = {0, 2, 2, 2, 4}; in rtw8822c_phy_cck_pd_set()
4421 nrx = (u8)rtw_read32_mask(rtwdev, 0x1a2c, 0x60000); in rtw8822c_phy_cck_pd_set()
4422 bw = (u8)rtw_read32_mask(rtwdev, 0x9b0, 0xc); in rtw8822c_phy_cck_pd_set()
4443 #define PWR_TRACK_MASK 0x7f
4450 rtw_write32_mask(rtwdev, 0x18a0, PWR_TRACK_MASK, in rtw8822c_pwrtrack_set()
4454 rtw_write32_mask(rtwdev, 0x41a0, PWR_TRACK_MASK, in rtw8822c_pwrtrack_set()
4466 if (rtwdev->efuse.thermal_meter[path] == 0xff) in rtw8822c_pwr_track_stats()
4469 thermal_value = rtw_read_rf(rtwdev, path, RF_T_METER, 0x7e); in rtw8822c_pwr_track_stats()
4494 for (i = 0; i < rtwdev->hal.rf_path_num; i++) in __rtw8822c_pwr_track()
4498 for (i = 0; i < rtwdev->hal.rf_path_num; i++) in __rtw8822c_pwr_track()
4507 if (efuse->power_track_type != 0) in rtw8822c_pwr_track()
4511 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01); in rtw8822c_pwr_track()
4512 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x00); in rtw8822c_pwr_track()
4513 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01); in rtw8822c_pwr_track()
4515 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01); in rtw8822c_pwr_track()
4516 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x00); in rtw8822c_pwr_track()
4517 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01); in rtw8822c_pwr_track()
4545 igi = dm_info->igi_history[0]; in rtw8822c_adaptivity()
4561 {0x0086,
4565 RTW_PWR_CMD_WRITE, BIT(0), 0},
4566 {0x0086,
4571 {0x002E,
4576 {0x002D,
4580 RTW_PWR_CMD_WRITE, BIT(0), 0},
4581 {0x007F,
4585 RTW_PWR_CMD_WRITE, BIT(7), 0},
4586 {0x004A,
4590 RTW_PWR_CMD_WRITE, BIT(0), 0},
4591 {0x0005,
4595 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
4596 {0xFFFF,
4599 0,
4600 RTW_PWR_CMD_END, 0, 0},
4604 {0x0000,
4608 RTW_PWR_CMD_WRITE, BIT(5), 0},
4609 {0x0005,
4613 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
4614 {0x0075,
4618 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
4619 {0x0006,
4624 {0x0075,
4628 RTW_PWR_CMD_WRITE, BIT(0), 0},
4629 {0xFF1A,
4633 RTW_PWR_CMD_WRITE, 0xFF, 0},
4634 {0x002E,
4638 RTW_PWR_CMD_WRITE, BIT(3), 0},
4639 {0x0006,
4643 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
4644 {0x0005,
4648 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
4649 {0x1018,
4654 {0x0005,
4658 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
4659 {0x0005,
4663 RTW_PWR_CMD_POLLING, BIT(0), 0},
4664 {0x0074,
4669 {0x0071,
4673 RTW_PWR_CMD_WRITE, BIT(4), 0},
4674 {0x0062,
4680 {0x0061,
4684 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
4685 {0x001F,
4690 {0x00EF,
4695 {0x1045,
4700 {0x0010,
4705 {0x1064,
4710 {0xFFFF,
4713 0,
4714 RTW_PWR_CMD_END, 0, 0},
4718 {0x0093,
4722 RTW_PWR_CMD_WRITE, BIT(3), 0},
4723 {0x001F,
4727 RTW_PWR_CMD_WRITE, 0xFF, 0},
4728 {0x00EF,
4732 RTW_PWR_CMD_WRITE, 0xFF, 0},
4733 {0x1045,
4737 RTW_PWR_CMD_WRITE, BIT(4), 0},
4738 {0xFF1A,
4742 RTW_PWR_CMD_WRITE, 0xFF, 0x30},
4743 {0x0049,
4747 RTW_PWR_CMD_WRITE, BIT(1), 0},
4748 {0x0006,
4752 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
4753 {0x0002,
4757 RTW_PWR_CMD_WRITE, BIT(1), 0},
4758 {0x0005,
4763 {0x0005,
4767 RTW_PWR_CMD_POLLING, BIT(1), 0},
4768 {0x0000,
4773 {0xFFFF,
4776 0,
4777 RTW_PWR_CMD_END, 0, 0},
4781 {0x0005,
4786 {0x0007,
4790 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
4791 {0x0067,
4795 RTW_PWR_CMD_WRITE, BIT(5), 0},
4796 {0x004A,
4800 RTW_PWR_CMD_WRITE, BIT(0), 0},
4801 {0x0081,
4805 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
4806 {0x0090,
4810 RTW_PWR_CMD_WRITE, BIT(1), 0},
4811 {0x0092,
4815 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
4816 {0x0093,
4820 RTW_PWR_CMD_WRITE, 0xFF, 0x04},
4821 {0x0005,
4826 {0x0005,
4831 {0x0086,
4835 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
4836 {0xFFFF,
4839 0,
4840 RTW_PWR_CMD_END, 0, 0},
4856 {0xFFFF, 0x00,
4863 {0xFFFF, 0x0000,
4870 {0xFFFF, 0x0000,
4877 {0xFFFF, 0x0000,
4895 [0] = RTW_DEF_RFE(8822c, 0, 0),
4896 [1] = RTW_DEF_RFE(8822c, 0, 0),
4897 [2] = RTW_DEF_RFE(8822c, 0, 0),
4898 [5] = RTW_DEF_RFE(8822c, 0, 5),
4899 [6] = RTW_DEF_RFE(8822c, 0, 0),
4903 [0] = { .addr = 0x1d70, .mask = 0x7f },
4904 [1] = { .addr = 0x1d70, .mask = 0x7f00 },
4916 {64, 64, 0, 0, 1},
4917 {64, 64, 64, 0, 1},
4993 {0xffffffff, 0xffffffff}, /* case-0 */
4994 {0x55555555, 0x55555555},
4995 {0x66555555, 0x66555555},
4996 {0xaaaaaaaa, 0xaaaaaaaa},
4997 {0x5a5a5a5a, 0x5a5a5a5a},
4998 {0xfafafafa, 0xfafafafa}, /* case-5 */
4999 {0x6a5a5555, 0xaaaaaaaa},
5000 {0x6a5a56aa, 0x6a5a56aa},
5001 {0x6a5a5a5a, 0x6a5a5a5a},
5002 {0x66555555, 0x5a5a5a5a},
5003 {0x66555555, 0x6a5a5a5a}, /* case-10 */
5004 {0x66555555, 0x6a5a5aaa},
5005 {0x66555555, 0x5a5a5aaa},
5006 {0x66555555, 0x6aaa5aaa},
5007 {0x66555555, 0xaaaa5aaa},
5008 {0x66555555, 0xaaaaaaaa}, /* case-15 */
5009 {0xffff55ff, 0xfafafafa},
5010 {0xffff55ff, 0x6afa5afa},
5011 {0xaaffffaa, 0xfafafafa},
5012 {0xaa5555aa, 0x5a5a5a5a},
5013 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
5014 {0xaa5555aa, 0xaaaaaaaa},
5015 {0xffffffff, 0x5a5a5a5a},
5016 {0xffffffff, 0x5a5a5a5a},
5017 {0xffffffff, 0x55555555},
5018 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
5019 {0x55555555, 0x5a5a5a5a},
5020 {0x55555555, 0xaaaaaaaa},
5021 {0x55555555, 0x6a5a6a5a},
5022 {0x66556655, 0x66556655},
5023 {0x66556aaa, 0x6a5a6aaa}, /*case-30*/
5024 {0xffffffff, 0x5aaa5aaa},
5025 {0x56555555, 0x5a5a5aaa},
5026 {0xdaffdaff, 0xdaffdaff},
5027 {0xddffddff, 0xddffddff},
5032 {0xffffffff, 0xffffffff}, /* case-100 */
5033 {0x55555555, 0x55555555},
5034 {0x66555555, 0x66555555},
5035 {0xaaaaaaaa, 0xaaaaaaaa},
5036 {0x5a5a5a5a, 0x5a5a5a5a},
5037 {0xfafafafa, 0xfafafafa}, /* case-105 */
5038 {0x5afa5afa, 0x5afa5afa},
5039 {0x55555555, 0xfafafafa},
5040 {0x66555555, 0xfafafafa},
5041 {0x66555555, 0x5a5a5a5a},
5042 {0x66555555, 0x6a5a5a5a}, /* case-110 */
5043 {0x66555555, 0xaaaaaaaa},
5044 {0xffff55ff, 0xfafafafa},
5045 {0xffff55ff, 0x5afa5afa},
5046 {0xffff55ff, 0xaaaaaaaa},
5047 {0xffff55ff, 0xffff55ff}, /* case-115 */
5048 {0xaaffffaa, 0x5afa5afa},
5049 {0xaaffffaa, 0xaaaaaaaa},
5050 {0xffffffff, 0xfafafafa},
5051 {0xffffffff, 0x5afa5afa},
5052 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
5053 {0x55ff55ff, 0x5afa5afa},
5054 {0x55ff55ff, 0xaaaaaaaa},
5055 {0x55ff55ff, 0x55ff55ff}
5060 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
5061 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
5062 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
5063 { {0x61, 0x30, 0x03, 0x11, 0x11} },
5064 { {0x61, 0x20, 0x03, 0x11, 0x11} },
5065 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
5066 { {0x61, 0x45, 0x03, 0x11, 0x10} },
5067 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
5068 { {0x61, 0x30, 0x03, 0x11, 0x10} },
5069 { {0x61, 0x20, 0x03, 0x11, 0x10} },
5070 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
5071 { {0x61, 0x08, 0x03, 0x11, 0x14} },
5072 { {0x61, 0x08, 0x03, 0x10, 0x14} },
5073 { {0x51, 0x08, 0x03, 0x10, 0x54} },
5074 { {0x51, 0x08, 0x03, 0x10, 0x55} },
5075 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
5076 { {0x51, 0x45, 0x03, 0x10, 0x50} },
5077 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
5078 { {0x51, 0x30, 0x03, 0x10, 0x50} },
5079 { {0x51, 0x20, 0x03, 0x10, 0x50} },
5080 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
5081 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
5082 { {0x51, 0x0c, 0x03, 0x10, 0x54} },
5083 { {0x55, 0x08, 0x03, 0x10, 0x54} },
5084 { {0x65, 0x10, 0x03, 0x11, 0x10} },
5085 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
5086 { {0x51, 0x08, 0x03, 0x10, 0x50} },
5087 { {0x61, 0x08, 0x03, 0x11, 0x11} }
5092 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */
5093 { {0x61, 0x45, 0x03, 0x11, 0x11} },
5094 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
5095 { {0x61, 0x30, 0x03, 0x11, 0x11} },
5096 { {0x61, 0x20, 0x03, 0x11, 0x11} },
5097 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
5098 { {0x61, 0x45, 0x03, 0x11, 0x10} },
5099 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
5100 { {0x61, 0x30, 0x03, 0x11, 0x10} },
5101 { {0x61, 0x20, 0x03, 0x11, 0x10} },
5102 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
5103 { {0x61, 0x08, 0x03, 0x11, 0x14} },
5104 { {0x61, 0x08, 0x03, 0x10, 0x14} },
5105 { {0x51, 0x08, 0x03, 0x10, 0x54} },
5106 { {0x51, 0x08, 0x03, 0x10, 0x55} },
5107 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
5108 { {0x51, 0x45, 0x03, 0x10, 0x50} },
5109 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
5110 { {0x51, 0x30, 0x03, 0x10, 0x50} },
5111 { {0x51, 0x20, 0x03, 0x10, 0x50} },
5112 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */
5113 { {0x51, 0x08, 0x03, 0x10, 0x50} }
5119 static const struct coex_5g_afh_map afh_5g_8822c[] = { {0, 0, 0} };
5123 {0, 0, false, 7}, /* for normal */
5124 {0, 16, false, 7}, /* for WL-CPT */
5129 {0, 21, true, 4} /* for gamg hid */
5133 {0, 0, false, 7}, /* for normal */
5134 {0, 16, false, 7}, /* for WL-CPT */
5138 {0, 28, true, 5},
5139 {0, 28, true, 5} /* for gamg hid */
5146 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10,
5149 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10,
5152 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10,
5159 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5162 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5165 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5172 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10,
5175 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10,
5178 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10,
5185 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5188 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5191 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5197 0, 1, 2, 3, 4, 4, 5, 6, 7, 8,
5203 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5209 0, 1, 2, 2, 3, 4, 4, 5, 6, 6,
5215 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5221 0, 1, 2, 3, 4, 5, 5, 6, 7, 8,
5227 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5233 0, 1, 2, 3, 3, 4, 5, 6, 6, 7,
5239 0, 1, 2, 3, 4, 5, 5, 6, 7, 8,
5269 {.addr = 0x84c, .mask = MASKBYTE2}, .offset = 0x80
5272 {.addr = 0x84c, .mask = MASKBYTE3}, .offset = 0x80
5289 {0x1860, BIT(3), RTW_REG_DOMAIN_MAC8},
5290 {0x4160, BIT(3), RTW_REG_DOMAIN_MAC8},
5291 {0x1c32, BIT(6), RTW_REG_DOMAIN_MAC8},
5292 {0x1c38, BIT(28), RTW_REG_DOMAIN_MAC32},
5293 {0, 0, RTW_REG_DOMAIN_NL},
5294 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
5295 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
5296 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
5297 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
5298 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
5299 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
5300 {0, 0, RTW_REG_DOMAIN_NL},
5301 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
5302 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
5303 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
5304 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
5305 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_B},
5306 {0, 0, RTW_REG_DOMAIN_NL},
5307 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
5308 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
5309 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
5310 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
5330 .max_power_index = 0x7f,
5334 .dig_min = 0x20,
5340 .sys_func_en = 0xD8,
5349 .rf_base_addr = {0x3c00, 0x4c00},
5350 .rf_sipi_addr = {0x1808, 0x4108},
5379 .coex_para_ver = 0x22020720,
5380 .bt_desired_ver = 0x20,
5402 .bt_afh_span_bw20 = 0x24,
5403 .bt_afh_span_bw40 = 0x36,
5410 .fw_fifo_addr = {0x780, 0x700, 0x780, 0x660, 0x650, 0x680},