290 		rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501);  in rtw8822b_set_channel_rfe_efem()
293 		rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500);  in rtw8822b_set_channel_rfe_efem()
296 		rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005);  in rtw8822b_set_channel_rfe_efem()
320 			rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501);  in rtw8822b_set_channel_rfe_ifem()
323 			rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500);  in rtw8822b_set_channel_rfe_ifem()
326 			rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005);  in rtw8822b_set_channel_rfe_ifem()
329 		rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa5a5);  in rtw8822b_set_channel_rfe_ifem()
609 			rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000);  in rtw8822b_set_channel_bb()
612 			rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x1525);  in rtw8822b_set_channel_bb()
735 		rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x3231);  in rtw8822b_config_trx_mode()
737 		rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x1111);  in rtw8822b_config_trx_mode()
740 		rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x3231);  in rtw8822b_config_trx_mode()
742 		rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x1111);  in rtw8822b_config_trx_mode()
1282 	rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);  in rtw8822b_coex_cfg_rfe_type()
1285 	rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);  in rtw8822b_coex_cfg_rfe_type()
2478 	{0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
2481 	{0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},