Lines Matching +full:0 +full:x261
42 efuse->lna_type_2g = map->lna_type_2g[0]; in rtw8822b_read_efuse()
43 efuse->lna_type_5g = map->lna_type_5g[0]; in rtw8822b_read_efuse()
45 efuse->country_code[0] = map->country_code[0]; in rtw8822b_read_efuse()
48 efuse->regd = map->rf_board_option & 0x7; in rtw8822b_read_efuse()
52 for (i = 0; i < 4; i++) in rtw8822b_read_efuse()
64 return 0; in rtw8822b_read_efuse()
70 rtw_write32_mask(rtwdev, 0x64, BIT(29) | BIT(28), 0x3); in rtw8822b_phy_rfe_init()
71 rtw_write32_mask(rtwdev, 0x4c, BIT(26) | BIT(25), 0x0); in rtw8822b_phy_rfe_init()
72 rtw_write32_mask(rtwdev, 0x40, BIT(2), 0x1); in rtw8822b_phy_rfe_init()
75 rtw_write32_mask(rtwdev, 0x1990, 0x3f, 0x30); in rtw8822b_phy_rfe_init()
76 rtw_write32_mask(rtwdev, 0x1990, (BIT(11) | BIT(10)), 0x3); in rtw8822b_phy_rfe_init()
79 rtw_write32_mask(rtwdev, 0x974, 0x3f, 0x3f); in rtw8822b_phy_rfe_init()
80 rtw_write32_mask(rtwdev, 0x974, (BIT(11) | BIT(10)), 0x3); in rtw8822b_phy_rfe_init()
85 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8,
86 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180,
87 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab,
88 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe
93 u8 i = 0; in rtw8822b_get_swing_index()
96 swing = rtw_read32_mask(rtwdev, 0xc1c, 0xffe00000); in rtw8822b_get_swing_index()
97 for (i = 0; i < RTW_TXSCALE_SIZE; i++) { in rtw8822b_get_swing_index()
119 dm_info->delta_power_index[path] = 0; in rtw8822b_pwrtrack_init()
130 rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF); in rtw8822b_phy_bf_init()
151 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; in rtw8822b_phy_set_param()
152 rtw_write32_mask(rtwdev, 0x24, 0x7e000000, crystal_cap); in rtw8822b_phy_set_param()
153 rtw_write32_mask(rtwdev, 0x28, 0x7e, crystal_cap); in rtw8822b_phy_set_param()
169 #define WLAN_SLOT_TIME 0x09
170 #define WLAN_PIFS_TIME 0x19
171 #define WLAN_SIFS_CCK_CONT_TX 0xA
172 #define WLAN_SIFS_OFDM_CONT_TX 0xE
173 #define WLAN_SIFS_CCK_TRX 0x10
174 #define WLAN_SIFS_OFDM_TRX 0x10
175 #define WLAN_VO_TXOP_LIMIT 0x186 /* unit : 32us */
176 #define WLAN_VI_TXOP_LIMIT 0x3BC /* unit : 32us */
177 #define WLAN_RDG_NAV 0x05
178 #define WLAN_TXOP_NAV 0x1B
179 #define WLAN_CCK_RX_TSF 0x30
180 #define WLAN_OFDM_RX_TSF 0x30
181 #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */
182 #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */
183 #define WLAN_DRV_EARLY_INT 0x04
184 #define WLAN_BCN_DMA_TIME 0x02
186 #define WLAN_RX_FILTER0 0x0FFFFFFF
187 #define WLAN_RX_FILTER2 0xFFFF
188 #define WLAN_RCR_CFG 0xE400220E
192 #define WLAN_AMPDU_MAX_TIME 0x70
193 #define WLAN_RTS_LEN_TH 0xFF
194 #define WLAN_RTS_TX_TIME_TH 0x08
195 #define WLAN_MAX_AGG_PKT_LIMIT 0x20
196 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20
197 #define FAST_EDCA_VO_TH 0x06
198 #define FAST_EDCA_VI_TH 0x06
199 #define FAST_EDCA_BE_TH 0x06
200 #define FAST_EDCA_BK_TH 0x06
201 #define WLAN_BAR_RETRY_LIMIT 0x01
202 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08
204 #define WLAN_TX_FUNC_CFG1 0x30
205 #define WLAN_TX_FUNC_CFG2 0x30
206 #define WLAN_MAC_OPT_NORM_FUNC1 0x98
207 #define WLAN_MAC_OPT_LB_FUNC1 0x80
208 #define WLAN_MAC_OPT_FUNC2 0xb0810041
241 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000); in rtw8822b_mac_init()
268 return 0; in rtw8822b_mac_init()
276 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x705770); in rtw8822b_set_channel_rfe_efem()
277 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57); in rtw8822b_set_channel_rfe_efem()
278 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(4), 0); in rtw8822b_set_channel_rfe_efem()
280 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x177517); in rtw8822b_set_channel_rfe_efem()
281 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75); in rtw8822b_set_channel_rfe_efem()
282 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(5), 0); in rtw8822b_set_channel_rfe_efem()
285 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0); in rtw8822b_set_channel_rfe_efem()
290 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501); in rtw8822b_set_channel_rfe_efem()
293 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500); in rtw8822b_set_channel_rfe_efem()
296 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005); in rtw8822b_set_channel_rfe_efem()
306 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x745774); in rtw8822b_set_channel_rfe_ifem()
307 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57); in rtw8822b_set_channel_rfe_ifem()
310 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x477547); in rtw8822b_set_channel_rfe_ifem()
311 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75); in rtw8822b_set_channel_rfe_ifem()
314 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0); in rtw8822b_set_channel_rfe_ifem()
320 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501); in rtw8822b_set_channel_rfe_ifem()
323 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500); in rtw8822b_set_channel_rfe_ifem()
326 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005); in rtw8822b_set_channel_rfe_ifem()
329 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa5a5); in rtw8822b_set_channel_rfe_ifem()
348 {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/
349 {0x79a0eaaa, 0x79A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/
350 {0x87765541, 0x87746341, 0x87765541, 0x87746341}, /*Reg838*/
354 {0x75B86010, 0x75B76010, 0x75B86010, 0x75B76010}, /*Reg82C*/
355 {0x79A0EAA8, 0x79A0EAAC, 0x79A0EAA8, 0x79a0eaaa}, /*Reg830*/
356 {0x87766451, 0x87766431, 0x87766451, 0x87766431}, /*Reg838*/
360 {0x75da8010, 0x75da8010, 0x75da8010, 0x75da8010}, /*Reg82C*/
361 {0x79a0eaaa, 0x97A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/
362 {0x87765541, 0x86666341, 0x87765561, 0x86666361}, /*Reg838*/
457 reg830 = 0x79a0ea28; in rtw8822b_set_channel_cca()
465 rtw_write32_mask(rtwdev, REG_L1WT, MASKDWORD, 0x9194b2b9); in rtw8822b_set_channel_cca()
468 rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf0, 0x4); in rtw8822b_set_channel_cca()
471 static const u8 low_band[15] = {0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7, 0xff, 0x6,
472 0x5, 0x0, 0x0, 0x7, 0x6, 0x6};
473 static const u8 middle_band[23] = {0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6, 0xff, 0x0,
474 0x0, 0x7, 0x6, 0x6, 0x5, 0x0, 0xff, 0x7, 0x6,
475 0x6, 0x5, 0x0, 0x0, 0x7};
476 static const u8 high_band[15] = {0x5, 0x5, 0x0, 0x7, 0x7, 0x6, 0x5, 0xff, 0x0,
477 0x7, 0x7, 0x6, 0x5, 0x5, 0x0};
482 #define RF18_BAND_2G (0) in rtw8822b_set_channel_rf()
497 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); in rtw8822b_set_channel_rf()
525 rf_reg_be = 0x0; in rtw8822b_set_channel_rf()
537 /* need to set 0xdf[18]=1 before writing RF18 when channel 144 */ in rtw8822b_set_channel_rf()
539 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x1); in rtw8822b_set_channel_rf()
541 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x0); in rtw8822b_set_channel_rf()
543 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18); in rtw8822b_set_channel_rf()
545 rtw_write_rf(rtwdev, RF_PATH_B, 0x18, RFREG_MASK, rf_reg18); in rtw8822b_set_channel_rf()
547 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); in rtw8822b_set_channel_rf()
561 igi = rtw_read32_mask(rtwdev, REG_RXIGI_A, 0x7f); in rtw8822b_toggle_igi()
562 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi - 2); in rtw8822b_toggle_igi()
563 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi); in rtw8822b_toggle_igi()
564 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi - 2); in rtw8822b_toggle_igi()
565 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi); in rtw8822b_toggle_igi()
567 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, 0x0); in rtw8822b_toggle_igi()
576 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x1); in rtw8822b_set_channel_rxdfir()
577 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x0); in rtw8822b_set_channel_rxdfir()
578 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8822b_set_channel_rxdfir()
581 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8822b_set_channel_rxdfir()
582 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); in rtw8822b_set_channel_rxdfir()
583 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8822b_set_channel_rxdfir()
586 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8822b_set_channel_rxdfir()
587 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); in rtw8822b_set_channel_rxdfir()
588 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); in rtw8822b_set_channel_rxdfir()
600 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); in rtw8822b_set_channel_bb()
601 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); in rtw8822b_set_channel_bb()
602 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); in rtw8822b_set_channel_bb()
603 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); in rtw8822b_set_channel_bb()
605 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x0); in rtw8822b_set_channel_bb()
606 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a); in rtw8822b_set_channel_bb()
608 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x00006577); in rtw8822b_set_channel_bb()
609 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000); in rtw8822b_set_channel_bb()
611 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x384f6577); in rtw8822b_set_channel_bb()
612 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x1525); in rtw8822b_set_channel_bb()
615 rtw_write32_mask(rtwdev, REG_RFEINV, 0x300, 0x2); in rtw8822b_set_channel_bb()
617 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); in rtw8822b_set_channel_bb()
618 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); in rtw8822b_set_channel_bb()
619 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); in rtw8822b_set_channel_bb()
620 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 34); in rtw8822b_set_channel_bb()
623 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x1); in rtw8822b_set_channel_bb()
625 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x2); in rtw8822b_set_channel_bb()
627 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x3); in rtw8822b_set_channel_bb()
630 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494); in rtw8822b_set_channel_bb()
632 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453); in rtw8822b_set_channel_bb()
634 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452); in rtw8822b_set_channel_bb()
636 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412); in rtw8822b_set_channel_bb()
638 rtw_write32_mask(rtwdev, 0xcbc, 0x300, 0x1); in rtw8822b_set_channel_bb()
645 val32 &= 0xFFCFFC00; in rtw8822b_set_channel_bb()
649 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8822b_set_channel_bb()
658 val32 &= 0xFF3FF300; in rtw8822b_set_channel_bb()
659 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_40); in rtw8822b_set_channel_bb()
662 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8822b_set_channel_bb()
666 val32 &= 0xFCEFCF00; in rtw8822b_set_channel_bb()
667 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_80); in rtw8822b_set_channel_bb()
670 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8822b_set_channel_bb()
673 rtw_write32_mask(rtwdev, REG_L1PKWT, 0x0000f000, 0x6); in rtw8822b_set_channel_bb()
674 rtw_write32_mask(rtwdev, REG_ADC40, BIT(10), 0x1); in rtw8822b_set_channel_bb()
679 val32 &= 0xEFEEFE00; in rtw8822b_set_channel_bb()
683 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8822b_set_channel_bb()
684 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8822b_set_channel_bb()
688 val32 &= 0xEFFEFF00; in rtw8822b_set_channel_bb()
692 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8822b_set_channel_bb()
693 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8822b_set_channel_bb()
735 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x3231); in rtw8822b_config_trx_mode()
737 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x1111); in rtw8822b_config_trx_mode()
740 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x3231); in rtw8822b_config_trx_mode()
742 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x1111); in rtw8822b_config_trx_mode()
744 rtw_write32_mask(rtwdev, REG_CDDTXP, (BIT(19) | BIT(18)), 0x3); in rtw8822b_config_trx_mode()
745 rtw_write32_mask(rtwdev, REG_TXPSEL, (BIT(29) | BIT(28)), 0x1); in rtw8822b_config_trx_mode()
746 rtw_write32_mask(rtwdev, REG_TXPSEL, BIT(30), 0x1); in rtw8822b_config_trx_mode()
749 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x001); in rtw8822b_config_trx_mode()
750 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x8); in rtw8822b_config_trx_mode()
752 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x002); in rtw8822b_config_trx_mode()
753 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x4); in rtw8822b_config_trx_mode()
757 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x01); in rtw8822b_config_trx_mode()
759 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x43); in rtw8822b_config_trx_mode()
766 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x043); in rtw8822b_config_trx_mode()
767 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0xc); in rtw8822b_config_trx_mode()
771 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(22), 0x0); in rtw8822b_config_trx_mode()
772 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(18), 0x0); in rtw8822b_config_trx_mode()
775 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x0); in rtw8822b_config_trx_mode()
777 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x5); in rtw8822b_config_trx_mode()
783 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x0); in rtw8822b_config_trx_mode()
784 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x0); in rtw8822b_config_trx_mode()
785 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x0); in rtw8822b_config_trx_mode()
787 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x1); in rtw8822b_config_trx_mode()
788 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x1); in rtw8822b_config_trx_mode()
789 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x1); in rtw8822b_config_trx_mode()
792 for (counter = 100; counter > 0; counter--) { in rtw8822b_config_trx_mode()
795 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000); in rtw8822b_config_trx_mode()
796 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001); in rtw8822b_config_trx_mode()
799 rf_reg33 = rtw_read_rf(rtwdev, RF_PATH_A, 0x33, RFREG_MASK); in rtw8822b_config_trx_mode()
801 if (rf_reg33 == 0x00001) in rtw8822b_config_trx_mode()
805 if (WARN(counter <= 0, "write RF mode table fail\n")) in rtw8822b_config_trx_mode()
808 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000); in rtw8822b_config_trx_mode()
809 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001); in rtw8822b_config_trx_mode()
810 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x00034); in rtw8822b_config_trx_mode()
811 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x4080c); in rtw8822b_config_trx_mode()
812 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000); in rtw8822b_config_trx_mode()
813 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000); in rtw8822b_config_trx_mode()
843 u8 evm_dbm = 0; in query_phy_status_page1()
880 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { in query_phy_status_page1()
888 if (rx_evm < 0) { in query_phy_status_page1()
890 evm_dbm = 0; in query_phy_status_page1()
903 page = *phy_status & 0xf; in query_phy_status()
906 case 0: in query_phy_status()
926 memset(pkt_stat, 0, sizeof(*pkt_stat)); in rtw8822b_query_rx_desc()
963 static const u32 offset_txagc[2] = {0x1d00, 0x1d80}; in rtw8822b_set_tx_power_index_by_rate()
968 for (j = 0; j < rtw_rate_size[rs]; j++) { in rtw8822b_set_tx_power_index_by_rate()
971 shift = rate & 0x3; in rtw8822b_set_tx_power_index_by_rate()
973 if (shift == 0x3) { in rtw8822b_set_tx_power_index_by_rate()
974 rate_idx = rate & 0xfc; in rtw8822b_set_tx_power_index_by_rate()
977 phy_pwr_idx = 0; in rtw8822b_set_tx_power_index_by_rate()
987 for (path = 0; path < hal->rf_path_num; path++) { in rtw8822b_set_tx_power_index()
988 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) in rtw8822b_set_tx_power_index()
1011 rtw_dbg(rtwdev, RTW_DBG_PHY, "config RF path, tx=0x%x rx=0x%x\n", in rtw8822b_set_antenna()
1015 rtw_warn(rtwdev, "unsupported tx path 0x%x\n", antenna_tx); in rtw8822b_set_antenna()
1020 rtw_warn(rtwdev, "unsupported rx path 0x%x\n", antenna_rx); in rtw8822b_set_antenna()
1029 return 0; in rtw8822b_set_antenna()
1050 cck_enable = rtw_read32(rtwdev, 0x808) & BIT(28); in rtw8822b_false_alarm_statistics()
1051 cck_fa_cnt = rtw_read16(rtwdev, 0xa5c); in rtw8822b_false_alarm_statistics()
1052 ofdm_fa_cnt = rtw_read16(rtwdev, 0xf48); in rtw8822b_false_alarm_statistics()
1057 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0; in rtw8822b_false_alarm_statistics()
1059 crc32_cnt = rtw_read32(rtwdev, 0xf04); in rtw8822b_false_alarm_statistics()
1060 dm_info->cck_ok_cnt = crc32_cnt & 0xffff; in rtw8822b_false_alarm_statistics()
1061 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16; in rtw8822b_false_alarm_statistics()
1062 crc32_cnt = rtw_read32(rtwdev, 0xf14); in rtw8822b_false_alarm_statistics()
1063 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff; in rtw8822b_false_alarm_statistics()
1064 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16; in rtw8822b_false_alarm_statistics()
1065 crc32_cnt = rtw_read32(rtwdev, 0xf10); in rtw8822b_false_alarm_statistics()
1066 dm_info->ht_ok_cnt = crc32_cnt & 0xffff; in rtw8822b_false_alarm_statistics()
1067 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; in rtw8822b_false_alarm_statistics()
1068 crc32_cnt = rtw_read32(rtwdev, 0xf0c); in rtw8822b_false_alarm_statistics()
1069 dm_info->vht_ok_cnt = crc32_cnt & 0xffff; in rtw8822b_false_alarm_statistics()
1070 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; in rtw8822b_false_alarm_statistics()
1072 cca32_cnt = rtw_read32(rtwdev, 0xf08); in rtw8822b_false_alarm_statistics()
1073 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16); in rtw8822b_false_alarm_statistics()
1076 cca32_cnt = rtw_read32(rtwdev, 0xfcc); in rtw8822b_false_alarm_statistics()
1077 dm_info->cck_cca_cnt = cca32_cnt & 0xffff; in rtw8822b_false_alarm_statistics()
1081 rtw_write32_set(rtwdev, 0x9a4, BIT(17)); in rtw8822b_false_alarm_statistics()
1082 rtw_write32_clr(rtwdev, 0x9a4, BIT(17)); in rtw8822b_false_alarm_statistics()
1083 rtw_write32_clr(rtwdev, 0xa2c, BIT(15)); in rtw8822b_false_alarm_statistics()
1084 rtw_write32_set(rtwdev, 0xa2c, BIT(15)); in rtw8822b_false_alarm_statistics()
1085 rtw_write32_set(rtwdev, 0xb58, BIT(0)); in rtw8822b_false_alarm_statistics()
1086 rtw_write32_clr(rtwdev, 0xb58, BIT(0)); in rtw8822b_false_alarm_statistics()
1092 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0}; in rtw8822b_do_iqk()
1099 for (counter = 0; counter < 300; counter++) { in rtw8822b_do_iqk()
1101 if (rf_reg == 0xabcde) in rtw8822b_do_iqk()
1105 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0); in rtw8822b_do_iqk()
1108 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0)); in rtw8822b_do_iqk()
1110 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n", in rtw8822b_do_iqk()
1125 /* 0x790[5:0]=0x5 */ in rtw8822b_coex_cfg_init()
1126 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); in rtw8822b_coex_cfg_init()
1129 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); in rtw8822b_coex_cfg_init()
1150 u8 regval = 0; in rtw8822b_coex_cfg_ant_switch()
1166 /* 0x4c[23] = 0 */ in rtw8822b_coex_cfg_ant_switch()
1167 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); in rtw8822b_coex_cfg_ant_switch()
1168 /* 0x4c[24] = 1 */ in rtw8822b_coex_cfg_ant_switch()
1169 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); in rtw8822b_coex_cfg_ant_switch()
1171 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x77); in rtw8822b_coex_cfg_ant_switch()
1174 if (coex_rfe->rfe_module_type != 0x4 && in rtw8822b_coex_cfg_ant_switch()
1175 coex_rfe->rfe_module_type != 0x2) in rtw8822b_coex_cfg_ant_switch()
1176 regval = 0x3; in rtw8822b_coex_cfg_ant_switch()
1178 regval = (!polarity_inverse ? 0x2 : 0x1); in rtw8822b_coex_cfg_ant_switch()
1180 regval = (!polarity_inverse ? 0x2 : 0x1); in rtw8822b_coex_cfg_ant_switch()
1182 regval = (!polarity_inverse ? 0x1 : 0x2); in rtw8822b_coex_cfg_ant_switch()
1188 /* 0x4c[23] = 0 */ in rtw8822b_coex_cfg_ant_switch()
1189 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); in rtw8822b_coex_cfg_ant_switch()
1190 /* 0x4c[24] = 1 */ in rtw8822b_coex_cfg_ant_switch()
1191 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); in rtw8822b_coex_cfg_ant_switch()
1193 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x66); in rtw8822b_coex_cfg_ant_switch()
1195 regval = (!polarity_inverse ? 0x2 : 0x1); in rtw8822b_coex_cfg_ant_switch()
1199 /* 0x4c[23] = 0 */ in rtw8822b_coex_cfg_ant_switch()
1200 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); in rtw8822b_coex_cfg_ant_switch()
1201 /* 0x4c[24] = 1 */ in rtw8822b_coex_cfg_ant_switch()
1202 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); in rtw8822b_coex_cfg_ant_switch()
1203 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x88); in rtw8822b_coex_cfg_ant_switch()
1206 /* 0x4c[23] = 1 */ in rtw8822b_coex_cfg_ant_switch()
1207 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x1); in rtw8822b_coex_cfg_ant_switch()
1209 regval = (!polarity_inverse ? 0x0 : 0x1); in rtw8822b_coex_cfg_ant_switch()
1213 /* 0x4c[23] = 0 */ in rtw8822b_coex_cfg_ant_switch()
1214 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); in rtw8822b_coex_cfg_ant_switch()
1215 /* 0x4c[24] = 1 */ in rtw8822b_coex_cfg_ant_switch()
1216 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); in rtw8822b_coex_cfg_ant_switch()
1219 /* 0x4c[23] = 0 */ in rtw8822b_coex_cfg_ant_switch()
1220 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); in rtw8822b_coex_cfg_ant_switch()
1221 /* 0x4c[24] = 0 */ in rtw8822b_coex_cfg_ant_switch()
1222 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x0); in rtw8822b_coex_cfg_ant_switch()
1233 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0); in rtw8822b_coex_cfg_gnt_debug()
1234 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0); in rtw8822b_coex_cfg_gnt_debug()
1235 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0); in rtw8822b_coex_cfg_gnt_debug()
1236 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0); in rtw8822b_coex_cfg_gnt_debug()
1237 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0); in rtw8822b_coex_cfg_gnt_debug()
1248 coex_rfe->ant_switch_polarity = 0; in rtw8822b_coex_cfg_rfe_type()
1250 if (coex_rfe->rfe_module_type == 0x12 || in rtw8822b_coex_cfg_rfe_type()
1251 coex_rfe->rfe_module_type == 0x15 || in rtw8822b_coex_cfg_rfe_type()
1252 coex_rfe->rfe_module_type == 0x16) in rtw8822b_coex_cfg_rfe_type()
1274 rtw_write8(rtwdev, REG_RFE_CTRL_E, 0xff); in rtw8822b_coex_cfg_rfe_type()
1275 rtw_write8_mask(rtwdev, REG_RFESEL_CTRL + 1, 0x3, 0x0); in rtw8822b_coex_cfg_rfe_type()
1276 rtw_write8_mask(rtwdev, REG_RFE_INV16, BIT_RFE_BUF_EN, 0x0); in rtw8822b_coex_cfg_rfe_type()
1279 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0); in rtw8822b_coex_cfg_rfe_type()
1282 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff); in rtw8822b_coex_cfg_rfe_type()
1285 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff); in rtw8822b_coex_cfg_rfe_type()
1292 static const u16 reg_addr[] = {0xc58, 0xe58}; in rtw8822b_coex_cfg_wl_tx_power()
1293 static const u8 wl_tx_power[] = {0xd8, 0xd4, 0xd0, 0xcc, 0xc8}; in rtw8822b_coex_cfg_wl_tx_power()
1306 for (i = 0; i < ARRAY_SIZE(reg_addr); i++) in rtw8822b_coex_cfg_wl_tx_power()
1307 rtw_write8_mask(rtwdev, reg_addr[i], 0xff, pwr); in rtw8822b_coex_cfg_wl_tx_power()
1316 0xff000003, 0xbd120003, 0xbe100003, 0xbf080003, 0xbf060003, in rtw8822b_coex_cfg_wl_rx_gain()
1317 0xbf050003, 0xbc140003, 0xbb160003, 0xba180003, 0xb91a0003, in rtw8822b_coex_cfg_wl_rx_gain()
1318 0xb81c0003, 0xb71e0003, 0xb4200003, 0xb5220003, 0xb4240003, in rtw8822b_coex_cfg_wl_rx_gain()
1319 0xb3260003, 0xb2280003, 0xb12a0003, 0xb02c0003, 0xaf2e0003, in rtw8822b_coex_cfg_wl_rx_gain()
1320 0xae300003, 0xad320003, 0xac340003, 0xab360003, 0x8d380003, in rtw8822b_coex_cfg_wl_rx_gain()
1321 0x8c3a0003, 0x8b3c0003, 0x8a3e0003, 0x6e400003, 0x6d420003, in rtw8822b_coex_cfg_wl_rx_gain()
1322 0x6c440003, 0x6b460003, 0x6a480003, 0x694a0003, 0x684c0003, in rtw8822b_coex_cfg_wl_rx_gain()
1323 0x674e0003, 0x66500003, 0x65520003, 0x64540003, 0x64560003, in rtw8822b_coex_cfg_wl_rx_gain()
1324 0x007e0403 in rtw8822b_coex_cfg_wl_rx_gain()
1329 0xff000003, 0xf4120003, 0xf5100003, 0xf60e0003, 0xf70c0003, in rtw8822b_coex_cfg_wl_rx_gain()
1330 0xf80a0003, 0xf3140003, 0xf2160003, 0xf1180003, 0xf01a0003, in rtw8822b_coex_cfg_wl_rx_gain()
1331 0xef1c0003, 0xee1e0003, 0xed200003, 0xec220003, 0xeb240003, in rtw8822b_coex_cfg_wl_rx_gain()
1332 0xea260003, 0xe9280003, 0xe82a0003, 0xe72c0003, 0xe62e0003, in rtw8822b_coex_cfg_wl_rx_gain()
1333 0xe5300003, 0xc8320003, 0xc7340003, 0xc6360003, 0xc5380003, in rtw8822b_coex_cfg_wl_rx_gain()
1334 0xc43a0003, 0xc33c0003, 0xc23e0003, 0xc1400003, 0xc0420003, in rtw8822b_coex_cfg_wl_rx_gain()
1335 0xa5440003, 0xa4460003, 0xa3480003, 0xa24a0003, 0xa14c0003, in rtw8822b_coex_cfg_wl_rx_gain()
1336 0x834e0003, 0x82500003, 0x81520003, 0x80540003, 0x65560003, in rtw8822b_coex_cfg_wl_rx_gain()
1337 0x007e0403 in rtw8822b_coex_cfg_wl_rx_gain()
1348 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_on); i++) in rtw8822b_coex_cfg_wl_rx_gain()
1352 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x1); in rtw8822b_coex_cfg_wl_rx_gain()
1353 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x3f); in rtw8822b_coex_cfg_wl_rx_gain()
1354 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x1); in rtw8822b_coex_cfg_wl_rx_gain()
1355 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x3f); in rtw8822b_coex_cfg_wl_rx_gain()
1358 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_off); i++) in rtw8822b_coex_cfg_wl_rx_gain()
1359 rtw_write32(rtwdev, 0x81c, wl_rx_low_gain_off[i]); in rtw8822b_coex_cfg_wl_rx_gain()
1362 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x4); in rtw8822b_coex_cfg_wl_rx_gain()
1363 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x0); in rtw8822b_coex_cfg_wl_rx_gain()
1364 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x4); in rtw8822b_coex_cfg_wl_rx_gain()
1365 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x0); in rtw8822b_coex_cfg_wl_rx_gain()
1376 u8 swing_lower_bound = 0; in rtw8822b_txagc_swing_offset()
1377 u8 max_tx_pwr_idx_offset = 0xf; in rtw8822b_txagc_swing_offset()
1378 s8 agc_index = 0; in rtw8822b_txagc_swing_offset()
1383 if (delta_pwr_idx >= 0) { in rtw8822b_txagc_swing_offset()
1401 agc_index = 0; in rtw8822b_txagc_swing_offset()
1420 reg1 = 0xc94; in rtw8822b_pwrtrack_set_pwr()
1421 reg2 = 0xc1c; in rtw8822b_pwrtrack_set_pwr()
1423 reg1 = 0xe94; in rtw8822b_pwrtrack_set_pwr()
1424 reg2 = 0xe1c; in rtw8822b_pwrtrack_set_pwr()
1487 if (rtwdev->efuse.thermal_meter[RF_PATH_A] == 0xff) in rtw8822b_phy_pwrtrack()
1490 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); in rtw8822b_phy_pwrtrack()
1500 for (path = 0; path < rtwdev->hal.rf_path_num; path++) in rtw8822b_phy_pwrtrack()
1513 if (efuse->power_track_type != 0) in rtw8822b_pwr_track()
1518 GENMASK(17, 16), 0x03); in rtw8822b_pwr_track()
1567 rtw_write32_mask(rtwdev, REG_EDCCA_POW_MA, BIT_MA_LEVEL, 0); in rtw8822b_adaptivity_init()
1579 igi = dm_info->igi_history[0]; in rtw8822b_adaptivity()
1592 {0x0086,
1596 RTW_PWR_CMD_WRITE, BIT(0), 0},
1597 {0x0086,
1602 {0x004A,
1606 RTW_PWR_CMD_WRITE, BIT(0), 0},
1607 {0x0005,
1611 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1612 {0x0300,
1616 RTW_PWR_CMD_WRITE, 0xFF, 0},
1617 {0x0301,
1621 RTW_PWR_CMD_WRITE, 0xFF, 0},
1622 {0xFFFF,
1625 0,
1626 RTW_PWR_CMD_END, 0, 0},
1630 {0x0012,
1634 RTW_PWR_CMD_WRITE, BIT(1), 0},
1635 {0x0012,
1639 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1640 {0x0020,
1644 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1645 {0x0001,
1650 {0x0000,
1654 RTW_PWR_CMD_WRITE, BIT(5), 0},
1655 {0x0005,
1659 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1660 {0x0075,
1664 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1665 {0x0006,
1670 {0x0075,
1674 RTW_PWR_CMD_WRITE, BIT(0), 0},
1675 {0xFF1A,
1679 RTW_PWR_CMD_WRITE, 0xFF, 0},
1680 {0x0006,
1684 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1685 {0x0005,
1689 RTW_PWR_CMD_WRITE, BIT(7), 0},
1690 {0x0005,
1694 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1695 {0x10C3,
1699 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1700 {0x0005,
1704 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1705 {0x0005,
1709 RTW_PWR_CMD_POLLING, BIT(0), 0},
1710 {0x0020,
1715 {0x10A8,
1719 RTW_PWR_CMD_WRITE, 0xFF, 0},
1720 {0x10A9,
1724 RTW_PWR_CMD_WRITE, 0xFF, 0xef},
1725 {0x10AA,
1729 RTW_PWR_CMD_WRITE, 0xFF, 0x0c},
1730 {0x0068,
1735 {0x0029,
1739 RTW_PWR_CMD_WRITE, 0xFF, 0xF9},
1740 {0x0024,
1744 RTW_PWR_CMD_WRITE, BIT(2), 0},
1745 {0x0074,
1750 {0x00AF,
1755 {0xFFFF,
1758 0,
1759 RTW_PWR_CMD_END, 0, 0},
1763 {0x0003,
1767 RTW_PWR_CMD_WRITE, BIT(2), 0},
1768 {0x0093,
1772 RTW_PWR_CMD_WRITE, BIT(3), 0},
1773 {0x001F,
1777 RTW_PWR_CMD_WRITE, 0xFF, 0},
1778 {0x00EF,
1782 RTW_PWR_CMD_WRITE, 0xFF, 0},
1783 {0xFF1A,
1787 RTW_PWR_CMD_WRITE, 0xFF, 0x30},
1788 {0x0049,
1792 RTW_PWR_CMD_WRITE, BIT(1), 0},
1793 {0x0006,
1797 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1798 {0x0002,
1802 RTW_PWR_CMD_WRITE, BIT(1), 0},
1803 {0x10C3,
1807 RTW_PWR_CMD_WRITE, BIT(0), 0},
1808 {0x0005,
1813 {0x0005,
1817 RTW_PWR_CMD_POLLING, BIT(1), 0},
1818 {0x0020,
1822 RTW_PWR_CMD_WRITE, BIT(3), 0},
1823 {0x0000,
1828 {0xFFFF,
1831 0,
1832 RTW_PWR_CMD_END, 0, 0},
1836 {0x0005,
1841 {0x0007,
1845 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
1846 {0x0067,
1850 RTW_PWR_CMD_WRITE, BIT(5), 0},
1851 {0x0005,
1856 {0x004A,
1860 RTW_PWR_CMD_WRITE, BIT(0), 0},
1861 {0x0067,
1865 RTW_PWR_CMD_WRITE, BIT(5), 0},
1866 {0x0067,
1870 RTW_PWR_CMD_WRITE, BIT(4), 0},
1871 {0x004F,
1875 RTW_PWR_CMD_WRITE, BIT(0), 0},
1876 {0x0067,
1880 RTW_PWR_CMD_WRITE, BIT(1), 0},
1881 {0x0046,
1886 {0x0067,
1890 RTW_PWR_CMD_WRITE, BIT(2), 0},
1891 {0x0046,
1896 {0x0062,
1901 {0x0081,
1905 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1906 {0x0005,
1911 {0x0086,
1915 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1916 {0x0086,
1920 RTW_PWR_CMD_POLLING, BIT(1), 0},
1921 {0x0090,
1925 RTW_PWR_CMD_WRITE, BIT(1), 0},
1926 {0x0044,
1930 RTW_PWR_CMD_WRITE, 0xFF, 0},
1931 {0x0040,
1935 RTW_PWR_CMD_WRITE, 0xFF, 0x90},
1936 {0x0041,
1940 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1941 {0x0042,
1945 RTW_PWR_CMD_WRITE, 0xFF, 0x04},
1946 {0xFFFF,
1949 0,
1950 RTW_PWR_CMD_END, 0, 0},
1966 {0xFFFF, 0x00,
1973 {0x0001, 0xA841,
1977 {0xFFFF, 0x0000,
1984 {0x0001, 0xA841,
1988 {0x0002, 0x60C6,
1992 {0x0008, 0x3596,
1996 {0x0009, 0x321C,
2000 {0x000A, 0x9623,
2004 {0x0020, 0x94FF,
2008 {0x0021, 0xFFCF,
2012 {0x0026, 0xC006,
2016 {0x0029, 0xFF0E,
2020 {0x002A, 0x1840,
2024 {0xFFFF, 0x0000,
2031 {0x0001, 0xA841,
2035 {0x0002, 0x60C6,
2039 {0x0008, 0x3597,
2043 {0x0009, 0x321C,
2047 {0x000A, 0x9623,
2051 {0x0020, 0x94FF,
2055 {0x0021, 0xFFCF,
2059 {0x0026, 0xC006,
2063 {0x0029, 0xFF0E,
2067 {0x002A, 0x3040,
2071 {0xFFFF, 0x0000,
2090 [3] = RTW_DEF_RFE(8822b, 3, 0),
2095 [0] = { .addr = 0xc50, .mask = 0x7f },
2096 [1] = { .addr = 0xe50, .mask = 0x7f },
2108 {64, 64, 0, 0, 1},
2109 {64, 64, 64, 0, 1},
2178 {0xffffffff, 0xffffffff}, /* case-0 */
2179 {0x55555555, 0x55555555},
2180 {0x66555555, 0x66555555},
2181 {0xaaaaaaaa, 0xaaaaaaaa},
2182 {0x5a5a5a5a, 0x5a5a5a5a},
2183 {0xfafafafa, 0xfafafafa}, /* case-5 */
2184 {0x6a5a5555, 0xaaaaaaaa},
2185 {0x6a5a56aa, 0x6a5a56aa},
2186 {0x6a5a5a5a, 0x6a5a5a5a},
2187 {0x66555555, 0x5a5a5a5a},
2188 {0x66555555, 0x6a5a5a5a}, /* case-10 */
2189 {0x66555555, 0xfafafafa},
2190 {0x66555555, 0x5a5a5aaa},
2191 {0x66555555, 0x6aaa5aaa},
2192 {0x66555555, 0xaaaa5aaa},
2193 {0x66555555, 0xaaaaaaaa}, /* case-15 */
2194 {0xffff55ff, 0xfafafafa},
2195 {0xffff55ff, 0x6afa5afa},
2196 {0xaaffffaa, 0xfafafafa},
2197 {0xaa5555aa, 0x5a5a5a5a},
2198 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
2199 {0xaa5555aa, 0xaaaaaaaa},
2200 {0xffffffff, 0x5a5a5a5a},
2201 {0xffffffff, 0x5a5a5a5a},
2202 {0xffffffff, 0x55555555},
2203 {0xffffffff, 0x6a5a5aaa}, /* case-25 */
2204 {0x55555555, 0x5a5a5a5a},
2205 {0x55555555, 0xaaaaaaaa},
2206 {0x55555555, 0x6a5a6a5a},
2207 {0x66556655, 0x66556655},
2208 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
2209 {0xffffffff, 0x5aaa5aaa},
2210 {0x56555555, 0x5a5a5aaa},
2215 {0xffffffff, 0xffffffff}, /* case-100 */
2216 {0x55555555, 0x55555555},
2217 {0x66555555, 0x66555555},
2218 {0xaaaaaaaa, 0xaaaaaaaa},
2219 {0x5a5a5a5a, 0x5a5a5a5a},
2220 {0xfafafafa, 0xfafafafa}, /* case-105 */
2221 {0x5afa5afa, 0x5afa5afa},
2222 {0x55555555, 0xfafafafa},
2223 {0x66555555, 0xfafafafa},
2224 {0x66555555, 0x5a5a5a5a},
2225 {0x66555555, 0x6a5a5a5a}, /* case-110 */
2226 {0x66555555, 0xaaaaaaaa},
2227 {0xffff55ff, 0xfafafafa},
2228 {0xffff55ff, 0x5afa5afa},
2229 {0xffff55ff, 0xaaaaaaaa},
2230 {0xffff55ff, 0xffff55ff}, /* case-115 */
2231 {0xaaffffaa, 0x5afa5afa},
2232 {0xaaffffaa, 0xaaaaaaaa},
2233 {0xffffffff, 0xfafafafa},
2234 {0xffffffff, 0x5afa5afa},
2235 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
2236 {0x55ff55ff, 0x5afa5afa},
2237 {0x55ff55ff, 0xaaaaaaaa},
2238 {0x55ff55ff, 0x55ff55ff}
2243 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
2244 { {0x61, 0x45, 0x03, 0x11, 0x11} },
2245 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
2246 { {0x61, 0x30, 0x03, 0x11, 0x11} },
2247 { {0x61, 0x20, 0x03, 0x11, 0x11} },
2248 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
2249 { {0x61, 0x45, 0x03, 0x11, 0x10} },
2250 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
2251 { {0x61, 0x30, 0x03, 0x11, 0x10} },
2252 { {0x61, 0x20, 0x03, 0x11, 0x10} },
2253 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
2254 { {0x61, 0x08, 0x03, 0x11, 0x14} },
2255 { {0x61, 0x08, 0x03, 0x10, 0x14} },
2256 { {0x51, 0x08, 0x03, 0x10, 0x54} },
2257 { {0x51, 0x08, 0x03, 0x10, 0x55} },
2258 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
2259 { {0x51, 0x45, 0x03, 0x10, 0x50} },
2260 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
2261 { {0x51, 0x30, 0x03, 0x10, 0x50} },
2262 { {0x51, 0x20, 0x03, 0x10, 0x50} },
2263 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
2264 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
2265 { {0x51, 0x0c, 0x03, 0x10, 0x54} },
2266 { {0x55, 0x08, 0x03, 0x10, 0x54} },
2267 { {0x65, 0x10, 0x03, 0x11, 0x10} },
2268 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
2269 { {0x51, 0x08, 0x03, 0x10, 0x50} },
2270 { {0x61, 0x08, 0x03, 0x11, 0x11} }
2275 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */
2276 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-101 */
2277 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
2278 { {0x61, 0x30, 0x03, 0x11, 0x11} },
2279 { {0x61, 0x20, 0x03, 0x11, 0x11} },
2280 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
2281 { {0x61, 0x45, 0x03, 0x11, 0x10} },
2282 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
2283 { {0x61, 0x30, 0x03, 0x11, 0x10} },
2284 { {0x61, 0x20, 0x03, 0x11, 0x10} },
2285 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
2286 { {0x61, 0x08, 0x03, 0x11, 0x14} },
2287 { {0x61, 0x08, 0x03, 0x10, 0x14} },
2288 { {0x51, 0x08, 0x03, 0x10, 0x54} },
2289 { {0x51, 0x08, 0x03, 0x10, 0x55} },
2290 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
2291 { {0x51, 0x45, 0x03, 0x10, 0x50} },
2292 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
2293 { {0x51, 0x30, 0x03, 0x10, 0x50} },
2294 { {0x51, 0x20, 0x03, 0x10, 0x50} },
2295 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */
2296 { {0x51, 0x08, 0x03, 0x10, 0x50} }
2305 {0, 0, false, 7}, /* for normal */
2306 {0, 16, false, 7}, /* for WL-CPT */
2307 {4, 0, true, 1},
2314 {0, 0, false, 7}, /* for normal */
2315 {0, 16, false, 7}, /* for WL-CPT */
2316 {4, 0, true, 1},
2347 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2350 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2353 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2360 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2363 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2366 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2373 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2376 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2379 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2386 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2389 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2392 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2398 0, 1, 1, 1, 2, 2, 3, 3, 3, 4,
2404 0, 0, 1, 1, 2, 2, 3, 3, 4, 4,
2410 0, 1, 1, 1, 2, 2, 3, 3, 3, 4,
2416 0, 1, 1, 2, 2, 3, 3, 4, 4, 5,
2422 0, 1, 1, 1, 2, 2, 3, 3, 3, 4,
2428 0, 0, 1, 1, 2, 2, 3, 3, 4, 4,
2434 0, 1, 1, 1, 2, 2, 3, 3, 3, 4,
2440 0, 1, 1, 2, 2, 3, 3, 4, 4, 5,
2469 {0xcb0, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2470 {0xcb4, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2471 {0xcba, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2472 {0xcbd, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2473 {0xc58, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2474 {0xcbd, BIT(0), RTW_REG_DOMAIN_MAC8},
2475 {0, 0, RTW_REG_DOMAIN_NL},
2476 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2477 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2478 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
2479 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2480 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
2481 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
2482 {0, 0, RTW_REG_DOMAIN_NL},
2483 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
2484 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
2485 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
2486 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
2487 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_B},
2488 {0, 0, RTW_REG_DOMAIN_NL},
2489 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2490 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2491 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
2492 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2496 [EDCCA_TH_L2H_IDX] = {{.addr = 0x8a4, .mask = MASKBYTE0}, .offset = 0},
2497 [EDCCA_TH_H2L_IDX] = {{.addr = 0x8a4, .mask = MASKBYTE1}, .offset = 0},
2517 .max_power_index = 0x3f,
2518 .csi_buf_pg_num = 0,
2521 .dig_min = 0x1c,
2525 .sys_func_en = 0xDC,
2534 .rf_base_addr = {0x2800, 0x2c00},
2535 .rf_sipi_addr = {0xc90, 0xe90},
2554 .coex_para_ver = 0x20070206,
2555 .bt_desired_ver = 0x6,
2577 .bt_afh_span_bw20 = 0x24,
2578 .bt_afh_span_bw40 = 0x36,
2585 .fw_fifo_addr = {0x780, 0x700, 0x780, 0x660, 0x650, 0x680},