Lines Matching +full:0 +full:xf08
13 u8 mac_addr[ETH_ALEN]; /* 0xd0 */
21 u8 ltr_cap; /* 0xe3 */
26 u8 res0:2; /* 0xf4 */
50 u8 res0[0x0e];
55 u8 channel_plan; /* 0xb8 */
59 u8 pa_type; /* 0xbc */
60 u8 lna_type_2g[2]; /* 0xbd */
70 u8 rf_antenna_option; /* 0xc9 */
82 /* 0xC00-0xCFF and 0xE00-0xEFF have the same layout */ in _rtw_write32s_mask()
84 rtw_write32_mask(rtwdev, addr + 0x200, mask, data); in _rtw_write32s_mask()
91 BUILD_BUG_ON((addr) < 0xC00 || (addr) >= 0xD00); \
94 } while (0)
97 #define WLAN_SLOT_TIME 0x09
98 #define WLAN_PIFS_TIME 0x19
99 #define WLAN_SIFS_CCK_CONT_TX 0xA
100 #define WLAN_SIFS_OFDM_CONT_TX 0xE
101 #define WLAN_SIFS_CCK_TRX 0x10
102 #define WLAN_SIFS_OFDM_TRX 0x10
103 #define WLAN_VO_TXOP_LIMIT 0x186
104 #define WLAN_VI_TXOP_LIMIT 0x3BC
105 #define WLAN_RDG_NAV 0x05
106 #define WLAN_TXOP_NAV 0x1B
107 #define WLAN_CCK_RX_TSF 0x30
108 #define WLAN_OFDM_RX_TSF 0x30
109 #define WLAN_TBTT_PROHIBIT 0x04
110 #define WLAN_TBTT_HOLD_TIME 0x064
111 #define WLAN_DRV_EARLY_INT 0x04
112 #define WLAN_BCN_DMA_TIME 0x02
114 #define WLAN_RX_FILTER0 0x0FFFFFFF
115 #define WLAN_RX_FILTER2 0xFFFF
116 #define WLAN_RCR_CFG 0xE400220E
120 #define WLAN_AMPDU_MAX_TIME 0x70
121 #define WLAN_RTS_LEN_TH 0xFF
122 #define WLAN_RTS_TX_TIME_TH 0x08
123 #define WLAN_MAX_AGG_PKT_LIMIT 0x20
124 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20
125 #define FAST_EDCA_VO_TH 0x06
126 #define FAST_EDCA_VI_TH 0x06
127 #define FAST_EDCA_BE_TH 0x06
128 #define FAST_EDCA_BK_TH 0x06
129 #define WLAN_BAR_RETRY_LIMIT 0x01
130 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08
132 #define WLAN_TX_FUNC_CFG1 0x30
133 #define WLAN_TX_FUNC_CFG2 0x30
134 #define WLAN_MAC_OPT_NORM_FUNC1 0x98
135 #define WLAN_MAC_OPT_LB_FUNC1 0x80
136 #define WLAN_MAC_OPT_FUNC2 0xb0810041
148 #define WLAN_PRE_TXCNT_TIME_TH 0x1E4
152 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
154 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(12, 8))
156 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(15, 13))
158 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), BIT(23))
160 #define BIT_LNA_L_MASK GENMASK(2, 0)
164 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
166 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
168 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
170 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
172 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
174 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
176 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8))
178 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
180 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8))
182 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
184 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8))
186 #define REG_SYS_CTRL 0x000
188 #define REG_INIRTS_RATE_SEL 0x0480
189 #define REG_HTSTFWT 0x800
190 #define REG_RXPSEL 0x808
192 #define REG_TXPSEL 0x80c
193 #define REG_RXCCAMSK 0x814
194 #define REG_CCASEL 0x82c
195 #define REG_PDMFTH 0x830
196 #define REG_CCA2ND 0x838
197 #define REG_L1WT 0x83c
198 #define REG_L1PKWT 0x840
199 #define REG_MRC 0x850
200 #define REG_CLKTRK 0x860
201 #define REG_ADCCLK 0x8ac
202 #define REG_ADC160 0x8c4
203 #define REG_ADC40 0x8c8
204 #define REG_CHFIR 0x8f0
205 #define REG_CDDTXP 0x93c
206 #define REG_TXPSEL1 0x940
207 #define REG_ACBB0 0x948
208 #define REG_ACBBRXFIR 0x94c
209 #define REG_ACGG2TBL 0x958
210 #define REG_FAS 0x9a4
211 #define REG_RXSB 0xa00
212 #define REG_ADCINI 0xa04
213 #define REG_PWRTH 0xa08
214 #define REG_TXSF2 0xa24
215 #define REG_TXSF6 0xa28
216 #define REG_FA_CCK 0xa5c
217 #define REG_RXDESC 0xa2c
218 #define REG_ENTXCCK 0xa80
219 #define BTG_LNA 0xfc84
220 #define WLG_LNA 0x7532
221 #define REG_ENRXCCA 0xa84
222 #define BTG_CCA 0x0e
223 #define WLG_CCA 0x12
224 #define REG_PWRTH2 0xaa8
225 #define REG_CSRATIO 0xaaa
226 #define REG_TXFILTER 0xaac
227 #define REG_CNTRST 0xb58
228 #define REG_AGCTR_A 0xc08
229 #define REG_TXSCALE_A 0xc1c
230 #define REG_TXDFIR 0xc20
231 #define REG_RXIGI_A 0xc50
232 #define REG_TXAGCIDX 0xc94
233 #define REG_TRSW 0xca0
234 #define REG_RFESEL0 0xcb0
235 #define REG_RFESEL8 0xcb4
236 #define REG_RFECTL 0xcb8
242 #define REG_RFEINV 0xcbc
243 #define REG_AGCTR_B 0xe08
244 #define REG_RXIGI_B 0xe50
245 #define REG_CRC_CCK 0xf04
246 #define REG_CRC_OFDM 0xf14
247 #define REG_CRC_HT 0xf10
248 #define REG_CRC_VHT 0xf0c
249 #define REG_CCA_OFDM 0xf08
250 #define REG_FA_OFDM 0xf48
251 #define REG_CCA_CCK 0xfcc
252 #define REG_DMEM_CTRL 0x1080
254 #define REG_ANTWT 0x1904
255 #define REG_IQKFAILMSK 0x1bf0
258 #define BT_CNT_ENABLE 0x1
260 #define BCN_PRI_EN 0x1
261 #define PTA_CTRL_PIN 0x66
262 #define DPDT_CTRL_PIN 0x77
263 #define ANTDIC_CTRL_PIN 0x88
264 #define REG_CTRL_TYPE 0x67
270 #define RF18_BAND_2G (0)