Lines Matching +full:12 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
19 static const s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -40, -46, -52};
20 static const s8 lna_gain_table_1[16] = {10, 6, 2, -2, -6, -10, -14, -17,
21 -20, -24, -28, -31, -34, -37, -40, -44};
26 ether_addr_copy(efuse->addr, map->e.mac_addr); in rtw8821ce_efuse_parsing()
38 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8821c_read_efuse()
44 efuse->rfe_option = map->rfe_option; in rtw8821c_read_efuse()
45 efuse->rf_board_option = map->rf_board_option; in rtw8821c_read_efuse()
46 efuse->crystal_cap = map->xtal_k; in rtw8821c_read_efuse()
47 efuse->pa_type_2g = map->pa_type; in rtw8821c_read_efuse()
48 efuse->pa_type_5g = map->pa_type; in rtw8821c_read_efuse()
49 efuse->lna_type_2g = map->lna_type_2g[0]; in rtw8821c_read_efuse()
50 efuse->lna_type_5g = map->lna_type_5g[0]; in rtw8821c_read_efuse()
51 efuse->channel_plan = map->channel_plan; in rtw8821c_read_efuse()
52 efuse->country_code[0] = map->country_code[0]; in rtw8821c_read_efuse()
53 efuse->country_code[1] = map->country_code[1]; in rtw8821c_read_efuse()
54 efuse->bt_setting = map->rf_bt_setting; in rtw8821c_read_efuse()
55 efuse->regd = map->rf_board_option & 0x7; in rtw8821c_read_efuse()
56 efuse->thermal_meter[0] = map->thermal_meter; in rtw8821c_read_efuse()
57 efuse->thermal_meter_k = map->thermal_meter; in rtw8821c_read_efuse()
58 efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g; in rtw8821c_read_efuse()
59 efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g; in rtw8821c_read_efuse()
62 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; in rtw8821c_read_efuse()
64 if (rtwdev->efuse.rfe_option == 2 || rtwdev->efuse.rfe_option == 4) in rtw8821c_read_efuse()
65 efuse->txpwr_idx_table[0].pwr_idx_2g = map->txpwr_idx_table[1].pwr_idx_2g; in rtw8821c_read_efuse()
73 return -ENOTSUPP; in rtw8821c_read_efuse()
103 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_pwrtrack_init()
107 dm_info->default_ofdm_index = 24; in rtw8821c_pwrtrack_init()
109 dm_info->default_ofdm_index = swing_idx; in rtw8821c_pwrtrack_init()
111 ewma_thermal_init(&dm_info->avg_thermal[RF_PATH_A]); in rtw8821c_pwrtrack_init()
112 dm_info->delta_power_index[RF_PATH_A] = 0; in rtw8821c_pwrtrack_init()
113 dm_info->delta_power_index_last[RF_PATH_A] = 0; in rtw8821c_pwrtrack_init()
114 dm_info->pwr_trk_triggered = false; in rtw8821c_pwrtrack_init()
115 dm_info->pwr_trk_init_trigger = true; in rtw8821c_pwrtrack_init()
116 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; in rtw8821c_pwrtrack_init()
128 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_phy_set_param()
156 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; in rtw8821c_phy_set_param()
159 rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0); in rtw8821c_phy_set_param()
163 hal->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD); in rtw8821c_phy_set_param()
164 hal->ch_param[1] = rtw_read32_mask(rtwdev, REG_TXSF6, MASKDWORD); in rtw8821c_phy_set_param()
165 hal->ch_param[2] = rtw_read32_mask(rtwdev, REG_TXFILTER, MASKDWORD); in rtw8821c_phy_set_param()
168 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f; in rtw8821c_phy_set_param()
196 rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5)); in rtw8821c_mac_init()
209 /* Set beacon cotnrol - enable TSF and other related functions */ in rtw8821c_mac_init()
226 rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1)); in rtw8821c_mac_init()
240 ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7); in rtw8821c_cfg_ldo25()
311 if (rtwdev->efuse.rfe_option == 0) in rtw8821c_set_channel_rf()
313 else if (rtwdev->efuse.rfe_option == 2 || in rtw8821c_set_channel_rf()
314 rtwdev->efuse.rfe_option == 4) in rtw8821c_set_channel_rf()
316 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1); in rtw8821c_set_channel_rf()
320 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0); in rtw8821c_set_channel_rf()
325 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); in rtw8821c_set_channel_rf()
326 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1); in rtw8821c_set_channel_rf()
333 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
334 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
335 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
336 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
339 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
340 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); in rtw8821c_set_channel_rxdfir()
341 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
342 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1); in rtw8821c_set_channel_rxdfir()
345 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
346 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
347 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); in rtw8821c_set_channel_rxdfir()
348 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
355 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_set_channel_bb()
359 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); in rtw8821c_set_channel_bb()
360 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); in rtw8821c_set_channel_bb()
361 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); in rtw8821c_set_channel_bb()
372 hal->ch_param[0]); in rtw8821c_set_channel_bb()
374 hal->ch_param[1] & MASKLWORD); in rtw8821c_set_channel_bb()
376 hal->ch_param[2]); in rtw8821c_set_channel_bb()
379 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); in rtw8821c_set_channel_bb()
380 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); in rtw8821c_set_channel_bb()
381 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); in rtw8821c_set_channel_bb()
409 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
413 rtw_write32_set(rtwdev, REG_RXSB, BIT(4)); in rtw8821c_set_channel_bb()
415 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4)); in rtw8821c_set_channel_bb()
423 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
432 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
440 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8821c_set_channel_bb()
441 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8821c_set_channel_bb()
449 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8821c_set_channel_bb()
450 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8821c_set_channel_bb()
457 struct rtw_efuse efuse = rtwdev->efuse; in rtw8821c_get_bb_swing()
489 struct rtw_efuse *efuse = &rtwdev->efuse; in get_cck_rx_pwr()
495 if (efuse->rfe_option == 0) { in get_cck_rx_pwr()
505 return -120; in get_cck_rx_pwr()
509 rx_pwr_all = lna_gain - 2 * vga_idx; in get_cck_rx_pwr()
517 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in query_phy_status_page0()
527 pkt_stat->rx_power[RF_PATH_A] = rx_power; in query_phy_status_page0()
528 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); in query_phy_status_page0()
529 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; in query_phy_status_page0()
530 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; in query_phy_status_page0()
531 pkt_stat->signal_power = rx_power; in query_phy_status_page0()
537 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in query_phy_status_page1()
539 s8 min_rx_power = -120; in query_phy_status_page1()
541 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) in query_phy_status_page1()
548 else if (rxsc >= 9 && rxsc <= 12) in query_phy_status_page1()
555 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; in query_phy_status_page1()
556 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); in query_phy_status_page1()
557 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; in query_phy_status_page1()
558 pkt_stat->bw = bw; in query_phy_status_page1()
559 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], in query_phy_status_page1()
588 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; in rtw8821c_query_rx_desc()
593 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); in rtw8821c_query_rx_desc()
594 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); in rtw8821c_query_rx_desc()
595 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); in rtw8821c_query_rx_desc()
596 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) && in rtw8821c_query_rx_desc()
598 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); in rtw8821c_query_rx_desc()
599 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); in rtw8821c_query_rx_desc()
600 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); in rtw8821c_query_rx_desc()
601 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); in rtw8821c_query_rx_desc()
602 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); in rtw8821c_query_rx_desc()
603 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); in rtw8821c_query_rx_desc()
604 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc); in rtw8821c_query_rx_desc()
605 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); in rtw8821c_query_rx_desc()
607 /* drv_info_sz is in unit of 8-bytes */ in rtw8821c_query_rx_desc()
608 pkt_stat->drv_info_sz *= 8; in rtw8821c_query_rx_desc()
611 if (pkt_stat->is_c2h) in rtw8821c_query_rx_desc()
614 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + in rtw8821c_query_rx_desc()
615 pkt_stat->drv_info_sz); in rtw8821c_query_rx_desc()
616 if (pkt_stat->phy_status) { in rtw8821c_query_rx_desc()
617 phy_status = rx_desc + desc_sz + pkt_stat->shift; in rtw8821c_query_rx_desc()
627 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_set_tx_power_index_by_rate()
635 pwr_index = hal->tx_pwr_tbl[path][rate]; in rtw8821c_set_tx_power_index_by_rate()
649 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_set_tx_power_index()
652 for (path = 0; path < hal->rf_path_num; path++) { in rtw8821c_set_tx_power_index()
664 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_false_alarm_statistics()
671 cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28); in rtw8821c_false_alarm_statistics()
675 dm_info->cck_fa_cnt = cck_fa_cnt; in rtw8821c_false_alarm_statistics()
676 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; in rtw8821c_false_alarm_statistics()
678 dm_info->total_fa_cnt += cck_fa_cnt; in rtw8821c_false_alarm_statistics()
679 dm_info->total_fa_cnt = ofdm_fa_cnt; in rtw8821c_false_alarm_statistics()
682 dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
683 dm_info->cck_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); in rtw8821c_false_alarm_statistics()
686 dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
687 dm_info->ofdm_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); in rtw8821c_false_alarm_statistics()
690 dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
691 dm_info->ht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); in rtw8821c_false_alarm_statistics()
694 dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
695 dm_info->vht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); in rtw8821c_false_alarm_statistics()
698 dm_info->ofdm_cca_cnt = FIELD_GET(GENMASK(31, 16), cca32_cnt); in rtw8821c_false_alarm_statistics()
699 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; in rtw8821c_false_alarm_statistics()
702 dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt); in rtw8821c_false_alarm_statistics()
703 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; in rtw8821c_false_alarm_statistics()
706 rtw_write32_set(rtwdev, REG_FAS, BIT(17)); in rtw8821c_false_alarm_statistics()
707 rtw_write32_clr(rtwdev, REG_FAS, BIT(17)); in rtw8821c_false_alarm_statistics()
708 rtw_write32_clr(rtwdev, REG_RXDESC, BIT(15)); in rtw8821c_false_alarm_statistics()
709 rtw_write32_set(rtwdev, REG_RXDESC, BIT(15)); in rtw8821c_false_alarm_statistics()
710 rtw_write32_set(rtwdev, REG_CNTRST, BIT(0)); in rtw8821c_false_alarm_statistics()
711 rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0)); in rtw8821c_false_alarm_statistics()
735 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16)); in rtw8821c_do_iqk()
759 /* enable PTA (3-wire function form BT side) */ in rtw8821c_coex_cfg_init()
770 /* beacon queue always hi-pri */ in rtw8821c_coex_cfg_init()
778 struct rtw_coex *coex = &rtwdev->coex; in rtw8821c_coex_cfg_ant_switch()
779 struct rtw_coex_dm *coex_dm = &coex->dm; in rtw8821c_coex_cfg_ant_switch()
780 struct rtw_coex_rfe *coex_rfe = &coex->rfe; in rtw8821c_coex_cfg_ant_switch()
785 if (switch_status == coex_dm->cur_switch_status) in rtw8821c_coex_cfg_ant_switch()
788 if (coex_rfe->wlg_at_btg) { in rtw8821c_coex_cfg_ant_switch()
791 if (coex_rfe->ant_switch_polarity) in rtw8821c_coex_cfg_ant_switch()
797 coex_dm->cur_switch_status = switch_status; in rtw8821c_coex_cfg_ant_switch()
799 if (coex_rfe->ant_switch_diversity && in rtw8821c_coex_cfg_ant_switch()
803 polarity_inverse = (coex_rfe->ant_switch_polarity == 1); in rtw8821c_coex_cfg_ant_switch()
815 if (coex_rfe->rfe_module_type != 0x4 && in rtw8821c_coex_cfg_ant_switch()
816 coex_rfe->rfe_module_type != 0x2) in rtw8821c_coex_cfg_ant_switch()
887 struct rtw_coex *coex = &rtwdev->coex; in rtw8821c_coex_cfg_rfe_type()
888 struct rtw_coex_rfe *coex_rfe = &coex->rfe; in rtw8821c_coex_cfg_rfe_type()
889 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8821c_coex_cfg_rfe_type()
891 coex_rfe->rfe_module_type = efuse->rfe_option; in rtw8821c_coex_cfg_rfe_type()
892 coex_rfe->ant_switch_polarity = 0; in rtw8821c_coex_cfg_rfe_type()
893 coex_rfe->ant_switch_exist = true; in rtw8821c_coex_cfg_rfe_type()
894 coex_rfe->wlg_at_btg = false; in rtw8821c_coex_cfg_rfe_type()
896 switch (coex_rfe->rfe_module_type) { in rtw8821c_coex_cfg_rfe_type()
900 case 9: /* 1-Ant, Main, WLG */ in rtw8821c_coex_cfg_rfe_type()
901 default: /* 2-Ant, DPDT, WLG */ in rtw8821c_coex_cfg_rfe_type()
904 case 10: /* 1-Ant, Main, BTG */ in rtw8821c_coex_cfg_rfe_type()
906 case 15: /* 2-Ant, DPDT, BTG */ in rtw8821c_coex_cfg_rfe_type()
907 coex_rfe->wlg_at_btg = true; in rtw8821c_coex_cfg_rfe_type()
910 case 11: /* 1-Ant, Aux, WLG */ in rtw8821c_coex_cfg_rfe_type()
911 coex_rfe->ant_switch_polarity = 1; in rtw8821c_coex_cfg_rfe_type()
914 case 12: /* 1-Ant, Aux, BTG */ in rtw8821c_coex_cfg_rfe_type()
915 coex_rfe->wlg_at_btg = true; in rtw8821c_coex_cfg_rfe_type()
916 coex_rfe->ant_switch_polarity = 1; in rtw8821c_coex_cfg_rfe_type()
919 case 13: /* 2-Ant, no switch, WLG */ in rtw8821c_coex_cfg_rfe_type()
921 case 14: /* 2-Ant, no antenna switch, WLG */ in rtw8821c_coex_cfg_rfe_type()
922 coex_rfe->ant_switch_exist = false; in rtw8821c_coex_cfg_rfe_type()
929 struct rtw_coex *coex = &rtwdev->coex; in rtw8821c_coex_cfg_wl_tx_power()
930 struct rtw_coex_dm *coex_dm = &coex->dm; in rtw8821c_coex_cfg_wl_tx_power()
931 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8821c_coex_cfg_wl_tx_power()
932 bool share_ant = efuse->share_ant; in rtw8821c_coex_cfg_wl_tx_power()
937 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) in rtw8821c_coex_cfg_wl_tx_power()
940 coex_dm->cur_wl_pwr_lvl = wl_pwr; in rtw8821c_coex_cfg_wl_tx_power()
951 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_txagc_swing_offset()
952 s8 delta_pwr_idx = dm_info->delta_power_index[RF_PATH_A]; in rtw8821c_txagc_swing_offset()
953 u8 swing_upper_bound = dm_info->default_ofdm_index + 10; in rtw8821c_txagc_swing_offset()
957 u8 swing_index = dm_info->default_ofdm_index; in rtw8821c_txagc_swing_offset()
960 pwr_idx_offset_lower = max_t(s8, pwr_idx_offset_lower, -15); in rtw8821c_txagc_swing_offset()
965 swing_index = dm_info->default_ofdm_index; in rtw8821c_txagc_swing_offset()
968 swing_index = dm_info->default_ofdm_index + in rtw8821c_txagc_swing_offset()
969 delta_pwr_idx - pwr_idx_offset; in rtw8821c_txagc_swing_offset()
975 swing_index = dm_info->default_ofdm_index; in rtw8821c_txagc_swing_offset()
977 if (dm_info->default_ofdm_index > in rtw8821c_txagc_swing_offset()
978 (pwr_idx_offset_lower - delta_pwr_idx)) in rtw8821c_txagc_swing_offset()
979 swing_index = dm_info->default_ofdm_index + in rtw8821c_txagc_swing_offset()
980 delta_pwr_idx - pwr_idx_offset_lower; in rtw8821c_txagc_swing_offset()
990 swing_index = ARRAY_SIZE(rtw8821c_txscale_tbl) - 1; in rtw8821c_txagc_swing_offset()
1012 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_pwrtrack_set()
1015 u8 channel = rtwdev->hal.current_channel; in rtw8821c_pwrtrack_set()
1016 u8 band_width = rtwdev->hal.current_band_width; in rtw8821c_pwrtrack_set()
1018 u8 tx_rate = dm_info->tx_rate; in rtw8821c_pwrtrack_set()
1019 u8 max_pwr_idx = rtwdev->chip->max_power_index; in rtw8821c_pwrtrack_set()
1026 pwr_idx_offset = max_pwr_idx - tx_pwr_idx; in rtw8821c_pwrtrack_set()
1027 pwr_idx_offset_lower = 0 - tx_pwr_idx; in rtw8821c_pwrtrack_set()
1034 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_phy_pwrtrack()
1040 if (rtwdev->efuse.thermal_meter[0] == 0xff) in rtw8821c_phy_pwrtrack()
1047 if (dm_info->pwr_trk_init_trigger) in rtw8821c_phy_pwrtrack()
1048 dm_info->pwr_trk_init_trigger = false; in rtw8821c_phy_pwrtrack()
1055 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1); in rtw8821c_phy_pwrtrack()
1057 dm_info->delta_power_index[RF_PATH_A] = in rtw8821c_phy_pwrtrack()
1060 if (dm_info->delta_power_index[RF_PATH_A] == in rtw8821c_phy_pwrtrack()
1061 dm_info->delta_power_index_last[RF_PATH_A]) in rtw8821c_phy_pwrtrack()
1064 dm_info->delta_power_index_last[RF_PATH_A] = in rtw8821c_phy_pwrtrack()
1065 dm_info->delta_power_index[RF_PATH_A]; in rtw8821c_phy_pwrtrack()
1075 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8821c_pwr_track()
1076 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_pwr_track()
1078 if (efuse->power_track_type != 0) in rtw8821c_pwr_track()
1081 if (!dm_info->pwr_trk_triggered) { in rtw8821c_pwr_track()
1084 dm_info->pwr_trk_triggered = true; in rtw8821c_pwr_track()
1089 dm_info->pwr_trk_triggered = false; in rtw8821c_pwr_track()
1115 if (bfee->role == RTW_BFEE_SU) in rtw8821c_bf_config_bfee()
1117 else if (bfee->role == RTW_BFEE_MU) in rtw8821c_bf_config_bfee()
1125 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_phy_cck_pd_set()
1129 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n", in rtw8821c_phy_cck_pd_set()
1130 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl); in rtw8821c_phy_cck_pd_set()
1132 if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl) in rtw8821c_phy_cck_pd_set()
1140 dm_info->cck_pd_default + new_lvl * 2, in rtw8821c_phy_cck_pd_set()
1141 pd[new_lvl], dm_info->cck_fa_avg); in rtw8821c_phy_cck_pd_set()
1143 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; in rtw8821c_phy_cck_pd_set()
1145 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl; in rtw8821c_phy_cck_pd_set()
1148 dm_info->cck_pd_default + new_lvl * 2); in rtw8821c_phy_cck_pd_set()
1156 RTW_PWR_CMD_WRITE, BIT(0), 0},
1161 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1166 RTW_PWR_CMD_WRITE, BIT(0), 0},
1171 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1194 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1204 RTW_PWR_CMD_WRITE, BIT(5), 0},
1209 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1214 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1219 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1224 RTW_PWR_CMD_WRITE, BIT(0), 0},
1229 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1234 RTW_PWR_CMD_WRITE, BIT(7), 0},
1239 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1244 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1249 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1254 RTW_PWR_CMD_POLLING, BIT(0), 0},
1259 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
1264 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1269 RTW_PWR_CMD_WRITE, BIT(1), 0},
1274 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)),
1275 (BIT(7) | BIT(6) | BIT(5))},
1280 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
1285 RTW_PWR_CMD_WRITE, BIT(1), 0},
1298 RTW_PWR_CMD_WRITE, BIT(3), 0},
1308 RTW_PWR_CMD_WRITE, BIT(1), 0},
1313 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1318 RTW_PWR_CMD_WRITE, BIT(1), 0},
1323 RTW_PWR_CMD_WRITE, BIT(0), 0},
1328 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1333 RTW_PWR_CMD_POLLING, BIT(1), 0},
1338 RTW_PWR_CMD_WRITE, BIT(3), 0},
1343 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1361 RTW_PWR_CMD_WRITE, BIT(5), 0},
1366 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
1371 RTW_PWR_CMD_WRITE, BIT(0), 0},
1376 RTW_PWR_CMD_WRITE, BIT(5), 0},
1381 RTW_PWR_CMD_WRITE, BIT(4), 0},
1386 RTW_PWR_CMD_WRITE, BIT(0), 0},
1391 RTW_PWR_CMD_WRITE, BIT(1), 0},
1396 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
1401 RTW_PWR_CMD_WRITE, BIT(2), 0},
1406 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1411 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1416 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1421 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
1426 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1431 RTW_PWR_CMD_POLLING, BIT(1), 0},
1436 RTW_PWR_CMD_WRITE, BIT(1), 0},
1608 /* rssi in percentage % (dbm = % - 100) */
1612 /* Shared-Antenna Coex Table */
1614 {0x55555555, 0x55555555}, /* case-0 */
1619 {0xfafafafa, 0xfafafafa}, /* case-5 */
1624 {0x66555555, 0x6a5a5a5a}, /* case-10 */
1629 {0x66555555, 0xaaaaaaaa}, /* case-15 */
1634 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
1639 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
1644 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1649 /* Non-Shared-Antenna Coex Table */
1651 {0xffffffff, 0xffffffff}, /* case-100 */
1656 {0xffffffff, 0xffffffff}, /* case-105 */
1661 {0x66555555, 0x6a5a5a5a}, /* case-110 */
1666 {0xffff55ff, 0xffff55ff}, /* case-115 */
1671 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
1677 /* Shared-Antenna TDMA */
1679 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1680 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
1684 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, /* case-5 */
1689 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1694 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1699 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1704 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1709 /* Non-Shared-Antenna TDMA */
1711 { {0x00, 0x00, 0x00, 0x40, 0x00} }, /* case-100 */
1716 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
1721 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
1726 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
1731 { {0x51, 0x21, 0x03, 0x10, 0x50} }, /* case-120 */
1740 {0, 20, false, 7}, /* for WL-CPT */
1749 {0, 20, false, 7}, /* for WL-CPT */
1760 11, 11, 12, 12, 12, 12, 12},
1762 11, 12, 12, 12, 12, 12, 12, 12},
1764 11, 12, 12, 12, 12, 12, 12},
1769 12, 12, 12, 12, 12, 12, 12},
1771 12, 12, 12, 12, 12, 12, 12, 12},
1773 11, 12, 12, 12, 12, 12, 12, 12},
1778 11, 11, 12, 12, 12, 12, 12},
1780 11, 12, 12, 12, 12, 12, 12, 12},
1782 11, 12, 12, 12, 12, 12, 12},
1787 12, 12, 12, 12, 12, 12, 12},
1789 12, 12, 12, 12, 12, 12, 12, 12},
1791 11, 12, 12, 12, 12, 12, 12, 12},
1866 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
1869 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
1870 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
1871 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
1872 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
1877 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
1905 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK),