49 	efuse->lna_type_2g = map->lna_type_2g[0];  in rtw8821c_read_efuse()
50 	efuse->lna_type_5g = map->lna_type_5g[0];  in rtw8821c_read_efuse()
52 	efuse->country_code[0] = map->country_code[0];  in rtw8821c_read_efuse()
55 	efuse->regd = map->rf_board_option & 0x7;  in rtw8821c_read_efuse()
56 	efuse->thermal_meter[0] = map->thermal_meter;  in rtw8821c_read_efuse()
61 	for (i = 0; i < 4; i++)  in rtw8821c_read_efuse()
65 		efuse->txpwr_idx_table[0].pwr_idx_2g = map->txpwr_idx_table[1].pwr_idx_2g;  in rtw8821c_read_efuse()
76 	return 0;  in rtw8821c_read_efuse()
80 	0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8,
81 	0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180,
82 	0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab,
83 	0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe
88 	u8 i = 0;  in rtw8821c_get_swing_index()
91 	swing = rtw_read32_mask(rtwdev, REG_TXSCALE_A, 0xffe00000);  in rtw8821c_get_swing_index()
92 	for (i = 0; i < ARRAY_SIZE(rtw8821c_txscale_tbl); i++) {  in rtw8821c_get_swing_index()
112 	dm_info->delta_power_index[RF_PATH_A] = 0;  in rtw8821c_pwrtrack_init()
113 	dm_info->delta_power_index_last[RF_PATH_A] = 0;  in rtw8821c_pwrtrack_init()
123 	rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF);  in rtw8821c_phy_bf_init()
156 	crystal_cap = rtwdev->efuse.crystal_cap & 0x3F;  in rtw8821c_phy_set_param()
157 	rtw_write32_mask(rtwdev, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap);  in rtw8821c_phy_set_param()
158 	rtw_write32_mask(rtwdev, REG_AFE_PLL_CTRL, 0x7e, crystal_cap);  in rtw8821c_phy_set_param()
159 	rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0);  in rtw8821c_phy_set_param()
163 	hal->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD);  in rtw8821c_phy_set_param()
168 	rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f;  in rtw8821c_phy_set_param()
184 	rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF));  in rtw8821c_mac_init()
200 	rtw_write16(rtwdev, REG_TXPAUSE, 0);  in rtw8821c_mac_init()
225 	rtw_write8(rtwdev, REG_ACKTO_CCK, 0x40);  in rtw8821c_mac_init()
232 	return 0;  in rtw8821c_mac_init()
282 	rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);  in rtw8821c_set_channel_rf()
311 		if (rtwdev->efuse.rfe_option == 0)  in rtw8821c_set_channel_rf()
316 		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1);  in rtw8821c_set_channel_rf()
317 		rtw_write_rf(rtwdev, RF_PATH_A, 0x64, 0xf, 0xf);  in rtw8821c_set_channel_rf()
320 		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0);  in rtw8821c_set_channel_rf()
323 	rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18);  in rtw8821c_set_channel_rf()
325 	rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0);  in rtw8821c_set_channel_rf()
333 		rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);  in rtw8821c_set_channel_rxdfir()
334 		rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);  in rtw8821c_set_channel_rxdfir()
335 		rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);  in rtw8821c_set_channel_rxdfir()
336 		rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0);  in rtw8821c_set_channel_rxdfir()
339 		rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);  in rtw8821c_set_channel_rxdfir()
340 		rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1);  in rtw8821c_set_channel_rxdfir()
341 		rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);  in rtw8821c_set_channel_rxdfir()
342 		rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1);  in rtw8821c_set_channel_rxdfir()
345 		rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);  in rtw8821c_set_channel_rxdfir()
346 		rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);  in rtw8821c_set_channel_rxdfir()
347 		rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1);  in rtw8821c_set_channel_rxdfir()
348 		rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0);  in rtw8821c_set_channel_rxdfir()
359 		rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1);  in rtw8821c_set_channel_bb()
360 		rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0);  in rtw8821c_set_channel_bb()
361 		rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0);  in rtw8821c_set_channel_bb()
362 		rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15);  in rtw8821c_set_channel_bb()
364 		rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x0);  in rtw8821c_set_channel_bb()
365 		rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a);  in rtw8821c_set_channel_bb()
367 			rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c);  in rtw8821c_set_channel_bb()
368 			rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000);  in rtw8821c_set_channel_bb()
369 			rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667);  in rtw8821c_set_channel_bb()
372 					 hal->ch_param[0]);  in rtw8821c_set_channel_bb()
379 		rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1);  in rtw8821c_set_channel_bb()
380 		rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1);  in rtw8821c_set_channel_bb()
381 		rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0);  in rtw8821c_set_channel_bb()
382 		rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15);  in rtw8821c_set_channel_bb()
385 			rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x1);  in rtw8821c_set_channel_bb()
387 			rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x2);  in rtw8821c_set_channel_bb()
389 			rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x3);  in rtw8821c_set_channel_bb()
392 			rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494);  in rtw8821c_set_channel_bb()
394 			rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453);  in rtw8821c_set_channel_bb()
396 			rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452);  in rtw8821c_set_channel_bb()
398 			rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412);  in rtw8821c_set_channel_bb()
405 		val32 &= 0xffcffc00;  in rtw8821c_set_channel_bb()
406 		val32 |= 0x10010000;  in rtw8821c_set_channel_bb()
409 		rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);  in rtw8821c_set_channel_bb()
418 		val32 &= 0xff3ff300;  in rtw8821c_set_channel_bb()
419 		val32 |= 0x20020000 | ((primary_ch_idx & 0xf) << 2) |  in rtw8821c_set_channel_bb()
423 		rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);  in rtw8821c_set_channel_bb()
427 		val32 &= 0xfcffcf00;  in rtw8821c_set_channel_bb()
428 		val32 |= 0x40040000 | ((primary_ch_idx & 0xf) << 2) |  in rtw8821c_set_channel_bb()
432 		rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);  in rtw8821c_set_channel_bb()
436 		val32 &= 0xefcefc00;  in rtw8821c_set_channel_bb()
437 		val32 |= 0x200240;  in rtw8821c_set_channel_bb()
440 		rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);  in rtw8821c_set_channel_bb()
441 		rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);  in rtw8821c_set_channel_bb()
445 		val32 &= 0xefcefc00;  in rtw8821c_set_channel_bb()
446 		val32 |= 0x300380;  in rtw8821c_set_channel_bb()
449 		rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);  in rtw8821c_set_channel_bb()
450 		rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);  in rtw8821c_set_channel_bb()
459 	u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6};  in rtw8821c_get_bb_swing()
464 		tx_bb_swing = 0;  in rtw8821c_get_bb_swing()
492 	s8 rx_pwr_all = 0;  in get_cck_rx_pwr()
493 	s8 lna_gain = 0;  in get_cck_rx_pwr()
495 	if (efuse->rfe_option == 0) {  in get_cck_rx_pwr()
519 	u8 lna_idx = 0;  in query_phy_status_page0()
520 	u8 vga_idx = 0;  in query_phy_status_page0()
568 	page = *phy_status & 0xf;  in query_phy_status()
571 	case 0:  in query_phy_status()
591 	memset(pkt_stat, 0, sizeof(*pkt_stat));  in rtw8821c_query_rx_desc()
628 	static const u32 offset_txagc[2] = {0x1d00, 0x1d80};  in rtw8821c_set_tx_power_index_by_rate()
633 	for (j = 0; j < rtw_rate_size[rs]; j++) {  in rtw8821c_set_tx_power_index_by_rate()
636 		shift = rate & 0x3;  in rtw8821c_set_tx_power_index_by_rate()
638 		if (shift == 0x3 || rate == DESC_RATEVHT1SS_MCS9) {  in rtw8821c_set_tx_power_index_by_rate()
639 			rate_idx = rate & 0xfc;  in rtw8821c_set_tx_power_index_by_rate()
642 			phy_pwr_idx = 0;  in rtw8821c_set_tx_power_index_by_rate()
652 	for (path = 0; path < hal->rf_path_num; path++) {  in rtw8821c_set_tx_power_index()
653 		for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) {  in rtw8821c_set_tx_power_index()
682 	dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);  in rtw8821c_false_alarm_statistics()
686 	dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);  in rtw8821c_false_alarm_statistics()
690 	dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);  in rtw8821c_false_alarm_statistics()
694 	dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);  in rtw8821c_false_alarm_statistics()
702 		dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt);  in rtw8821c_false_alarm_statistics()
710 	rtw_write32_set(rtwdev, REG_CNTRST, BIT(0));  in rtw8821c_false_alarm_statistics()
711 	rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0));  in rtw8821c_false_alarm_statistics()
717 	struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0};  in rtw8821c_do_iqk()
727 	for (counter = 0; counter < 300; counter++) {  in rtw8821c_do_iqk()
729 		if (rf_reg == 0xabcde)  in rtw8821c_do_iqk()
733 	rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0);  in rtw8821c_do_iqk()
736 	iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0));  in rtw8821c_do_iqk()
738 		"iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n",  in rtw8821c_do_iqk()
754 	rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);  in rtw8821c_coex_cfg_init()
783 	u8 regval = 0;  in rtw8821c_coex_cfg_ant_switch()
815 			if (coex_rfe->rfe_module_type != 0x4 &&  in rtw8821c_coex_cfg_ant_switch()
816 			    coex_rfe->rfe_module_type != 0x2)  in rtw8821c_coex_cfg_ant_switch()
817 				regval = 0x3;  in rtw8821c_coex_cfg_ant_switch()
819 				regval = (!polarity_inverse ? 0x2 : 0x1);  in rtw8821c_coex_cfg_ant_switch()
821 			regval = (!polarity_inverse ? 0x2 : 0x1);  in rtw8821c_coex_cfg_ant_switch()
823 			regval = (!polarity_inverse ? 0x1 : 0x2);  in rtw8821c_coex_cfg_ant_switch()
836 		regval = (!polarity_inverse ? 0x2 : 0x1);  in rtw8821c_coex_cfg_ant_switch()
849 		regval = (!polarity_inverse ? 0x0 : 0x1);  in rtw8821c_coex_cfg_ant_switch()
892 	coex_rfe->ant_switch_polarity = 0;  in rtw8821c_coex_cfg_rfe_type()
897 	case 0:  in rtw8821c_coex_cfg_rfe_type()
954 	u8 swing_lower_bound = 0;  in rtw8821c_txagc_swing_offset()
955 	u8 max_pwr_idx_offset = 0xf;  in rtw8821c_txagc_swing_offset()
956 	s8 agc_index = 0;  in rtw8821c_txagc_swing_offset()
962 	if (delta_pwr_idx >= 0) {  in rtw8821c_txagc_swing_offset()
972 	} else if (delta_pwr_idx < 0) {  in rtw8821c_txagc_swing_offset()
1027 	pwr_idx_offset_lower = 0 - tx_pwr_idx;  in rtw8821c_pwrtrack_set()
1040 	if (rtwdev->efuse.thermal_meter[0] == 0xff)  in rtw8821c_phy_pwrtrack()
1043 	thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00);  in rtw8821c_phy_pwrtrack()
1078 	if (efuse->power_track_type != 0)  in rtw8821c_pwr_track()
1083 			     GENMASK(17, 16), 0x03);  in rtw8821c_pwr_track()
1138 		"is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x, cck_fa_avg=%d\n",  in rtw8821c_phy_cck_pd_set()
1146 	rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]);  in rtw8821c_phy_cck_pd_set()
1147 	rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000,  in rtw8821c_phy_cck_pd_set()
1152 	{0x0086,
1156 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1157 	{0x0086,
1162 	{0x004A,
1166 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1167 	{0x0005,
1171 	 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1172 	{0x0300,
1176 	 RTW_PWR_CMD_WRITE, 0xFF, 0},
1177 	{0x0301,
1181 	 RTW_PWR_CMD_WRITE, 0xFF, 0},
1182 	{0xFFFF,
1185 	 0,
1186 	 RTW_PWR_CMD_END, 0, 0},
1190 	{0x0020,
1194 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1195 	{0x0001,
1200 	{0x0000,
1204 	 RTW_PWR_CMD_WRITE, BIT(5), 0},
1205 	{0x0005,
1209 	 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1210 	{0x0075,
1214 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1215 	{0x0006,
1220 	{0x0075,
1224 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1225 	{0x0006,
1229 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1230 	{0x0005,
1234 	 RTW_PWR_CMD_WRITE, BIT(7), 0},
1235 	{0x0005,
1239 	 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1240 	{0x10C3,
1244 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1245 	{0x0005,
1249 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1250 	{0x0005,
1254 	 RTW_PWR_CMD_POLLING, BIT(0), 0},
1255 	{0x0020,
1260 	{0x0074,
1265 	{0x0022,
1269 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1270 	{0x0062,
1276 	{0x0061,
1280 	 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
1281 	{0x007C,
1285 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1286 	{0xFFFF,
1289 	 0,
1290 	 RTW_PWR_CMD_END, 0, 0},
1294 	{0x0093,
1298 	 RTW_PWR_CMD_WRITE, BIT(3), 0},
1299 	{0x001F,
1303 	 RTW_PWR_CMD_WRITE, 0xFF, 0},
1304 	{0x0049,
1308 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1309 	{0x0006,
1313 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1314 	{0x0002,
1318 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1319 	{0x10C3,
1323 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1324 	{0x0005,
1329 	{0x0005,
1333 	 RTW_PWR_CMD_POLLING, BIT(1), 0},
1334 	{0x0020,
1338 	 RTW_PWR_CMD_WRITE, BIT(3), 0},
1339 	{0x0000,
1344 	{0xFFFF,
1347 	 0,
1348 	 RTW_PWR_CMD_END, 0, 0},
1352 	{0x0007,
1356 	 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
1357 	{0x0067,
1361 	 RTW_PWR_CMD_WRITE, BIT(5), 0},
1362 	{0x0005,
1367 	{0x004A,
1371 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1372 	{0x0067,
1376 	 RTW_PWR_CMD_WRITE, BIT(5), 0},
1377 	{0x0067,
1381 	 RTW_PWR_CMD_WRITE, BIT(4), 0},
1382 	{0x004F,
1386 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1387 	{0x0067,
1391 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1392 	{0x0046,
1397 	{0x0067,
1401 	 RTW_PWR_CMD_WRITE, BIT(2), 0},
1402 	{0x0046,
1407 	{0x0062,
1412 	{0x0081,
1416 	 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1417 	{0x0005,
1422 	{0x0086,
1426 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1427 	{0x0086,
1431 	 RTW_PWR_CMD_POLLING, BIT(1), 0},
1432 	{0x0090,
1436 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1437 	{0x0044,
1441 	 RTW_PWR_CMD_WRITE, 0xFF, 0},
1442 	{0x0040,
1446 	 RTW_PWR_CMD_WRITE, 0xFF, 0x90},
1447 	{0x0041,
1451 	 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1452 	{0x0042,
1456 	 RTW_PWR_CMD_WRITE, 0xFF, 0x04},
1457 	{0xFFFF,
1460 	 0,
1461 	 RTW_PWR_CMD_END, 0, 0},
1477 	{0xFFFF, 0x00,
1484 	{0xFFFF, 0x0000,
1491 	{0x0009, 0x6380,
1495 	{0xFFFF, 0x0000,
1502 	{0xFFFF, 0x0000,
1520 	[0] = RTW_DEF_RFE(8821c, 0, 0),
1521 	[2] = RTW_DEF_RFE_EXT(8821c, 0, 0, 2),
1522 	[4] = RTW_DEF_RFE_EXT(8821c, 0, 0, 2),
1523 	[6] = RTW_DEF_RFE(8821c, 0, 0),
1527 	[0] = { .addr = 0xc50, .mask = 0x7f },
1537 	/* not sure what [0] stands for */
1540 	{16, 16, 0, 0, 1},
1541 	{16, 16, 16, 0, 1},
1546 	/* not sure what [0] stands for */
1614 	{0x55555555, 0x55555555}, /* case-0 */
1615 	{0x55555555, 0x55555555},
1616 	{0x66555555, 0x66555555},
1617 	{0xaaaaaaaa, 0xaaaaaaaa},
1618 	{0x5a5a5a5a, 0x5a5a5a5a},
1619 	{0xfafafafa, 0xfafafafa}, /* case-5 */
1620 	{0x6a5a5555, 0xaaaaaaaa},
1621 	{0x6a5a56aa, 0x6a5a56aa},
1622 	{0x6a5a5a5a, 0x6a5a5a5a},
1623 	{0x66555555, 0x5a5a5a5a},
1624 	{0x66555555, 0x6a5a5a5a}, /* case-10 */
1625 	{0x66555555, 0xaaaaaaaa},
1626 	{0x66555555, 0x6a5a5aaa},
1627 	{0x66555555, 0x6aaa6aaa},
1628 	{0x66555555, 0x6a5a5aaa},
1629 	{0x66555555, 0xaaaaaaaa}, /* case-15 */
1630 	{0xffff55ff, 0xfafafafa},
1631 	{0xffff55ff, 0x6afa5afa},
1632 	{0xaaffffaa, 0xfafafafa},
1633 	{0xaa5555aa, 0x5a5a5a5a},
1634 	{0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
1635 	{0xaa5555aa, 0xaaaaaaaa},
1636 	{0xffffffff, 0x55555555},
1637 	{0xffffffff, 0x5a5a5a5a},
1638 	{0xffffffff, 0x5a5a5a5a},
1639 	{0xffffffff, 0x5a5a5aaa}, /* case-25 */
1640 	{0x55555555, 0x5a5a5a5a},
1641 	{0x55555555, 0xaaaaaaaa},
1642 	{0x66555555, 0x6a5a6a5a},
1643 	{0x66556655, 0x66556655},
1644 	{0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1645 	{0xffffffff, 0x5aaa5aaa},
1646 	{0x56555555, 0x5a5a5aaa}
1651 	{0xffffffff, 0xffffffff}, /* case-100 */
1652 	{0xffff55ff, 0xfafafafa},
1653 	{0x66555555, 0x66555555},
1654 	{0xaaaaaaaa, 0xaaaaaaaa},
1655 	{0x5a5a5a5a, 0x5a5a5a5a},
1656 	{0xffffffff, 0xffffffff}, /* case-105 */
1657 	{0x5afa5afa, 0x5afa5afa},
1658 	{0x55555555, 0xfafafafa},
1659 	{0x66555555, 0xfafafafa},
1660 	{0x66555555, 0x5a5a5a5a},
1661 	{0x66555555, 0x6a5a5a5a}, /* case-110 */
1662 	{0x66555555, 0xaaaaaaaa},
1663 	{0xffff55ff, 0xfafafafa},
1664 	{0xffff55ff, 0x5afa5afa},
1665 	{0xffff55ff, 0xaaaaaaaa},
1666 	{0xffff55ff, 0xffff55ff}, /* case-115 */
1667 	{0xaaffffaa, 0x5afa5afa},
1668 	{0xaaffffaa, 0xaaaaaaaa},
1669 	{0xffffffff, 0xfafafafa},
1670 	{0xffff55ff, 0xfafafafa},
1671 	{0xffffffff, 0xaaaaaaaa}, /* case-120 */
1672 	{0xffff55ff, 0x5afa5afa},
1673 	{0xffff55ff, 0x5afa5afa},
1674 	{0x55ff55ff, 0x55ff55ff}
1679 	{ {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1680 	{ {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
1681 	{ {0x61, 0x3a, 0x03, 0x11, 0x11} },
1682 	{ {0x61, 0x35, 0x03, 0x11, 0x11} },
1683 	{ {0x61, 0x20, 0x03, 0x11, 0x11} },
1684 	{ {0x61, 0x3a, 0x03, 0x11, 0x11} }, /* case-5 */
1685 	{ {0x61, 0x45, 0x03, 0x11, 0x10} },
1686 	{ {0x61, 0x35, 0x03, 0x11, 0x10} },
1687 	{ {0x61, 0x30, 0x03, 0x11, 0x10} },
1688 	{ {0x61, 0x20, 0x03, 0x11, 0x10} },
1689 	{ {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1690 	{ {0x61, 0x08, 0x03, 0x11, 0x15} },
1691 	{ {0x61, 0x08, 0x03, 0x10, 0x14} },
1692 	{ {0x51, 0x08, 0x03, 0x10, 0x54} },
1693 	{ {0x51, 0x08, 0x03, 0x10, 0x55} },
1694 	{ {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1695 	{ {0x51, 0x45, 0x03, 0x10, 0x50} },
1696 	{ {0x51, 0x3a, 0x03, 0x11, 0x50} },
1697 	{ {0x51, 0x30, 0x03, 0x10, 0x50} },
1698 	{ {0x51, 0x21, 0x03, 0x10, 0x50} },
1699 	{ {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1700 	{ {0x51, 0x4a, 0x03, 0x10, 0x50} },
1701 	{ {0x51, 0x08, 0x03, 0x30, 0x54} },
1702 	{ {0x55, 0x08, 0x03, 0x10, 0x54} },
1703 	{ {0x65, 0x10, 0x03, 0x11, 0x10} },
1704 	{ {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1705 	{ {0x51, 0x21, 0x03, 0x10, 0x50} },
1706 	{ {0x61, 0x08, 0x03, 0x11, 0x11} }
1711 	{ {0x00, 0x00, 0x00, 0x40, 0x00} }, /* case-100 */
1712 	{ {0x61, 0x45, 0x03, 0x11, 0x11} },
1713 	{ {0x61, 0x25, 0x03, 0x11, 0x11} },
1714 	{ {0x61, 0x35, 0x03, 0x11, 0x11} },
1715 	{ {0x61, 0x20, 0x03, 0x11, 0x11} },
1716 	{ {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
1717 	{ {0x61, 0x45, 0x03, 0x11, 0x10} },
1718 	{ {0x61, 0x30, 0x03, 0x11, 0x10} },
1719 	{ {0x61, 0x30, 0x03, 0x11, 0x10} },
1720 	{ {0x61, 0x20, 0x03, 0x11, 0x10} },
1721 	{ {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
1722 	{ {0x61, 0x10, 0x03, 0x11, 0x11} },
1723 	{ {0x61, 0x08, 0x03, 0x10, 0x14} },
1724 	{ {0x51, 0x08, 0x03, 0x10, 0x54} },
1725 	{ {0x51, 0x08, 0x03, 0x10, 0x55} },
1726 	{ {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
1727 	{ {0x51, 0x45, 0x03, 0x10, 0x50} },
1728 	{ {0x51, 0x3a, 0x03, 0x10, 0x50} },
1729 	{ {0x51, 0x30, 0x03, 0x10, 0x50} },
1730 	{ {0x51, 0x21, 0x03, 0x10, 0x50} },
1731 	{ {0x51, 0x21, 0x03, 0x10, 0x50} }, /* case-120 */
1732 	{ {0x51, 0x10, 0x03, 0x10, 0x50} }
1735 static const struct coex_5g_afh_map afh_5g_8821c[] = { {0, 0, 0} };
1739 	{0, 0, false, 7},  /* for normal */
1740 	{0, 20, false, 7}, /* for WL-CPT */
1748 	{0, 0, false, 7},  /* for normal */
1749 	{0, 20, false, 7}, /* for WL-CPT */
1753 	{0, 28, true, 5}
1759 	{0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10,
1761 	{0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11,
1763 	{0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11,
1768 	{0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11,
1770 	{0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11,
1772 	{0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11,
1777 	{0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10,
1779 	{0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11,
1781 	{0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11,
1786 	{0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11,
1788 	{0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11,
1790 	{0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11,
1795 	0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4,
1800 	0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5,
1805 	0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4,
1810 	0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5,
1815 	0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4,
1820 	0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5,
1825 	0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4,
1830 	0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5,
1835 	.pwrtrk_5gb_n[0] = rtw8821c_pwrtrk_5gb_n[0],
1838 	.pwrtrk_5gb_p[0] = rtw8821c_pwrtrk_5gb_p[0],
1841 	.pwrtrk_5ga_n[0] = rtw8821c_pwrtrk_5ga_n[0],
1844 	.pwrtrk_5ga_p[0] = rtw8821c_pwrtrk_5ga_p[0],
1858 	{0xCB0, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1859 	{0xCB4, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1860 	{0xCBA, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1861 	{0, 0, RTW_REG_DOMAIN_NL},
1862 	{0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1863 	{0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1864 	{0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
1865 	{0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1866 	{0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
1867 	{0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
1868 	{0, 0, RTW_REG_DOMAIN_NL},
1869 	{0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
1870 	{0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
1871 	{0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
1872 	{0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
1873 	{0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_A},
1874 	{0, 0, RTW_REG_DOMAIN_NL},
1875 	{0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1876 	{0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1877 	{0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
1878 	{0xc50,  MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1879 	{0x60A, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1898 	.max_power_index = 0x3f,
1899 	.csi_buf_pg_num = 0,
1902 	.dig_min = 0x1c,
1906 	.sys_func_en = 0xD8,
1914 	.rf_base_addr = {0x2800, 0x2c00},
1915 	.rf_sipi_addr = {0xc90, 0xe90},
1931 	.coex_para_ver = 0x19092746,
1932 	.bt_desired_ver = 0x46,
1954 	.bt_afh_span_bw20 = 0x24,
1955 	.bt_afh_span_bw40 = 0x36,