19 	[DESC_RATE1M]	= { .addr = 0xe08, .mask = 0x0000ff00 },
20 	[DESC_RATE2M]	= { .addr = 0x86c, .mask = 0x0000ff00 },
21 	[DESC_RATE5_5M]	= { .addr = 0x86c, .mask = 0x00ff0000 },
22 	[DESC_RATE11M]	= { .addr = 0x86c, .mask = 0xff000000 },
23 	[DESC_RATE6M]	= { .addr = 0xe00, .mask = 0x000000ff },
24 	[DESC_RATE9M]	= { .addr = 0xe00, .mask = 0x0000ff00 },
25 	[DESC_RATE12M]	= { .addr = 0xe00, .mask = 0x00ff0000 },
26 	[DESC_RATE18M]	= { .addr = 0xe00, .mask = 0xff000000 },
27 	[DESC_RATE24M]	= { .addr = 0xe04, .mask = 0x000000ff },
28 	[DESC_RATE36M]	= { .addr = 0xe04, .mask = 0x0000ff00 },
29 	[DESC_RATE48M]	= { .addr = 0xe04, .mask = 0x00ff0000 },
30 	[DESC_RATE54M]	= { .addr = 0xe04, .mask = 0xff000000 },
31 	[DESC_RATEMCS0]	= { .addr = 0xe10, .mask = 0x000000ff },
32 	[DESC_RATEMCS1]	= { .addr = 0xe10, .mask = 0x0000ff00 },
33 	[DESC_RATEMCS2]	= { .addr = 0xe10, .mask = 0x00ff0000 },
34 	[DESC_RATEMCS3]	= { .addr = 0xe10, .mask = 0xff000000 },
35 	[DESC_RATEMCS4]	= { .addr = 0xe14, .mask = 0x000000ff },
36 	[DESC_RATEMCS5]	= { .addr = 0xe14, .mask = 0x0000ff00 },
37 	[DESC_RATEMCS6]	= { .addr = 0xe14, .mask = 0x00ff0000 },
38 	[DESC_RATEMCS7]	= { .addr = 0xe14, .mask = 0xff000000 },
41 #define WLAN_TXQ_RPT_EN		0x1F
42 #define WLAN_SLOT_TIME		0x09
43 #define WLAN_RL_VAL		0x3030
44 #define WLAN_BAR_VAL		0x0201ffff
45 #define BIT_MASK_TBTT_HOLD	0x00000fff
47 #define BIT_MASK_TBTT_SETUP	0x000000ff
48 #define BIT_SHIFT_TBTT_SETUP	0
53 #define WLAN_TBTT_TIME_NORMAL	TBTT_TIME(0x04, 0x80)
54 #define WLAN_TBTT_TIME_STOP_BCN	TBTT_TIME(0x04, 0x64)
55 #define WLAN_PIFS_VAL		0
56 #define WLAN_AGG_BRK_TIME	0x16
57 #define WLAN_NAV_PROT_LEN	0x0040
58 #define WLAN_SPEC_SIFS		0x100a
59 #define WLAN_RX_PKT_LIMIT	0x17
60 #define WLAN_MAX_AGG_NR		0x0A
61 #define WLAN_AMPDU_MAX_TIME	0x1C
62 #define WLAN_ANT_SEL		0x82
63 #define WLAN_LTR_IDLE_LAT	0x90039003
64 #define WLAN_LTR_ACT_LAT	0x883c883c
65 #define WLAN_LTR_CTRL1		0xCB004010
66 #define WLAN_LTR_CTRL2		0x01233425
75 	if ((val_ctx & BIT_MASK_CTX_TYPE) != 0)  in rtw8723d_lck()
78 		rtw_write8(rtwdev, REG_TXPAUSE, 0xFF);  in rtw8723d_lck()
83 	ret = read_poll_timeout(rtw_read_rf, rf_val, rf_val != 0x1,  in rtw8723d_lck()
90 	if ((val_ctx & BIT_MASK_CTX_TYPE) != 0)  in rtw8723d_lck()
93 		rtw_write8(rtwdev, REG_TXPAUSE, 0x00);  in rtw8723d_lck()
97 	0x0b40002d, 0x0c000030, 0x0cc00033, 0x0d800036, 0x0e400039, 0x0f00003c,
98 	0x10000040, 0x11000044, 0x12000048, 0x1300004c, 0x14400051, 0x15800056,
99 	0x16c0005b, 0x18000060, 0x19800066, 0x1b00006c, 0x1c800072, 0x1e400079,
100 	0x20000080, 0x22000088, 0x24000090, 0x26000098, 0x288000a2, 0x2ac000ab,
101 	0x2d4000b5, 0x300000c0, 0x32c000cb, 0x35c000d7, 0x390000e4, 0x3c8000f2,
102 	0x40000100, 0x43c0010f, 0x47c0011f, 0x4c000130, 0x50800142, 0x55400155,
103 	0x5a400169, 0x5fc0017f, 0x65400195, 0x6b8001ae, 0x71c001c7, 0x788001e2,
104 	0x7f8001fe,
108 	0x0CD, 0x0D9, 0x0E6, 0x0F3, 0x102, 0x111, 0x121, 0x132, 0x144, 0x158,
109 	0x16C, 0x182, 0x198, 0x1B1, 0x1CA, 0x1E5, 0x202, 0x221, 0x241, 0x263,
110 	0x287, 0x2AE, 0x2D6, 0x301, 0x32F, 0x35F, 0x392, 0x3C9, 0x402, 0x43F,
111 	0x47F, 0x4C3, 0x50C, 0x558, 0x5A9, 0x5FF, 0x65A, 0x6BA, 0x720, 0x78C,
112 	0x7FF,
127 		dm_info->delta_power_index[path] = 0;  in rtw8723d_pwrtrack_init()
132 	dm_info->txagc_remnant_cck = 0;  in rtw8723d_pwrtrack_init()
133 	dm_info->txagc_remnant_ofdm = 0;  in rtw8723d_pwrtrack_init()
146 	rtw_write8(rtwdev, REG_AFE_CTRL1 + 1, 0x80);  in rtw8723d_phy_set_param()
155 	xtal_cap = rtwdev->efuse.crystal_cap & 0x3F;  in rtw8723d_phy_set_param()
170 	rtw_write8(rtwdev, REG_ATIMWND, 0x2);  in rtw8723d_phy_set_param()
195 	rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f;  in rtw8723d_phy_set_param()
201 	rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50);  in rtw8723d_phy_set_param()
202 	rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20);  in rtw8723d_phy_set_param()
221 	efuse->rfe_option = 0;  in rtw8723d_read_efuse()
225 	efuse->lna_type_2g = map->lna_type_2g[0];  in rtw8723d_read_efuse()
227 	efuse->country_code[0] = map->country_code[0];  in rtw8723d_read_efuse()
230 	efuse->regd = map->rf_board_option & 0x7;  in rtw8723d_read_efuse()
231 	efuse->thermal_meter[0] = map->thermal_meter;  in rtw8723d_read_efuse()
235 	for (i = 0; i < 4; i++)  in rtw8723d_read_efuse()
247 	return 0;  in rtw8723d_read_efuse()
278 	if (GET_PHY_STAT_P1_RF_MODE(phy_status) == 0)  in query_phy_status_page1()
299 	rx_evm = clamp_t(s8, -pkt_stat->rx_evm[RF_PATH_A] >> 1, 0, 64);  in query_phy_status_page1()
300 	rx_evm &= 0x3F;	/* 64->0: second path of 1SS rate is 64 */  in query_phy_status_page1()
309 	page = *phy_status & 0xf;  in query_phy_status()
312 	case 0:  in query_phy_status()
332 	memset(pkt_stat, 0, sizeof(*pkt_stat));  in rtw8723d_query_rx_desc()
345 	pkt_stat->ppdu_cnt = 0;  in rtw8723d_query_rx_desc()
395 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f);  in rtw8723d_cfg_notch()
396 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);  in rtw8723d_cfg_notch()
397 		rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);  in rtw8723d_cfg_notch()
398 		rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);  in rtw8723d_cfg_notch()
399 		rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);  in rtw8723d_cfg_notch()
400 		rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);  in rtw8723d_cfg_notch()
401 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);  in rtw8723d_cfg_notch()
407 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb);  in rtw8723d_cfg_notch()
408 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);  in rtw8723d_cfg_notch()
409 		rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x04000000);  in rtw8723d_cfg_notch()
410 		rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);  in rtw8723d_cfg_notch()
411 		rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);  in rtw8723d_cfg_notch()
412 		rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);  in rtw8723d_cfg_notch()
413 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);  in rtw8723d_cfg_notch()
416 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x5);  in rtw8723d_cfg_notch()
417 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);  in rtw8723d_cfg_notch()
418 		rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);  in rtw8723d_cfg_notch()
419 		rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);  in rtw8723d_cfg_notch()
420 		rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);  in rtw8723d_cfg_notch()
421 		rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00080000);  in rtw8723d_cfg_notch()
422 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);  in rtw8723d_cfg_notch()
425 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);  in rtw8723d_cfg_notch()
426 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);  in rtw8723d_cfg_notch()
475 	[0] = {
476 		{ .len = 4, .reg = 0xA24, .val = 0x64B80C1C },
477 		{ .len = 4, .reg = 0xA28, .val = 0x00008810 },
478 		{ .len = 4, .reg = 0xAAC, .val = 0x01235667 },
481 		{ .len = 4, .reg = 0xA24, .val = 0x0000B81C },
482 		{ .len = 4, .reg = 0xA28, .val = 0x00000000 },
483 		{ .len = 4, .reg = 0xAAC, .val = 0x00003667 },
493 	cck_dfir = channel <= 13 ? cck_dfir_cfg[0] : cck_dfir_cfg[1];  in rtw8723d_set_channel_bb()
495 	for (i = 0; i < CCK_DFIR_NR; i++, cck_dfir++)  in rtw8723d_set_channel_bb()
500 		rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x0);  in rtw8723d_set_channel_bb()
501 		rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x0);  in rtw8723d_set_channel_bb()
503 		rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_MASK_RXBB_DFIR, 0xa);  in rtw8723d_set_channel_bb()
506 		rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x1);  in rtw8723d_set_channel_bb()
507 		rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x1);  in rtw8723d_set_channel_bb()
508 		rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_RXBB_DFIR_EN, 0);  in rtw8723d_set_channel_bb()
510 				 (primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0));  in rtw8723d_set_channel_bb()
530 #define WLAN_RX_FILTER0		0xFFFF
531 #define WLAN_RX_FILTER1		0x400
532 #define WLAN_RX_FILTER2		0xFFFF
533 #define WLAN_RCR_CFG		0x700060CE
545 	rtw_write32(rtwdev, REG_INT_MIG, 0);  in rtw8723d_mac_init()
546 	rtw_write32(rtwdev, REG_MCUTST_1, 0x0);  in rtw8723d_mac_init()
549 	rtw_write8(rtwdev, REG_2ND_CCA_CTRL, 0);  in rtw8723d_mac_init()
551 	return 0;  in rtw8723d_mac_init()
581 	for (j = 0; j < rtw_rate_size[rs]; j++) {  in rtw8723d_set_tx_power_index_by_rate()
586 			rtw_warn(rtwdev, "rate 0x%x isn't supported\n", rate);  in rtw8723d_set_tx_power_index_by_rate()
591 			rtw_warn(rtwdev, "rate 0x%x isn't defined\n", rate);  in rtw8723d_set_tx_power_index_by_rate()
604 	for (path = 0; path < hal->rf_path_num; path++) {  in rtw8723d_set_tx_power_index()
605 		for (rs = 0; rs <= RTW_RATE_SECTION_HT_1S; rs++)  in rtw8723d_set_tx_power_index()
663 	dm_info->vht_err_cnt = 0;  in rtw8723d_false_alarm_statistics()
664 	dm_info->vht_ok_cnt = 0;  in rtw8723d_false_alarm_statistics()
673 	rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 0);  in rtw8723d_false_alarm_statistics()
675 	rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 0);  in rtw8723d_false_alarm_statistics()
676 	rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 0);  in rtw8723d_false_alarm_statistics()
677 	rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 0);  in rtw8723d_false_alarm_statistics()
678 	rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 0);  in rtw8723d_false_alarm_statistics()
680 	rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 0);  in rtw8723d_false_alarm_statistics()
683 	rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 0);  in rtw8723d_false_alarm_statistics()
687 	0x85c, 0xe6c, 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c,
688 	0xed0, 0xed4, 0xed8, 0xedc, 0xee0, 0xeec
691 static const u32 iqk_mac8_regs[] = {0x522, 0x550, 0x551};
692 static const u32 iqk_mac32_regs[] = {0x40};
695 	0xc04, 0xc08, 0x874, 0xb68, 0xb6c, 0x870, 0x860, 0x864, 0xa04
724 	for (i = 0; i < IQK_ADDA_REG_NUM; i++)  in rtw8723d_iqk_backup_regs()
727 	for (i = 0; i < IQK_MAC8_REG_NUM; i++)  in rtw8723d_iqk_backup_regs()
729 	for (i = 0; i < IQK_MAC32_REG_NUM; i++)  in rtw8723d_iqk_backup_regs()
732 	for (i = 0; i < IQK_BB_REG_NUM; i++)  in rtw8723d_iqk_backup_regs()
746 	for (i = 0; i < IQK_ADDA_REG_NUM; i++)  in rtw8723d_iqk_restore_regs()
749 	for (i = 0; i < IQK_MAC8_REG_NUM; i++)  in rtw8723d_iqk_restore_regs()
751 	for (i = 0; i < IQK_MAC32_REG_NUM; i++)  in rtw8723d_iqk_restore_regs()
754 	for (i = 0; i < IQK_BB_REG_NUM; i++)  in rtw8723d_iqk_restore_regs()
757 	rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50);  in rtw8723d_iqk_restore_regs()
760 	rtw_write32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0, 0x50);  in rtw8723d_iqk_restore_regs()
763 	rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x01008c00);  in rtw8723d_iqk_restore_regs()
764 	rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x01008c00);  in rtw8723d_iqk_restore_regs()
771 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] original 0x67 = 0x%x\n",  in rtw8723d_iqk_backup_path_ctrl()
777 	rtw_write32_mask(rtwdev, REG_PAD_CTRL1, BIT_BT_BTG_SEL, 0x1);  in rtw8723d_iqk_config_path_ctrl()
778 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] set 0x67 = 0x%x\n",  in rtw8723d_iqk_config_path_ctrl()
786 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] restore 0x67 = 0x%x\n",  in rtw8723d_iqk_restore_path_ctrl()
794 	rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0x800f0038);  in rtw8723d_iqk_backup_lte_path_gnt()
797 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] OriginalGNT = 0x%x\n",  in rtw8723d_iqk_backup_lte_path_gnt()
803 	rtw_write32(rtwdev, REG_LTECOEX_WRITE_DATA, 0x0000ff00);  in rtw8723d_iqk_config_lte_path_gnt()
804 	rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0xc0020038);  in rtw8723d_iqk_config_lte_path_gnt()
805 	rtw_write32_mask(rtwdev, REG_LTECOEX_PATH_CONTROL, BIT_LTE_MUX_CTRL_PATH, 0x1);  in rtw8723d_iqk_config_lte_path_gnt()
812 	rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0xc00f0038);  in rtw8723d_iqk_restore_lte_path_gnt()
832 		.val_bb_sel_btg = 0x99000000,
834 		.val_txiqk_pi = 0x8214019f,
838 		.val_wlint = 0xe0d,
839 		.val_wlsel = 0x60d,
840 		.val_iqkpts = 0xfa000000,
844 		.val_bb_sel_btg = 0x99000280,
846 		.val_txiqk_pi = 0x8214018a,
850 		.val_wlint = 0xe6d,
851 		.val_wlsel = 0x66d,
852 		.val_iqkpts = 0xf9000000,
862 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xeac = 0x%x\n",  in rtw8723d_iqk_check_tx_failed()
864 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe94 = 0x%x, 0xe9c = 0x%x\n",  in rtw8723d_iqk_check_tx_failed()
868 		"[IQK] 0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n",  in rtw8723d_iqk_check_tx_failed()
869 		rtw_read32(rtwdev, 0xe90),  in rtw8723d_iqk_check_tx_failed()
870 		rtw_read32(rtwdev, 0xe98));  in rtw8723d_iqk_check_tx_failed()
882 	return 0;  in rtw8723d_iqk_check_tx_failed()
891 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xea4 = 0x%x, 0xeac = 0x%x\n",  in rtw8723d_iqk_check_rx_failed()
896 		"[IQK] 0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n",  in rtw8723d_iqk_check_rx_failed()
897 		rtw_read32(rtwdev, 0xea0),  in rtw8723d_iqk_check_rx_failed()
898 		rtw_read32(rtwdev, 0xea8));  in rtw8723d_iqk_check_rx_failed()
912 	return 0;  in rtw8723d_iqk_check_rx_failed()
918 	u32 pts = (tx ? iqk_cfg->val_iqkpts : 0xf9000000);  in rtw8723d_iqk_one_shot()
924 	rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0x800f0054);  in rtw8723d_iqk_one_shot()
926 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] GNT_BT @%s %sIQK1 = 0x%x\n",  in rtw8723d_iqk_one_shot()
929 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x948 @%s %sIQK1 = 0x%x\n",  in rtw8723d_iqk_one_shot()
935 	rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf8000000);  in rtw8723d_iqk_one_shot()
952 	rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x0);  in rtw8723d_iqk_txrx_path_post()
953 	rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, BIT(0), 0x0);  in rtw8723d_iqk_txrx_path_post()
954 	rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, BIT(0), 0x0);  in rtw8723d_iqk_txrx_path_post()
964 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s TXIQK = 0x%x\n",  in rtw8723d_iqk_tx_path()
971 	rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x80000);  in rtw8723d_iqk_tx_path()
972 	rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00004);  in rtw8723d_iqk_tx_path()
973 	rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005d);  in rtw8723d_iqk_tx_path()
974 	rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xBFFE0);  in rtw8723d_iqk_tx_path()
975 	rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000);  in rtw8723d_iqk_tx_path()
978 	rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x08008c0c);  in rtw8723d_iqk_tx_path()
979 	rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c);  in rtw8723d_iqk_tx_path()
981 	rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160200);  in rtw8723d_iqk_tx_path()
982 	rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00);  in rtw8723d_iqk_tx_path()
983 	rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);  in rtw8723d_iqk_tx_path()
986 	rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x00462911);  in rtw8723d_iqk_tx_path()
989 	rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x1);  in rtw8723d_iqk_tx_path()
990 	rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x600, 0x0);  in rtw8723d_iqk_tx_path()
991 	rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x1E0, 0x3);  in rtw8723d_iqk_tx_path()
992 	rtw_write_rf(rtwdev, RF_PATH_A, RF_RXIQGEN, 0x1F, 0xf);  in rtw8723d_iqk_tx_path()
995 	rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, 0x10, 0x1);  in rtw8723d_iqk_tx_path()
996 	rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_bspad, 0x1, 0x1);  in rtw8723d_iqk_tx_path()
1001 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1 @%s TXIQK = 0x%x\n",  in rtw8723d_iqk_tx_path()
1004 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2 @%s TXIQK = 0x%x\n",  in rtw8723d_iqk_tx_path()
1025 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s RXIQK1 = 0x%x\n",  in rtw8723d_iqk_rx_path()
1033 	rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00);  in rtw8723d_iqk_rx_path()
1034 	rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);  in rtw8723d_iqk_rx_path()
1037 	rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c);  in rtw8723d_iqk_rx_path()
1038 	rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c);  in rtw8723d_iqk_rx_path()
1039 	rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c);  in rtw8723d_iqk_rx_path()
1040 	rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c);  in rtw8723d_iqk_rx_path()
1041 	rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82160000);  in rtw8723d_iqk_rx_path()
1042 	rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160000);  in rtw8723d_iqk_rx_path()
1045 	rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a911);  in rtw8723d_iqk_rx_path()
1048 	rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x80000);  in rtw8723d_iqk_rx_path()
1049 	rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00006);  in rtw8723d_iqk_rx_path()
1050 	rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005f);  in rtw8723d_iqk_rx_path()
1051 	rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xa7ffb);  in rtw8723d_iqk_rx_path()
1052 	rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000);  in rtw8723d_iqk_rx_path()
1054 	/* PA/PAD=0 */  in rtw8723d_iqk_rx_path()
1055 	rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x1);  in rtw8723d_iqk_rx_path()
1056 	rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x600, 0x0);  in rtw8723d_iqk_rx_path()
1060 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1@ path %s RXIQK1 = 0x%x\n",  in rtw8723d_iqk_rx_path()
1063 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2@ path %s RXIQK1 = 0x%x\n",  in rtw8723d_iqk_rx_path()
1078 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe40 = 0x%x u4tmp = 0x%x\n",  in rtw8723d_iqk_rx_path()
1084 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s RXIQK2 = 0x%x\n",  in rtw8723d_iqk_rx_path()
1088 	rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);  in rtw8723d_iqk_rx_path()
1089 	rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x38008c1c);  in rtw8723d_iqk_rx_path()
1090 	rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x18008c1c);  in rtw8723d_iqk_rx_path()
1091 	rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c);  in rtw8723d_iqk_rx_path()
1092 	rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c);  in rtw8723d_iqk_rx_path()
1093 	rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82170000);  in rtw8723d_iqk_rx_path()
1094 	rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28171400);  in rtw8723d_iqk_rx_path()
1097 	rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a8d1);  in rtw8723d_iqk_rx_path()
1102 	rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, 0x80000, 0x1);  in rtw8723d_iqk_rx_path()
1103 	rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00007);  in rtw8723d_iqk_rx_path()
1104 	rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005f);  in rtw8723d_iqk_rx_path()
1105 	rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xb3fdb);  in rtw8723d_iqk_rx_path()
1106 	rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000);  in rtw8723d_iqk_rx_path()
1108 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1 @%s RXIQK2 = 0x%x\n",  in rtw8723d_iqk_rx_path()
1111 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2 @%s RXIQK2 = 0x%x\n",  in rtw8723d_iqk_rx_path()
1132 	if (result[IQK_S1_TX_X] == 0)  in rtw8723d_iqk_fill_s1_matrix()
1155 		"[IQK] X = 0x%x, TX1_A = 0x%x, oldval_1 0x%x\n",  in rtw8723d_iqk_fill_s1_matrix()
1158 		"[IQK] Y = 0x%x, TX1_C = 0x%x\n", y, tx1_c);  in rtw8723d_iqk_fill_s1_matrix()
1160 	if (result[IQK_S1_RX_X] == 0)  in rtw8723d_iqk_fill_s1_matrix()
1179 	if (result[IQK_S0_TX_X] == 0)  in rtw8723d_iqk_fill_s0_matrix()
1196 	if (result[IQK_S0_RX_X] == 0)  in rtw8723d_iqk_fill_s0_matrix()
1209 	for (i = 0; i < IQK_ADDA_REG_NUM; i++)  in rtw8723d_iqk_path_adda_on()
1210 		rtw_write32(rtwdev, iqk_adda_regs[i], 0x03c00016);  in rtw8723d_iqk_path_adda_on()
1215 	rtw_write8(rtwdev, REG_TXPAUSE, 0xff);  in rtw8723d_iqk_config_mac()
1226 	rtw_write_rf(rtwdev, path, RF_MODE, RFREG_MASK, 0x10000);  in rtw8723d_iqk_rf_standby()
1235 	u32 bitmap = 0;  in rtw8723d_iqk_similarity_cmp()
1241 	for (i = 0; i < IQK_NR; i++) {  in rtw8723d_iqk_similarity_cmp()
1251 			if (result[c1][i] + result[c1][i + 1] == 0)  in rtw8723d_iqk_similarity_cmp()
1253 			else if (result[c2][i] + result[c2][i + 1] == 0)  in rtw8723d_iqk_similarity_cmp()
1262 	if (bitmap != 0)  in rtw8723d_iqk_similarity_cmp()
1265 	for (i = 0; i < PATH_NR; i++) {  in rtw8723d_iqk_similarity_cmp()
1277 	for (i = 0; i < IQK_NR; i++) {  in rtw8723d_iqk_similarity_cmp()
1297 	rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00);  in rtw8723d_iqk_precfg_path()
1298 	rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);  in rtw8723d_iqk_precfg_path()
1318 	rtw_write32_mask(rtwdev, REG_CCK_ANT_SEL_11N, 0x0f000000, 0xf);  in rtw8723d_iqk_one_round()
1319 	rtw_write32(rtwdev, REG_BB_RX_PATH_11N, 0x03a05611);  in rtw8723d_iqk_one_round()
1320 	rtw_write32(rtwdev, REG_TRMUX_11N, 0x000800e4);  in rtw8723d_iqk_one_round()
1321 	rtw_write32(rtwdev, REG_BB_PWR_SAV1_11N, 0x25204200);  in rtw8723d_iqk_one_round()
1324 	for (i = 0; i < PATH_IQK_RETRY; i++) {  in rtw8723d_iqk_one_round()
1337 		result[t][IQK_S1_TX_X] = 0x100;  in rtw8723d_iqk_one_round()
1338 		result[t][IQK_S1_TX_Y] = 0x0;  in rtw8723d_iqk_one_round()
1341 	for (i = 0; i < PATH_IQK_RETRY; i++) {  in rtw8723d_iqk_one_round()
1354 		result[t][IQK_S1_RX_X] = 0x100;  in rtw8723d_iqk_one_round()
1355 		result[t][IQK_S1_RX_Y] = 0x0;  in rtw8723d_iqk_one_round()
1358 	if (s1_ok == 0x0)  in rtw8723d_iqk_one_round()
1363 	for (i = 0; i < PATH_IQK_RETRY; i++) {  in rtw8723d_iqk_one_round()
1376 		result[t][IQK_S0_TX_X] = 0x100;  in rtw8723d_iqk_one_round()
1377 		result[t][IQK_S0_TX_Y] = 0x0;  in rtw8723d_iqk_one_round()
1380 	for (i = 0; i < PATH_IQK_RETRY; i++) {  in rtw8723d_iqk_one_round()
1394 		result[t][IQK_S0_RX_X] = 0x100;  in rtw8723d_iqk_one_round()
1395 		result[t][IQK_S0_RX_Y] = 0x0;  in rtw8723d_iqk_one_round()
1398 	if (s0_ok == 0x0)  in rtw8723d_iqk_one_round()
1419 	memset(result, 0, sizeof(result));  in rtw8723d_phy_calibration()
1450 		s32 reg_tmp = 0;  in rtw8723d_phy_calibration()
1452 		for (i = 0; i < IQK_NR; i++)  in rtw8723d_phy_calibration()
1455 		if (reg_tmp != 0) {  in rtw8723d_phy_calibration()
1483 			result[i][0], result[i][1], result[i][2], result[i][3],  in rtw8723d_phy_calibration()
1488 		"[IQK]0xc80 = 0x%x 0xc94 = 0x%x 0xc14 = 0x%x 0xca0 = 0x%x\n",  in rtw8723d_phy_calibration()
1494 		"[IQK]0xcd0 = 0x%x 0xcd4 = 0x%x 0xcd8 = 0x%x\n",  in rtw8723d_phy_calibration()
1517 		"is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x, cck_fa_avg=%d\n",  in rtw8723d_phy_cck_pd_set()
1525 	rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]);  in rtw8723d_phy_cck_pd_set()
1526 	rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000,  in rtw8723d_phy_cck_pd_set()
1537 	/* 0x790[5:0]=0x5 */  in rtw8723d_coex_cfg_init()
1538 	rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);  in rtw8723d_coex_cfg_init()
1541 	rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1);  in rtw8723d_coex_cfg_init()
1557 	rtw_write8_mask(rtwdev, REG_LEDCFG2, BIT(6), 0);  in rtw8723d_coex_cfg_gnt_debug()
1558 	rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(0), 0);  in rtw8723d_coex_cfg_gnt_debug()
1559 	rtw_write8_mask(rtwdev, REG_GPIO_INTM + 2, BIT(4), 0);  in rtw8723d_coex_cfg_gnt_debug()
1560 	rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT(1), 0);  in rtw8723d_coex_cfg_gnt_debug()
1561 	rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(1), 0);  in rtw8723d_coex_cfg_gnt_debug()
1562 	rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT(7), 0);  in rtw8723d_coex_cfg_gnt_debug()
1563 	rtw_write8_mask(rtwdev, REG_SYS_CLKR + 1, BIT(1), 0);  in rtw8723d_coex_cfg_gnt_debug()
1564 	rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT(3), 0);  in rtw8723d_coex_cfg_gnt_debug()
1575 	coex_rfe->ant_switch_polarity = 0;  in rtw8723d_coex_cfg_rfe_type()
1584 			rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x80);  in rtw8723d_coex_cfg_rfe_type()
1586 			rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x200);  in rtw8723d_coex_cfg_rfe_type()
1589 			rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x280);  in rtw8723d_coex_cfg_rfe_type()
1591 			rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x0);  in rtw8723d_coex_cfg_rfe_type()
1595 	rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0);  in rtw8723d_coex_cfg_rfe_type()
1596 	rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);  in rtw8723d_coex_cfg_rfe_type()
1597 	rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);  in rtw8723d_coex_cfg_rfe_type()
1604 	static const u8	wl_tx_power[] = {0xb2, 0x90};  in rtw8723d_coex_cfg_wl_tx_power()
1626 		0xec120101, 0xeb130101, 0xce140101, 0xcd150101, 0xcc160101,  in rtw8723d_coex_cfg_wl_rx_gain()
1627 		0xcb170101, 0xca180101, 0x8d190101, 0x8c1a0101, 0x8b1b0101,  in rtw8723d_coex_cfg_wl_rx_gain()
1628 		0x4f1c0101, 0x4e1d0101, 0x4d1e0101, 0x4c1f0101, 0x0e200101,  in rtw8723d_coex_cfg_wl_rx_gain()
1629 		0x0d210101, 0x0c220101, 0x0b230101, 0xcf240001, 0xce250001,  in rtw8723d_coex_cfg_wl_rx_gain()
1630 		0xcd260001, 0xcc270001, 0x8f280001  in rtw8723d_coex_cfg_wl_rx_gain()
1634 		0xec120101, 0xeb130101, 0xea140101, 0xe9150101, 0xe8160101,  in rtw8723d_coex_cfg_wl_rx_gain()
1635 		0xe7170101, 0xe6180101, 0xe5190101, 0xe41a0101, 0xe31b0101,  in rtw8723d_coex_cfg_wl_rx_gain()
1636 		0xe21c0101, 0xe11d0101, 0xe01e0101, 0x861f0101, 0x85200101,  in rtw8723d_coex_cfg_wl_rx_gain()
1637 		0x84210101, 0x83220101, 0x82230101, 0x81240101, 0x80250101,  in rtw8723d_coex_cfg_wl_rx_gain()
1638 		0x44260101, 0x43270101, 0x42280101  in rtw8723d_coex_cfg_wl_rx_gain()
1648 		for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_on); i++)  in rtw8723d_coex_cfg_wl_rx_gain()
1651 		for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_off); i++)  in rtw8723d_coex_cfg_wl_rx_gain()
1682 		rtw_warn(rtwdev, "pwrtrack unhandled tx_rate 0x%x\n", tx_rate);  in rtw8723d_pwrtrack_get_limit_ofdm()
1724 		/* write new elements A, C, D, and element B is always 0 */  in rtw8723d_set_iqk_matrix_by_result()
1737 		/* write new elements A, C, D, and element B is always 0 */  in rtw8723d_set_iqk_matrix_by_result()
1761 	else if (ofdm_index < 0)  in rtw8723d_set_iqk_matrix()
1762 		ofdm_index = 0;  in rtw8723d_set_iqk_matrix()
1776 				 0x00);  in rtw8723d_set_iqk_matrix()
1792 		rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_EXT_S0, 0x0);  in rtw8723d_set_iqk_matrix()
1793 		rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, 0x0);  in rtw8723d_set_iqk_matrix()
1794 		rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, 0x0);  in rtw8723d_set_iqk_matrix()
1817 	rtw_write32_mask(rtwdev, 0xab4, 0x000007FF,  in rtw8723d_pwrtrack_set_cck_pwr()
1840 	else if (final_ofdm_swing_index < 0)  in rtw8723d_pwrtrack_set()
1841 		rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, 0,  in rtw8723d_pwrtrack_set()
1844 		rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, final_ofdm_swing_index, 0);  in rtw8723d_pwrtrack_set()
1849 	else if (final_cck_swing_index < 0)  in rtw8723d_pwrtrack_set()
1850 		rtw8723d_pwrtrack_set_cck_pwr(rtwdev, 0,  in rtw8723d_pwrtrack_set()
1853 		rtw8723d_pwrtrack_set_cck_pwr(rtwdev, final_cck_swing_index, 0);  in rtw8723d_pwrtrack_set()
1872 	xtal_cap = rtwdev->efuse.crystal_cap & 0x3F;  in rtw8723d_pwrtrack_set_xtal()
1873 	xtal_cap = clamp_t(s8, xtal_cap + pwrtrk_xtal[delta], 0, 0x3F);  in rtw8723d_pwrtrack_set_xtal()
1887 	if (rtwdev->efuse.thermal_meter[0] == 0xff)  in rtw8723d_phy_pwrtrack()
1890 	thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00);  in rtw8723d_phy_pwrtrack()
1909 	for (path = 0; path < rtwdev->hal.rf_path_num; path++) {  in rtw8723d_phy_pwrtrack()
1934 	if (efuse->power_track_type != 0)  in rtw8723d_pwr_track()
1939 			     GENMASK(17, 16), 0x03);  in rtw8723d_pwr_track()
1980 	{0xffffffff, 0xffffffff}, /* case-0 */
1981 	{0x55555555, 0x55555555},
1982 	{0x66555555, 0x66555555},
1983 	{0xaaaaaaaa, 0xaaaaaaaa},
1984 	{0x5a5a5a5a, 0x5a5a5a5a},
1985 	{0xfafafafa, 0xfafafafa}, /* case-5 */
1986 	{0x6a5a5555, 0xaaaaaaaa},
1987 	{0x6a5a56aa, 0x6a5a56aa},
1988 	{0x6a5a5a5a, 0x6a5a5a5a},
1989 	{0x66555555, 0x5a5a5a5a},
1990 	{0x66555555, 0x6a5a5a5a}, /* case-10 */
1991 	{0x66555555, 0x6a5a5aaa},
1992 	{0x66555555, 0x5a5a5aaa},
1993 	{0x66555555, 0x6aaa5aaa},
1994 	{0x66555555, 0xaaaa5aaa},
1995 	{0x66555555, 0xaaaaaaaa}, /* case-15 */
1996 	{0xffff55ff, 0xfafafafa},
1997 	{0xffff55ff, 0x6afa5afa},
1998 	{0xaaffffaa, 0xfafafafa},
1999 	{0xaa5555aa, 0x5a5a5a5a},
2000 	{0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
2001 	{0xaa5555aa, 0xaaaaaaaa},
2002 	{0xffffffff, 0x5a5a5a5a},
2003 	{0xffffffff, 0x5a5a5a5a},
2004 	{0xffffffff, 0x55555555},
2005 	{0xffffffff, 0x5a5a5aaa}, /* case-25 */
2006 	{0x55555555, 0x5a5a5a5a},
2007 	{0x55555555, 0xaaaaaaaa},
2008 	{0x55555555, 0x6a5a6a5a},
2009 	{0x66556655, 0x66556655},
2010 	{0x66556aaa, 0x6a5a6aaa}, /* case-30 */
2011 	{0xffffffff, 0x5aaa5aaa},
2012 	{0x56555555, 0x5a5a5aaa},
2017 	{0xffffffff, 0xffffffff}, /* case-100 */
2018 	{0x55555555, 0x55555555},
2019 	{0x66555555, 0x66555555},
2020 	{0xaaaaaaaa, 0xaaaaaaaa},
2021 	{0x5a5a5a5a, 0x5a5a5a5a},
2022 	{0xfafafafa, 0xfafafafa}, /* case-105 */
2023 	{0x5afa5afa, 0x5afa5afa},
2024 	{0x55555555, 0xfafafafa},
2025 	{0x66555555, 0xfafafafa},
2026 	{0x66555555, 0x5a5a5a5a},
2027 	{0x66555555, 0x6a5a5a5a}, /* case-110 */
2028 	{0x66555555, 0xaaaaaaaa},
2029 	{0xffff55ff, 0xfafafafa},
2030 	{0xffff55ff, 0x5afa5afa},
2031 	{0xffff55ff, 0xaaaaaaaa},
2032 	{0xffff55ff, 0xffff55ff}, /* case-115 */
2033 	{0xaaffffaa, 0x5afa5afa},
2034 	{0xaaffffaa, 0xaaaaaaaa},
2035 	{0xffffffff, 0xfafafafa},
2036 	{0xffffffff, 0x5afa5afa},
2037 	{0xffffffff, 0xaaaaaaaa}, /* case-120 */
2038 	{0x55ff55ff, 0x5afa5afa},
2039 	{0x55ff55ff, 0xaaaaaaaa},
2040 	{0x55ff55ff, 0x55ff55ff}
2045 	{ {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
2046 	{ {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
2047 	{ {0x61, 0x3a, 0x03, 0x11, 0x11} },
2048 	{ {0x61, 0x30, 0x03, 0x11, 0x11} },
2049 	{ {0x61, 0x20, 0x03, 0x11, 0x11} },
2050 	{ {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
2051 	{ {0x61, 0x45, 0x03, 0x11, 0x10} },
2052 	{ {0x61, 0x3a, 0x03, 0x11, 0x10} },
2053 	{ {0x61, 0x30, 0x03, 0x11, 0x10} },
2054 	{ {0x61, 0x20, 0x03, 0x11, 0x10} },
2055 	{ {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
2056 	{ {0x61, 0x08, 0x03, 0x11, 0x14} },
2057 	{ {0x61, 0x08, 0x03, 0x10, 0x14} },
2058 	{ {0x51, 0x08, 0x03, 0x10, 0x54} },
2059 	{ {0x51, 0x08, 0x03, 0x10, 0x55} },
2060 	{ {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
2061 	{ {0x51, 0x45, 0x03, 0x10, 0x50} },
2062 	{ {0x51, 0x3a, 0x03, 0x10, 0x50} },
2063 	{ {0x51, 0x30, 0x03, 0x10, 0x50} },
2064 	{ {0x51, 0x20, 0x03, 0x10, 0x50} },
2065 	{ {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
2066 	{ {0x51, 0x4a, 0x03, 0x10, 0x50} },
2067 	{ {0x51, 0x0c, 0x03, 0x10, 0x54} },
2068 	{ {0x55, 0x08, 0x03, 0x10, 0x54} },
2069 	{ {0x65, 0x10, 0x03, 0x11, 0x10} },
2070 	{ {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
2071 	{ {0x51, 0x08, 0x03, 0x10, 0x50} },
2072 	{ {0x61, 0x08, 0x03, 0x11, 0x11} }
2077 	{ {0x00, 0x00, 0x00, 0x00, 0x01} }, /* case-100 */
2078 	{ {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-101 */
2079 	{ {0x61, 0x3a, 0x03, 0x11, 0x11} },
2080 	{ {0x61, 0x30, 0x03, 0x11, 0x11} },
2081 	{ {0x61, 0x20, 0x03, 0x11, 0x11} },
2082 	{ {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
2083 	{ {0x61, 0x45, 0x03, 0x11, 0x10} },
2084 	{ {0x61, 0x3a, 0x03, 0x11, 0x10} },
2085 	{ {0x61, 0x30, 0x03, 0x11, 0x10} },
2086 	{ {0x61, 0x20, 0x03, 0x11, 0x10} },
2087 	{ {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
2088 	{ {0x61, 0x08, 0x03, 0x11, 0x14} },
2089 	{ {0x61, 0x08, 0x03, 0x10, 0x14} },
2090 	{ {0x51, 0x08, 0x03, 0x10, 0x54} },
2091 	{ {0x51, 0x08, 0x03, 0x10, 0x55} },
2092 	{ {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
2093 	{ {0x51, 0x45, 0x03, 0x10, 0x50} },
2094 	{ {0x51, 0x3a, 0x03, 0x10, 0x50} },
2095 	{ {0x51, 0x30, 0x03, 0x10, 0x50} },
2096 	{ {0x51, 0x20, 0x03, 0x10, 0x50} },
2097 	{ {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */
2098 	{ {0x51, 0x08, 0x03, 0x10, 0x50} }
2104 static const struct coex_5g_afh_map afh_5g_8723d[] = { {0, 0, 0} };
2112 	{0, 0, false, 7},  /* for normal */
2113 	{0, 10, false, 7}, /* for WL-CPT */
2114 	{1, 0, true, 4},
2121 	{0, 0, false, 7},  /* for normal */
2122 	{0, 10, false, 7}, /* for WL-CPT */
2123 	{1, 0, true, 5},
2130 	{0x0005,
2134 	 RTW_PWR_CMD_WRITE, BIT(3) | BIT(7), 0},
2135 	{0x0086,
2139 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
2140 	{0x0086,
2145 	{0x004A,
2149 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
2150 	{0x0005,
2154 	 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
2155 	{0x0023,
2159 	 RTW_PWR_CMD_WRITE, BIT(4), 0},
2160 	{0x0301,
2164 	 RTW_PWR_CMD_WRITE, 0xFF, 0},
2165 	{0xFFFF,
2168 	 0,
2169 	 RTW_PWR_CMD_END, 0, 0},
2173 	{0x0020,
2177 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
2178 	{0x0001,
2183 	{0x0000,
2187 	 RTW_PWR_CMD_WRITE, BIT(5), 0},
2188 	{0x0005,
2192 	 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
2193 	{0x0075,
2197 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
2198 	{0x0006,
2203 	{0x0075,
2207 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
2208 	{0x0006,
2212 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
2213 	{0x0005,
2217 	 RTW_PWR_CMD_POLLING, (BIT(1) | BIT(0)), 0},
2218 	{0x0005,
2222 	 RTW_PWR_CMD_WRITE, BIT(7), 0},
2223 	{0x0005,
2227 	 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
2228 	{0x0005,
2232 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
2233 	{0x0005,
2237 	 RTW_PWR_CMD_POLLING, BIT(0), 0},
2238 	{0x0010,
2243 	{0x0049,
2248 	{0x0063,
2253 	{0x0062,
2257 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
2258 	{0x0058,
2262 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
2263 	{0x005A,
2268 	{0x0068,
2273 	{0x0069,
2278 	{0x001f,
2282 	 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
2283 	{0x0077,
2287 	 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
2288 	{0x001f,
2292 	 RTW_PWR_CMD_WRITE, 0xFF, 0x07},
2293 	{0x0077,
2297 	 RTW_PWR_CMD_WRITE, 0xFF, 0x07},
2298 	{0xFFFF,
2301 	 0,
2302 	 RTW_PWR_CMD_END, 0, 0},
2312 	{0x0301,
2316 	 RTW_PWR_CMD_WRITE, 0xFF, 0xFF},
2317 	{0x0522,
2321 	 RTW_PWR_CMD_WRITE, 0xFF, 0xFF},
2322 	{0x05F8,
2326 	 RTW_PWR_CMD_POLLING, 0xFF, 0},
2327 	{0x05F9,
2331 	 RTW_PWR_CMD_POLLING, 0xFF, 0},
2332 	{0x05FA,
2336 	 RTW_PWR_CMD_POLLING, 0xFF, 0},
2337 	{0x05FB,
2341 	 RTW_PWR_CMD_POLLING, 0xFF, 0},
2342 	{0x0002,
2346 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
2347 	{0x0002,
2351 	 RTW_PWR_CMD_DELAY, 0, RTW_PWR_DELAY_US},
2352 	{0x0002,
2356 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
2357 	{0x0100,
2361 	 RTW_PWR_CMD_WRITE, 0xFF, 0x03},
2362 	{0x0101,
2366 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
2367 	{0x0093,
2371 	 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
2372 	{0x0553,
2377 	{0xFFFF,
2380 	 0,
2381 	 RTW_PWR_CMD_END, 0, 0},
2385 	{0x0003,
2389 	 RTW_PWR_CMD_WRITE, BIT(2), 0},
2390 	{0x0080,
2394 	 RTW_PWR_CMD_WRITE, 0xFF, 0},
2395 	{0xFFFF,
2398 	 0,
2399 	 RTW_PWR_CMD_END, 0, 0},
2403 	{0x0002,
2407 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
2408 	{0x0049,
2412 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
2413 	{0x0006,
2417 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
2418 	{0x0005,
2423 	{0x0005,
2427 	 RTW_PWR_CMD_POLLING, BIT(1), 0},
2428 	{0x0010,
2432 	 RTW_PWR_CMD_WRITE, BIT(6), 0},
2433 	{0x0000,
2438 	{0x0020,
2442 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
2443 	{0xFFFF,
2446 	 0,
2447 	 RTW_PWR_CMD_END, 0, 0},
2451 	{0x0007,
2455 	 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
2456 	{0x0005,
2461 	{0x0005,
2466 	{0x0005,
2471 	{0x004A,
2475 	 RTW_PWR_CMD_WRITE, BIT(0), 1},
2476 	{0x0023,
2481 	{0x0086,
2485 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
2486 	{0x0086,
2490 	 RTW_PWR_CMD_POLLING, BIT(1), 0},
2491 	{0xFFFF,
2494 	 0,
2495 	 RTW_PWR_CMD_END, 0, 0},
2499 	{0x001D,
2503 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
2504 	{0x001D,
2508 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
2509 	{0x001C,
2513 	 RTW_PWR_CMD_WRITE, 0xFF, 0x0E},
2514 	{0xFFFF,
2517 	 0,
2518 	 RTW_PWR_CMD_END, 0, 0},
2531 	{12, 2, 2, 0, 1},
2532 	{12, 2, 2, 0, 1},
2533 	{12, 2, 2, 0, 1},
2534 	{12, 2, 2, 0, 1},
2535 	{12, 2, 2, 0, 1},
2573 	{0x0008, 0x4a22,
2577 	{0x0009, 0x1000,
2581 	{0xFFFF, 0x0000,
2593 	[0] = { .addr = 0xc50, .mask = 0x7f },
2594 	[1] = { .addr = 0xc50, .mask = 0x7f },
2598 	[0] = { .addr = 0xa0c, .mask = 0x3f00 },
2602 	[RF_PATH_A] = { .hssi_1 = 0x820, .lssi_read    = 0x8a0,
2603 			.hssi_2 = 0x824, .lssi_read_pi = 0x8b8},
2604 	[RF_PATH_B] = { .hssi_1 = 0x828, .lssi_read    = 0x8a4,
2605 			.hssi_2 = 0x82c, .lssi_read_pi = 0x8bc},
2615 	[0] = { .phy_pg_tbl	= &rtw8723d_bb_pg_tbl,
2620 	0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5,
2625 	0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7,
2630 	0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5,
2635 	0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7,
2640 	0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6,
2645 	0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7,
2650 	0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6,
2655 	0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7,
2660 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2661 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
2665 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2666 	0, -10, -12, -14, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16
2683 	{0x948, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2684 	{0x67, BIT(7), RTW_REG_DOMAIN_MAC8},
2685 	{0, 0, RTW_REG_DOMAIN_NL},
2686 	{0x964, BIT(1), RTW_REG_DOMAIN_MAC8},
2687 	{0x864, BIT(0), RTW_REG_DOMAIN_MAC8},
2688 	{0xab7, BIT(5), RTW_REG_DOMAIN_MAC8},
2689 	{0xa01, BIT(7), RTW_REG_DOMAIN_MAC8},
2690 	{0, 0, RTW_REG_DOMAIN_NL},
2691 	{0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2692 	{0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2693 	{0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
2694 	{0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2695 	{0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
2696 	{0, 0, RTW_REG_DOMAIN_NL},
2697 	{0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
2698 	{0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
2699 	{0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2700 	{0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2701 	{0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
2720 	.max_power_index = 0x3f,
2721 	.csi_buf_pg_num = 0,
2724 	.dig_min = 0x20,
2727 	.lps_deep_mode_supported = 0,
2728 	.sys_func_en = 0xFD,
2737 	.rf_sipi_addr = {0x840, 0x844},
2753 	.coex_para_ver = 0x2007022f,
2754 	.bt_desired_ver = 0x2f,
2776 	.bt_afh_span_bw20 = 0x20,
2777 	.bt_afh_span_bw40 = 0x30,