Lines Matching refs:rt2x00_set_field32
94 rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value); in rt2800_bbp_write()
95 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); in rt2800_bbp_write()
96 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); in rt2800_bbp_write()
97 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0); in rt2800_bbp_write()
98 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); in rt2800_bbp_write()
123 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); in rt2800_bbp_read()
124 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); in rt2800_bbp_read()
125 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1); in rt2800_bbp_read()
126 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); in rt2800_bbp_read()
155 rt2x00_set_field32(®, RF_CSR_CFG_DATA_MT7620, value); in rt2800_rfcsr_write()
156 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, in rt2800_rfcsr_write()
158 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 1); in rt2800_rfcsr_write()
159 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); in rt2800_rfcsr_write()
168 rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); in rt2800_rfcsr_write()
169 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); in rt2800_rfcsr_write()
170 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); in rt2800_rfcsr_write()
171 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); in rt2800_rfcsr_write()
241 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, in rt2800_rfcsr_read()
243 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 0); in rt2800_rfcsr_read()
244 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); in rt2800_rfcsr_read()
257 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); in rt2800_rfcsr_read()
258 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); in rt2800_rfcsr_read()
259 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); in rt2800_rfcsr_read()
294 rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value); in rt2800_rf_write()
295 rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0); in rt2800_rf_write()
296 rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0); in rt2800_rf_write()
297 rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1); in rt2800_rf_write()
461 rt2x00_set_field32(®, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff); in rt2800_enable_wlan_rt3290()
462 rt2x00_set_field32(®, FRC_WL_ANT_SET, 1); in rt2800_enable_wlan_rt3290()
463 rt2x00_set_field32(®, WLAN_CLK_EN, 0); in rt2800_enable_wlan_rt3290()
464 rt2x00_set_field32(®, WLAN_EN, 1); in rt2800_enable_wlan_rt3290()
499 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 0); in rt2800_enable_wlan_rt3290()
500 rt2x00_set_field32(®, WLAN_CLK_EN, 1); in rt2800_enable_wlan_rt3290()
501 rt2x00_set_field32(®, WLAN_RESET, 1); in rt2800_enable_wlan_rt3290()
504 rt2x00_set_field32(®, WLAN_RESET, 0); in rt2800_enable_wlan_rt3290()
532 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); in rt2800_mcu_request()
533 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); in rt2800_mcu_request()
534 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); in rt2800_mcu_request()
535 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); in rt2800_mcu_request()
539 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); in rt2800_mcu_request()
592 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); in rt2800_disable_wpdma()
593 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); in rt2800_disable_wpdma()
594 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); in rt2800_disable_wpdma()
595 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); in rt2800_disable_wpdma()
596 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); in rt2800_disable_wpdma()
743 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); in rt2800_load_firmware()
744 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); in rt2800_load_firmware()
804 rt2x00_set_field32(&word, TXWI_W0_FRAG, in rt2800_write_tx_data()
806 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, in rt2800_write_tx_data()
808 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0); in rt2800_write_tx_data()
809 rt2x00_set_field32(&word, TXWI_W0_TS, in rt2800_write_tx_data()
811 rt2x00_set_field32(&word, TXWI_W0_AMPDU, in rt2800_write_tx_data()
813 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, in rt2800_write_tx_data()
815 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop); in rt2800_write_tx_data()
816 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs); in rt2800_write_tx_data()
817 rt2x00_set_field32(&word, TXWI_W0_BW, in rt2800_write_tx_data()
819 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI, in rt2800_write_tx_data()
821 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc); in rt2800_write_tx_data()
822 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode); in rt2800_write_tx_data()
826 rt2x00_set_field32(&word, TXWI_W1_ACK, in rt2800_write_tx_data()
828 rt2x00_set_field32(&word, TXWI_W1_NSEQ, in rt2800_write_tx_data()
830 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size); in rt2800_write_tx_data()
831 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, in rt2800_write_tx_data()
834 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, in rt2800_write_tx_data()
836 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid); in rt2800_write_tx_data()
837 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1); in rt2800_write_tx_data()
1348 rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM, in rt2800_update_beacons_setup()
1368 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); in rt2800_write_beacon()
1458 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); in rt2800_clear_beacon()
1560 rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity); in rt2800_brightness_set()
1564 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, in rt2800_brightness_set()
1567 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, in rt2800_brightness_set()
1570 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, in rt2800_brightness_set()
1647 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7)); in rt2800_config_wcid_attr_bssidx()
1648 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, in rt2800_config_wcid_attr_bssidx()
1665 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, in rt2800_config_wcid_attr_cipher()
1672 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, in rt2800_config_wcid_attr_cipher()
1674 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, in rt2800_config_wcid_attr_cipher()
1676 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); in rt2800_config_wcid_attr_cipher()
1681 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0); in rt2800_config_wcid_attr_cipher()
1682 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0); in rt2800_config_wcid_attr_cipher()
1683 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0); in rt2800_config_wcid_attr_cipher()
1684 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0); in rt2800_config_wcid_attr_cipher()
1740 rt2x00_set_field32(®, field, in rt2800_config_shared_key()
1806 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, max_psdu); in rt2800_set_max_psdu_len()
1920 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, in rt2800_config_filter()
1922 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, in rt2800_config_filter()
1924 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME, in rt2800_config_filter()
1926 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); in rt2800_config_filter()
1927 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1); in rt2800_config_filter()
1928 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST, in rt2800_config_filter()
1930 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0); in rt2800_config_filter()
1931 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1); in rt2800_config_filter()
1932 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK, in rt2800_config_filter()
1934 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END, in rt2800_config_filter()
1936 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK, in rt2800_config_filter()
1938 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS, in rt2800_config_filter()
1940 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS, in rt2800_config_filter()
1942 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL, in rt2800_config_filter()
1944 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 0); in rt2800_config_filter()
1945 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, in rt2800_config_filter()
1947 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL, in rt2800_config_filter()
1964 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); in rt2800_config_intf()
1972 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0); in rt2800_config_intf()
1973 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1); in rt2800_config_intf()
1974 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); in rt2800_config_intf()
1975 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0); in rt2800_config_intf()
1979 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4); in rt2800_config_intf()
1980 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2); in rt2800_config_intf()
1981 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); in rt2800_config_intf()
1982 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16); in rt2800_config_intf()
2000 rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); in rt2800_config_intf()
2011 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3); in rt2800_config_intf()
2012 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 0); in rt2800_config_intf()
2098 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate); in rt2800_config_ht_opmode()
2099 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode); in rt2800_config_ht_opmode()
2103 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate); in rt2800_config_ht_opmode()
2104 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode); in rt2800_config_ht_opmode()
2108 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate); in rt2800_config_ht_opmode()
2109 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode); in rt2800_config_ht_opmode()
2113 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate); in rt2800_config_ht_opmode()
2114 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode); in rt2800_config_ht_opmode()
2125 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, in rt2800_config_erp()
2132 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, in rt2800_config_erp()
2145 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, in rt2800_config_erp()
2150 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); in rt2800_config_erp()
2156 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, in rt2800_config_erp()
2216 rt2x00_set_field32(®, GPIO_SWITCH_0, 1); in rt2800_config_3572bt_ant()
2217 rt2x00_set_field32(®, GPIO_SWITCH_1, 1); in rt2800_config_3572bt_ant()
2219 rt2x00_set_field32(®, GPIO_SWITCH_0, 0); in rt2800_config_3572bt_ant()
2220 rt2x00_set_field32(®, GPIO_SWITCH_1, 0); in rt2800_config_3572bt_ant()
2232 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode); in rt2800_config_3572bt_ant()
2233 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode); in rt2800_config_3572bt_ant()
2251 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin); in rt2800_set_ant_diversity()
2258 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); in rt2800_set_ant_diversity()
2259 rt2x00_set_field32(®, GPIO_CTRL_VAL3, gpio_bit3); in rt2800_set_ant_diversity()
2428 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); in rt2800_config_channel_rf2xxx()
2431 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1); in rt2800_config_channel_rf2xxx()
2434 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1); in rt2800_config_channel_rf2xxx()
2435 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); in rt2800_config_channel_rf2xxx()
2437 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); in rt2800_config_channel_rf2xxx()
2446 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST, in rt2800_config_channel_rf2xxx()
2452 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1); in rt2800_config_channel_rf2xxx()
2454 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST, in rt2800_config_channel_rf2xxx()
2460 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2); in rt2800_config_channel_rf2xxx()
2462 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1); in rt2800_config_channel_rf2xxx()
2463 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2); in rt2800_config_channel_rf2xxx()
2466 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf)); in rt2800_config_channel_rf2xxx()
2726 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); in rt2800_config_channel_rf3052()
2728 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); in rt2800_config_channel_rf3052()
2730 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 0); in rt2800_config_channel_rf3052()
3440 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, in rt2800_config_channel_rf55xx()
3886 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, power_level); in rt2800_config_alc()
3887 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, power_level); in rt2800_config_alc()
3888 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_0, max_power); in rt2800_config_alc()
3889 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_1, max_power); in rt2800_config_alc()
3896 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, target_power); in rt2800_config_alc()
3897 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, target_power); in rt2800_config_alc()
3902 rt2x00_set_field32(®, TX_ALC_CFG_1_TX_TEMP_COMP, 0); in rt2800_config_alc()
4274 rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf)); in rt2800_config_channel()
4275 rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); in rt2800_config_channel()
4276 rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); in rt2800_config_channel()
4284 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1); in rt2800_config_channel()
4292 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, in rt2800_config_channel()
4294 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, in rt2800_config_channel()
4299 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, in rt2800_config_channel()
4301 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, in rt2800_config_channel()
4306 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, in rt2800_config_channel()
4309 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); in rt2800_config_channel()
4311 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, in rt2800_config_channel()
4319 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1); in rt2800_config_channel()
4320 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1); in rt2800_config_channel()
4324 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1); in rt2800_config_channel()
4325 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1); in rt2800_config_channel()
4329 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1); in rt2800_config_channel()
4330 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1); in rt2800_config_channel()
4334 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); in rt2800_config_channel()
4335 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); in rt2800_config_channel()
4358 rt2x00_set_field32(®, GPIO_CTRL_DIR8, 0); in rt2800_config_channel()
4360 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 1); in rt2800_config_channel()
4362 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 0); in rt2800_config_channel()
4370 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); in rt2800_config_channel()
4371 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); in rt2800_config_channel()
4373 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); in rt2800_config_channel()
4374 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); in rt2800_config_channel()
4377 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); in rt2800_config_channel()
4378 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); in rt2800_config_channel()
4801 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
4803 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
4805 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], in rt2800_config_txpower_rt3593()
4812 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
4814 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
4816 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], in rt2800_config_txpower_rt3593()
4823 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
4825 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
4827 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], in rt2800_config_txpower_rt3593()
4834 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
4836 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
4838 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], in rt2800_config_txpower_rt3593()
4849 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
4851 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
4853 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], in rt2800_config_txpower_rt3593()
4860 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
4862 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
4864 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], in rt2800_config_txpower_rt3593()
4871 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], in rt2800_config_txpower_rt3593()
4873 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], in rt2800_config_txpower_rt3593()
4875 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], in rt2800_config_txpower_rt3593()
4886 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
4888 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
4890 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], in rt2800_config_txpower_rt3593()
4897 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
4899 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
4901 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], in rt2800_config_txpower_rt3593()
4908 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
4910 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
4912 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], in rt2800_config_txpower_rt3593()
4919 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
4921 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
4923 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], in rt2800_config_txpower_rt3593()
4934 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], in rt2800_config_txpower_rt3593()
4936 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], in rt2800_config_txpower_rt3593()
4938 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], in rt2800_config_txpower_rt3593()
4945 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
4947 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
4949 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], in rt2800_config_txpower_rt3593()
4956 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
4958 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
4960 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], in rt2800_config_txpower_rt3593()
4967 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
4969 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
4971 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], in rt2800_config_txpower_rt3593()
4982 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
4984 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
4986 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], in rt2800_config_txpower_rt3593()
4993 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], in rt2800_config_txpower_rt3593()
4995 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], in rt2800_config_txpower_rt3593()
4997 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], in rt2800_config_txpower_rt3593()
5004 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], in rt2800_config_txpower_rt3593()
5006 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], in rt2800_config_txpower_rt3593()
5008 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], in rt2800_config_txpower_rt3593()
5015 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], in rt2800_config_txpower_rt3593()
5017 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], in rt2800_config_txpower_rt3593()
5019 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], in rt2800_config_txpower_rt3593()
5030 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], in rt2800_config_txpower_rt3593()
5032 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], in rt2800_config_txpower_rt3593()
5034 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], in rt2800_config_txpower_rt3593()
5041 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], in rt2800_config_txpower_rt3593()
5043 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], in rt2800_config_txpower_rt3593()
5045 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], in rt2800_config_txpower_rt3593()
5052 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], in rt2800_config_txpower_rt3593()
5054 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], in rt2800_config_txpower_rt3593()
5056 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], in rt2800_config_txpower_rt3593()
5067 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
5069 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
5071 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], in rt2800_config_txpower_rt3593()
5078 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
5080 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
5082 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], in rt2800_config_txpower_rt3593()
5089 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower); in rt2800_config_txpower_rt3593()
5090 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower); in rt2800_config_txpower_rt3593()
5091 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0, in rt2800_config_txpower_rt3593()
5098 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower); in rt2800_config_txpower_rt3593()
5099 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower); in rt2800_config_txpower_rt3593()
5100 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2, in rt2800_config_txpower_rt3593()
5111 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], in rt2800_config_txpower_rt3593()
5113 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], in rt2800_config_txpower_rt3593()
5115 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], in rt2800_config_txpower_rt3593()
5249 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t); in rt2800_config_txpower_rt6352()
5254 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t); in rt2800_config_txpower_rt6352()
5261 rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t); in rt2800_config_txpower_rt6352()
5268 rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t); in rt2800_config_txpower_rt6352()
5376 rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower); in rt2800_config_txpower_rt28xx()
5387 rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower); in rt2800_config_txpower_rt28xx()
5398 rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower); in rt2800_config_txpower_rt28xx()
5409 rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower); in rt2800_config_txpower_rt28xx()
5426 rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower); in rt2800_config_txpower_rt28xx()
5437 rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower); in rt2800_config_txpower_rt28xx()
5448 rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower); in rt2800_config_txpower_rt28xx()
5459 rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower); in rt2800_config_txpower_rt28xx()
5555 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1); in rt2800_vco_calibration()
5558 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1); in rt2800_vco_calibration()
5562 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); in rt2800_vco_calibration()
5568 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1); in rt2800_vco_calibration()
5571 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1); in rt2800_vco_calibration()
5575 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1); in rt2800_vco_calibration()
5626 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, in rt2800_config_retry_limit()
5628 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, in rt2800_config_retry_limit()
5645 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); in rt2800_config_ps()
5646 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, in rt2800_config_ps()
5648 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1); in rt2800_config_ps()
5654 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); in rt2800_config_ps()
5655 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); in rt2800_config_ps()
5656 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); in rt2800_config_ps()
5840 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600); in rt2800_init_registers()
5841 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); in rt2800_init_registers()
5842 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); in rt2800_init_registers()
5843 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); in rt2800_init_registers()
5844 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); in rt2800_init_registers()
5845 rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); in rt2800_init_registers()
5851 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9); in rt2800_init_registers()
5852 rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); in rt2800_init_registers()
5858 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 1); in rt2800_init_registers()
5864 rt2x00_set_field32(®, LDO0_EN, 1); in rt2800_init_registers()
5865 rt2x00_set_field32(®, LDO_BGSEL, 3); in rt2800_init_registers()
5870 rt2x00_set_field32(®, OSC_ROSC_EN, 1); in rt2800_init_registers()
5871 rt2x00_set_field32(®, OSC_CAL_REQ, 1); in rt2800_init_registers()
5872 rt2x00_set_field32(®, OSC_REF_CYCLE, 0x27); in rt2800_init_registers()
5876 rt2x00_set_field32(®, COEX_CFG_ANT, 0x5e); in rt2800_init_registers()
5880 rt2x00_set_field32(®, BT_COEX_CFG1, 0x00); in rt2800_init_registers()
5881 rt2x00_set_field32(®, BT_COEX_CFG0, 0x17); in rt2800_init_registers()
5882 rt2x00_set_field32(®, WL_COEX_CFG1, 0x93); in rt2800_init_registers()
5883 rt2x00_set_field32(®, WL_COEX_CFG0, 0x7f); in rt2800_init_registers()
5887 rt2x00_set_field32(®, PLL_CONTROL, 1); in rt2800_init_registers()
5985 rt2x00_set_field32(®, TX_ALC_CFG_1_ROS_BUSY_EN, 0); in rt2800_init_registers()
5993 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); in rt2800_init_registers()
5994 rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); in rt2800_init_registers()
5995 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); in rt2800_init_registers()
5996 rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0); in rt2800_init_registers()
5997 rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0); in rt2800_init_registers()
5998 rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1); in rt2800_init_registers()
5999 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0); in rt2800_init_registers()
6000 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); in rt2800_init_registers()
6004 rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); in rt2800_init_registers()
6005 rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); in rt2800_init_registers()
6006 rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); in rt2800_init_registers()
6010 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); in rt2800_init_registers()
6020 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu); in rt2800_init_registers()
6021 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 10); in rt2800_init_registers()
6022 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 10); in rt2800_init_registers()
6026 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70); in rt2800_init_registers()
6027 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30); in rt2800_init_registers()
6028 rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); in rt2800_init_registers()
6029 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3); in rt2800_init_registers()
6030 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3); in rt2800_init_registers()
6031 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3); in rt2800_init_registers()
6032 rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1); in rt2800_init_registers()
6038 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 2); in rt2800_init_registers()
6039 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 2); in rt2800_init_registers()
6040 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); in rt2800_init_registers()
6041 rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); in rt2800_init_registers()
6042 rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); in rt2800_init_registers()
6043 rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); in rt2800_init_registers()
6047 rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); in rt2800_init_registers()
6048 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); in rt2800_init_registers()
6049 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 1); in rt2800_init_registers()
6050 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0); in rt2800_init_registers()
6051 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 0); in rt2800_init_registers()
6052 rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0); in rt2800_init_registers()
6053 rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); in rt2800_init_registers()
6057 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3); in rt2800_init_registers()
6058 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); in rt2800_init_registers()
6059 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
6060 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); in rt2800_init_registers()
6061 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
6062 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
6063 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0); in rt2800_init_registers()
6064 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
6065 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0); in rt2800_init_registers()
6066 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1); in rt2800_init_registers()
6070 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3); in rt2800_init_registers()
6071 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); in rt2800_init_registers()
6072 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
6073 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); in rt2800_init_registers()
6074 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
6075 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
6076 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0); in rt2800_init_registers()
6077 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
6078 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0); in rt2800_init_registers()
6079 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1); in rt2800_init_registers()
6083 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); in rt2800_init_registers()
6084 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 1); in rt2800_init_registers()
6085 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
6086 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0); in rt2800_init_registers()
6087 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
6088 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
6089 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); in rt2800_init_registers()
6090 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
6091 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); in rt2800_init_registers()
6092 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0); in rt2800_init_registers()
6096 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); in rt2800_init_registers()
6097 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 1); in rt2800_init_registers()
6098 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
6099 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0); in rt2800_init_registers()
6100 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
6101 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
6102 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); in rt2800_init_registers()
6103 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
6104 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); in rt2800_init_registers()
6105 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0); in rt2800_init_registers()
6109 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); in rt2800_init_registers()
6110 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 1); in rt2800_init_registers()
6111 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
6112 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0); in rt2800_init_registers()
6113 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
6114 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
6115 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); in rt2800_init_registers()
6116 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
6117 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); in rt2800_init_registers()
6118 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0); in rt2800_init_registers()
6122 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); in rt2800_init_registers()
6123 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 1); in rt2800_init_registers()
6124 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
6125 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0); in rt2800_init_registers()
6126 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
6127 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
6128 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); in rt2800_init_registers()
6129 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
6130 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); in rt2800_init_registers()
6131 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0); in rt2800_init_registers()
6138 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); in rt2800_init_registers()
6139 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); in rt2800_init_registers()
6140 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); in rt2800_init_registers()
6141 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); in rt2800_init_registers()
6142 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); in rt2800_init_registers()
6143 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); in rt2800_init_registers()
6144 rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0); in rt2800_init_registers()
6145 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); in rt2800_init_registers()
6146 rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); in rt2800_init_registers()
6155 rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1); in rt2800_init_registers()
6156 rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1); in rt2800_init_registers()
6157 rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1); in rt2800_init_registers()
6158 rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1); in rt2800_init_registers()
6159 rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1); in rt2800_init_registers()
6160 rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1); in rt2800_init_registers()
6161 rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0); in rt2800_init_registers()
6162 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0); in rt2800_init_registers()
6163 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88); in rt2800_init_registers()
6164 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0); in rt2800_init_registers()
6176 rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7); in rt2800_init_registers()
6177 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, in rt2800_init_registers()
6179 rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 1); in rt2800_init_registers()
6192 rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16); in rt2800_init_registers()
6193 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16); in rt2800_init_registers()
6194 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); in rt2800_init_registers()
6195 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314); in rt2800_init_registers()
6196 rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); in rt2800_init_registers()
6229 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30); in rt2800_init_registers()
6233 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125); in rt2800_init_registers()
6254 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, rate); in rt2800_init_registers()
6259 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); in rt2800_init_registers()
6260 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); in rt2800_init_registers()
6261 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); in rt2800_init_registers()
6262 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2); in rt2800_init_registers()
6263 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3); in rt2800_init_registers()
6264 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4); in rt2800_init_registers()
6265 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5); in rt2800_init_registers()
6266 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); in rt2800_init_registers()
6270 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); in rt2800_init_registers()
6271 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); in rt2800_init_registers()
6272 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); in rt2800_init_registers()
6273 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10); in rt2800_init_registers()
6274 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11); in rt2800_init_registers()
6275 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12); in rt2800_init_registers()
6276 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13); in rt2800_init_registers()
6277 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); in rt2800_init_registers()
6281 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); in rt2800_init_registers()
6282 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); in rt2800_init_registers()
6283 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); in rt2800_init_registers()
6284 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10); in rt2800_init_registers()
6285 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11); in rt2800_init_registers()
6286 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12); in rt2800_init_registers()
6287 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13); in rt2800_init_registers()
6288 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); in rt2800_init_registers()
6292 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); in rt2800_init_registers()
6293 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); in rt2800_init_registers()
6294 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); in rt2800_init_registers()
6295 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2); in rt2800_init_registers()
6302 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0); in rt2800_init_registers()
6303 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0); in rt2800_init_registers()
6322 rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4); in rt2800_init_registers()
6329 rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1); in rt2800_init_registers()
6330 rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1); in rt2800_init_registers()
6331 rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1); in rt2800_init_registers()
6332 rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1); in rt2800_init_registers()
6333 rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1); in rt2800_init_registers()
6900 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); in rt2800_init_bbp_53xx()
6901 rt2x00_set_field32(®, GPIO_CTRL_DIR6, 0); in rt2800_init_bbp_53xx()
6902 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 0); in rt2800_init_bbp_53xx()
6903 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 0); in rt2800_init_bbp_53xx()
6905 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 1); in rt2800_init_bbp_53xx()
6907 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 1); in rt2800_init_bbp_53xx()
7276 rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1); in rt2800_led_open_drain_enable()
7609 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_30xx()
7610 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); in rt2800_init_rfcsr_30xx()
7621 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_30xx()
7626 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); in rt2800_init_rfcsr_30xx()
7628 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); in rt2800_init_rfcsr_30xx()
7633 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); in rt2800_init_rfcsr_30xx()
7848 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); in rt2800_init_rfcsr_3390()
7904 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); in rt2800_init_rfcsr_3572()
7905 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_3572()
7909 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); in rt2800_init_rfcsr_3572()
7910 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_3572()
7973 rt2x00_set_field32(®, GPIO_SWITCH_4, 0); in rt2800_init_rfcsr_3593()
7974 rt2x00_set_field32(®, GPIO_SWITCH_7, 0); in rt2800_init_rfcsr_3593()
8024 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); in rt2800_init_rfcsr_3593()
8025 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_3593()
8029 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); in rt2800_init_rfcsr_3593()
10696 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); in rt2800_enable_radio()
10697 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); in rt2800_enable_radio()
10703 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); in rt2800_enable_radio()
10704 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); in rt2800_enable_radio()
10705 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); in rt2800_enable_radio()
10709 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); in rt2800_enable_radio()
10710 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); in rt2800_enable_radio()
10742 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0); in rt2800_disable_radio()
10743 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); in rt2800_disable_radio()
10788 rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); in rt2800_efuse_read()
10789 rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); in rt2800_efuse_read()
10790 rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); in rt2800_efuse_read()
11881 rt2x00_set_field32(®, GPIO_CTRL_DIR2, 1); in rt2800_probe_hw()
11963 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); in rt2800_set_rts_threshold()
11967 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
11971 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
11975 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
11979 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
11983 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
11987 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
12031 rt2x00_set_field32(®, field, queue->txop); in rt2800_conf_tx()
12039 rt2x00_set_field32(®, field, queue->aifs); in rt2800_conf_tx()
12043 rt2x00_set_field32(®, field, queue->cw_min); in rt2800_conf_tx()
12047 rt2x00_set_field32(®, field, queue->cw_max); in rt2800_conf_tx()
12054 rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); in rt2800_conf_tx()
12055 rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); in rt2800_conf_tx()
12056 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); in rt2800_conf_tx()
12057 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max); in rt2800_conf_tx()