Lines Matching +full:spi +full:- +full:crc
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
8 #include <linux/spi/spi.h>
10 #include <linux/crc-itu-t.h>
18 static bool enable_crc7; /* protect SPI commands with CRC7 */
22 "\t\t\tagainst corruption during the SPI transfer.\n"
23 "\t\t\tCommand transfers are short and the CPU-cycle cost\n"
26 static bool enable_crc16; /* protect SPI data with CRC16 */
30 "\t\t\tagainst corruption during the SPI transfer.\n"
31 "\t\t\tData transfers can be large and the CPU-cycle cost\n"
38 * USER GUIDE" (https://tinyurl.com/4hhshdts) but we have observed 1-4
39 * zero bytes when the SPI bus operates at 48MHz and none when it
45 bool isinit; /* true if SPI protocol has been configured */
46 bool probing_crc; /* true if we're probing chip's CRC config */
61 * Spi protocol Function
79 /* SPI response fields (section 11.1.2 in ATWILC1000 User Guide): */
83 /* SPI response values for the response fields: */
95 * The SPI data packet size may be any integer power of two in the
117 u8 crc[]; member
122 u8 crc[]; member
127 u8 crc[]; member
132 u8 crc[]; member
137 u8 crc[]; member
145 u8 crc[]; member
162 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_parse_gpios() local
163 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_parse_gpios()
164 struct wilc_gpios *gpios = &spi_priv->gpios; in wilc_parse_gpios()
167 gpios->enable = devm_gpiod_get_optional(&spi->dev, in wilc_parse_gpios()
170 if (gpios->enable) { in wilc_parse_gpios()
172 gpios->reset = devm_gpiod_get(&spi->dev, in wilc_parse_gpios()
174 if (IS_ERR(gpios->reset)) { in wilc_parse_gpios()
175 dev_err(&spi->dev, "missing reset gpio.\n"); in wilc_parse_gpios()
176 return PTR_ERR(gpios->reset); in wilc_parse_gpios()
179 gpios->reset = devm_gpiod_get_optional(&spi->dev, in wilc_parse_gpios()
187 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_wlan_power()
188 struct wilc_gpios *gpios = &spi_priv->gpios; in wilc_wlan_power()
192 gpiod_set_value(gpios->enable, 1); in wilc_wlan_power()
195 gpiod_set_value(gpios->reset, 1); in wilc_wlan_power()
198 gpiod_set_value(gpios->reset, 0); in wilc_wlan_power()
200 gpiod_set_value(gpios->enable, 0); in wilc_wlan_power()
204 static int wilc_bus_probe(struct spi_device *spi) in wilc_bus_probe() argument
212 return -ENOMEM; in wilc_bus_probe()
214 ret = wilc_cfg80211_init(&wilc, &spi->dev, WILC_HIF_SPI, &wilc_hif_spi); in wilc_bus_probe()
218 spi_set_drvdata(spi, wilc); in wilc_bus_probe()
219 wilc->dev = &spi->dev; in wilc_bus_probe()
220 wilc->bus_data = spi_priv; in wilc_bus_probe()
221 wilc->dev_irq_num = spi->irq; in wilc_bus_probe()
227 wilc->rtc_clk = devm_clk_get_optional(&spi->dev, "rtc"); in wilc_bus_probe()
228 if (IS_ERR(wilc->rtc_clk)) { in wilc_bus_probe()
229 ret = PTR_ERR(wilc->rtc_clk); in wilc_bus_probe()
232 clk_prepare_enable(wilc->rtc_clk); in wilc_bus_probe()
243 static void wilc_bus_remove(struct spi_device *spi) in wilc_bus_remove() argument
245 struct wilc *wilc = spi_get_drvdata(spi); in wilc_bus_remove()
246 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_bus_remove()
248 clk_disable_unprepare(wilc->rtc_clk); in wilc_bus_remove()
263 MODULE_DEVICE_TABLE(spi, wilc_spi_id);
279 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_tx() local
295 return -ENOMEM; in wilc_spi_tx()
298 dev_dbg(&spi->dev, "Request writing %d bytes\n", len); in wilc_spi_tx()
302 msg.spi = spi; in wilc_spi_tx()
305 ret = spi_sync(spi, &msg); in wilc_spi_tx()
307 dev_err(&spi->dev, "SPI transaction failed\n"); in wilc_spi_tx()
311 dev_err(&spi->dev, in wilc_spi_tx()
314 ret = -EINVAL; in wilc_spi_tx()
322 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_rx() local
339 return -ENOMEM; in wilc_spi_rx()
345 msg.spi = spi; in wilc_spi_rx()
348 ret = spi_sync(spi, &msg); in wilc_spi_rx()
350 dev_err(&spi->dev, "SPI transaction failed\n"); in wilc_spi_rx()
353 dev_err(&spi->dev, in wilc_spi_rx()
356 ret = -EINVAL; in wilc_spi_rx()
364 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_tx_rx() local
383 msg.spi = spi; in wilc_spi_tx_rx()
386 ret = spi_sync(spi, &msg); in wilc_spi_tx_rx()
388 dev_err(&spi->dev, "SPI transaction failed\n"); in wilc_spi_tx_rx()
390 dev_err(&spi->dev, in wilc_spi_tx_rx()
393 ret = -EINVAL; in wilc_spi_tx_rx()
401 struct spi_device *spi = to_spi_device(wilc->dev); in spi_data_write() local
402 struct wilc_spi *spi_priv = wilc->bus_data; in spi_data_write()
405 u8 cmd, order, crc[2]; in spi_data_write() local
431 dev_err(&spi->dev, in spi_data_write()
433 result = -EINVAL; in spi_data_write()
441 dev_err(&spi->dev, in spi_data_write()
443 result = -EINVAL; in spi_data_write()
448 * Write CRC in spi_data_write()
450 if (spi_priv->crc16_enabled) { in spi_data_write()
452 crc[0] = crc_calc >> 8; in spi_data_write()
453 crc[1] = crc_calc; in spi_data_write()
454 if (wilc_spi_tx(wilc, crc, 2)) { in spi_data_write()
455 dev_err(&spi->dev, "Failed data block crc write, bus error...\n"); in spi_data_write()
456 result = -EINVAL; in spi_data_write()
465 sz -= nbytes; in spi_data_write()
473 * Spi Internal Read/Write Function
484 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_single_read() local
485 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_single_read()
496 c->cmd_type = cmd; in wilc_spi_single_read()
498 c->u.simple_cmd.addr[0] = adr >> 16; in wilc_spi_single_read()
499 c->u.simple_cmd.addr[1] = adr >> 8; in wilc_spi_single_read()
500 c->u.simple_cmd.addr[2] = adr; in wilc_spi_single_read()
502 c->u.simple_cmd.addr[0] = adr >> 8; in wilc_spi_single_read()
504 c->u.simple_cmd.addr[0] |= BIT(7); in wilc_spi_single_read()
505 c->u.simple_cmd.addr[1] = adr; in wilc_spi_single_read()
506 c->u.simple_cmd.addr[2] = 0x0; in wilc_spi_single_read()
508 dev_err(&spi->dev, "cmd [%x] not supported\n", cmd); in wilc_spi_single_read()
509 return -EINVAL; in wilc_spi_single_read()
512 cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc); in wilc_spi_single_read()
515 if (spi_priv->crc7_enabled) { in wilc_spi_single_read()
516 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_single_read()
522 dev_err(&spi->dev, in wilc_spi_single_read()
523 "spi buffer size too small (%d) (%d) (%zu)\n", in wilc_spi_single_read()
525 return -EINVAL; in wilc_spi_single_read()
529 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); in wilc_spi_single_read()
530 return -EINVAL; in wilc_spi_single_read()
534 if (r->rsp_cmd_type != cmd && !clockless) { in wilc_spi_single_read()
535 if (!spi_priv->probing_crc) in wilc_spi_single_read()
536 dev_err(&spi->dev, in wilc_spi_single_read()
538 cmd, r->rsp_cmd_type); in wilc_spi_single_read()
539 return -EINVAL; in wilc_spi_single_read()
542 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) { in wilc_spi_single_read()
543 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", in wilc_spi_single_read()
544 r->status); in wilc_spi_single_read()
545 return -EINVAL; in wilc_spi_single_read()
549 if (WILC_GET_RESP_HDR_START(r->data[i]) == 0xf) in wilc_spi_single_read()
553 dev_err(&spi->dev, "Error, data start missing\n"); in wilc_spi_single_read()
554 return -EINVAL; in wilc_spi_single_read()
557 r_data = (struct wilc_spi_read_rsp_data *)&r->data[i]; in wilc_spi_single_read()
560 memcpy(b, r_data->data, 4); in wilc_spi_single_read()
562 if (!clockless && spi_priv->crc16_enabled) { in wilc_spi_single_read()
563 crc_recv = (r_data->crc[0] << 8) | r_data->crc[1]; in wilc_spi_single_read()
564 crc_calc = crc_itu_t(0xffff, r_data->data, 4); in wilc_spi_single_read()
566 dev_err(&spi->dev, "%s: bad CRC 0x%04x " in wilc_spi_single_read()
569 return -EINVAL; in wilc_spi_single_read()
579 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_write_cmd() local
580 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_write_cmd()
589 c->cmd_type = cmd; in wilc_spi_write_cmd()
591 c->u.internal_w_cmd.addr[0] = adr >> 8; in wilc_spi_write_cmd()
593 c->u.internal_w_cmd.addr[0] |= BIT(7); in wilc_spi_write_cmd()
595 c->u.internal_w_cmd.addr[1] = adr; in wilc_spi_write_cmd()
596 c->u.internal_w_cmd.data = cpu_to_be32(data); in wilc_spi_write_cmd()
597 cmd_len = offsetof(struct wilc_spi_cmd, u.internal_w_cmd.crc); in wilc_spi_write_cmd()
598 if (spi_priv->crc7_enabled) in wilc_spi_write_cmd()
599 c->u.internal_w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_write_cmd()
601 c->u.w_cmd.addr[0] = adr >> 16; in wilc_spi_write_cmd()
602 c->u.w_cmd.addr[1] = adr >> 8; in wilc_spi_write_cmd()
603 c->u.w_cmd.addr[2] = adr; in wilc_spi_write_cmd()
604 c->u.w_cmd.data = cpu_to_be32(data); in wilc_spi_write_cmd()
605 cmd_len = offsetof(struct wilc_spi_cmd, u.w_cmd.crc); in wilc_spi_write_cmd()
606 if (spi_priv->crc7_enabled) in wilc_spi_write_cmd()
607 c->u.w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_write_cmd()
609 dev_err(&spi->dev, "write cmd [%x] not supported\n", cmd); in wilc_spi_write_cmd()
610 return -EINVAL; in wilc_spi_write_cmd()
613 if (spi_priv->crc7_enabled) in wilc_spi_write_cmd()
619 dev_err(&spi->dev, in wilc_spi_write_cmd()
620 "spi buffer size too small (%d) (%d) (%zu)\n", in wilc_spi_write_cmd()
622 return -EINVAL; in wilc_spi_write_cmd()
626 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); in wilc_spi_write_cmd()
627 return -EINVAL; in wilc_spi_write_cmd()
635 if (r->rsp_cmd_type != cmd && !clockless) { in wilc_spi_write_cmd()
636 dev_err(&spi->dev, in wilc_spi_write_cmd()
638 cmd, r->rsp_cmd_type); in wilc_spi_write_cmd()
639 return -EINVAL; in wilc_spi_write_cmd()
642 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) { in wilc_spi_write_cmd()
643 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", in wilc_spi_write_cmd()
644 r->status); in wilc_spi_write_cmd()
645 return -EINVAL; in wilc_spi_write_cmd()
653 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_dma_rw() local
654 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_dma_rw()
659 u8 crc[2]; in wilc_spi_dma_rw() local
666 c->cmd_type = cmd; in wilc_spi_dma_rw()
668 c->u.dma_cmd.addr[0] = adr >> 16; in wilc_spi_dma_rw()
669 c->u.dma_cmd.addr[1] = adr >> 8; in wilc_spi_dma_rw()
670 c->u.dma_cmd.addr[2] = adr; in wilc_spi_dma_rw()
671 c->u.dma_cmd.size[0] = sz >> 8; in wilc_spi_dma_rw()
672 c->u.dma_cmd.size[1] = sz; in wilc_spi_dma_rw()
673 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd.crc); in wilc_spi_dma_rw()
674 if (spi_priv->crc7_enabled) in wilc_spi_dma_rw()
675 c->u.dma_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_dma_rw()
677 c->u.dma_cmd_ext.addr[0] = adr >> 16; in wilc_spi_dma_rw()
678 c->u.dma_cmd_ext.addr[1] = adr >> 8; in wilc_spi_dma_rw()
679 c->u.dma_cmd_ext.addr[2] = adr; in wilc_spi_dma_rw()
680 c->u.dma_cmd_ext.size[0] = sz >> 16; in wilc_spi_dma_rw()
681 c->u.dma_cmd_ext.size[1] = sz >> 8; in wilc_spi_dma_rw()
682 c->u.dma_cmd_ext.size[2] = sz; in wilc_spi_dma_rw()
683 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd_ext.crc); in wilc_spi_dma_rw()
684 if (spi_priv->crc7_enabled) in wilc_spi_dma_rw()
685 c->u.dma_cmd_ext.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_dma_rw()
687 dev_err(&spi->dev, "dma read write cmd [%x] not supported\n", in wilc_spi_dma_rw()
689 return -EINVAL; in wilc_spi_dma_rw()
691 if (spi_priv->crc7_enabled) in wilc_spi_dma_rw()
697 dev_err(&spi->dev, "spi buffer size too small (%d)(%d) (%zu)\n", in wilc_spi_dma_rw()
699 return -EINVAL; in wilc_spi_dma_rw()
703 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); in wilc_spi_dma_rw()
704 return -EINVAL; in wilc_spi_dma_rw()
708 if (r->rsp_cmd_type != cmd) { in wilc_spi_dma_rw()
709 dev_err(&spi->dev, in wilc_spi_dma_rw()
711 cmd, r->rsp_cmd_type); in wilc_spi_dma_rw()
712 return -EINVAL; in wilc_spi_dma_rw()
715 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { in wilc_spi_dma_rw()
716 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", in wilc_spi_dma_rw()
717 r->status); in wilc_spi_dma_rw()
718 return -EINVAL; in wilc_spi_dma_rw()
736 dev_err(&spi->dev, in wilc_spi_dma_rw()
738 return -EINVAL; in wilc_spi_dma_rw()
742 } while (retry--); in wilc_spi_dma_rw()
748 dev_err(&spi->dev, in wilc_spi_dma_rw()
750 return -EINVAL; in wilc_spi_dma_rw()
754 * Read CRC in wilc_spi_dma_rw()
756 if (spi_priv->crc16_enabled) { in wilc_spi_dma_rw()
757 if (wilc_spi_rx(wilc, crc, 2)) { in wilc_spi_dma_rw()
758 dev_err(&spi->dev, in wilc_spi_dma_rw()
759 "Failed block CRC read, bus err\n"); in wilc_spi_dma_rw()
760 return -EINVAL; in wilc_spi_dma_rw()
762 crc_recv = (crc[0] << 8) | crc[1]; in wilc_spi_dma_rw()
765 dev_err(&spi->dev, "%s: bad CRC 0x%04x " in wilc_spi_dma_rw()
768 return -EINVAL; in wilc_spi_dma_rw()
773 sz -= nbytes; in wilc_spi_dma_rw()
780 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_special_cmd() local
781 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_special_cmd()
788 return -EINVAL; in wilc_spi_special_cmd()
793 c->cmd_type = cmd; in wilc_spi_special_cmd()
796 memset(c->u.simple_cmd.addr, 0xFF, 3); in wilc_spi_special_cmd()
798 cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc); in wilc_spi_special_cmd()
801 if (spi_priv->crc7_enabled) { in wilc_spi_special_cmd()
802 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_special_cmd()
806 dev_err(&spi->dev, "spi buffer size too small (%d) (%d) (%zu)\n", in wilc_spi_special_cmd()
808 return -EINVAL; in wilc_spi_special_cmd()
812 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); in wilc_spi_special_cmd()
813 return -EINVAL; in wilc_spi_special_cmd()
817 if (r->rsp_cmd_type != cmd) { in wilc_spi_special_cmd()
818 if (!spi_priv->probing_crc) in wilc_spi_special_cmd()
819 dev_err(&spi->dev, in wilc_spi_special_cmd()
821 cmd, r->rsp_cmd_type); in wilc_spi_special_cmd()
822 return -EINVAL; in wilc_spi_special_cmd()
825 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { in wilc_spi_special_cmd()
826 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", in wilc_spi_special_cmd()
827 r->status); in wilc_spi_special_cmd()
828 return -EINVAL; in wilc_spi_special_cmd()
835 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_read_reg() local
848 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr); in wilc_spi_read_reg()
859 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_read() local
863 return -EINVAL; in wilc_spi_read()
867 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr); in wilc_spi_read()
876 struct spi_device *spi = to_spi_device(wilc->dev); in spi_internal_write() local
881 dev_err(&spi->dev, "Failed internal write cmd...\n"); in spi_internal_write()
890 struct spi_device *spi = to_spi_device(wilc->dev); in spi_internal_read() local
891 struct wilc_spi *spi_priv = wilc->bus_data; in spi_internal_read()
896 if (!spi_priv->probing_crc) in spi_internal_read()
897 dev_err(&spi->dev, "Failed internal read cmd...\n"); in spi_internal_read()
908 * Spi interfaces
914 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_write_reg() local
927 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr); in wilc_spi_write_reg()
936 struct spi_device *spi = to_spi_device(wilc->dev); in spi_data_rsp() local
946 * second-to-last packet before the one for the final packet. in spi_data_rsp()
954 dev_err(&spi->dev, "Failed bus error...\n"); in spi_data_rsp()
958 for (i = sizeof(rsp) - 2; i >= 0; --i) in spi_data_rsp()
963 dev_err(&spi->dev, in spi_data_rsp()
966 return -1; in spi_data_rsp()
973 dev_err(&spi->dev, "Data response error (%02x %02x)\n", in spi_data_rsp()
975 return -1; in spi_data_rsp()
982 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_write() local
989 return -EINVAL; in wilc_spi_write()
993 dev_err(&spi->dev, in wilc_spi_write()
1003 dev_err(&spi->dev, "Failed block data write...\n"); in wilc_spi_write()
1021 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_reset() local
1022 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_reset()
1026 if (result && !spi_priv->probing_crc) in wilc_spi_reset()
1027 dev_err(&spi->dev, "Failed cmd reset\n"); in wilc_spi_reset()
1034 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_is_init()
1036 return spi_priv->isinit; in wilc_spi_is_init()
1041 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_deinit()
1043 spi_priv->isinit = false; in wilc_spi_deinit()
1050 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_init() local
1051 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_init()
1056 if (spi_priv->isinit) { in wilc_spi_init()
1062 dev_err(&spi->dev, "Fail cmd read chip id...\n"); in wilc_spi_init()
1072 * Infer the CRC settings that are currently in effect. This in wilc_spi_init()
1076 spi_priv->probing_crc = true; in wilc_spi_init()
1077 spi_priv->crc7_enabled = enable_crc7; in wilc_spi_init()
1078 spi_priv->crc16_enabled = false; /* don't check CRC16 during probing */ in wilc_spi_init()
1083 spi_priv->crc7_enabled = !enable_crc7; in wilc_spi_init()
1086 dev_err(&spi->dev, "Failed with CRC7 on and off.\n"); in wilc_spi_init()
1090 /* set up the desired CRC configuration: */ in wilc_spi_init()
1102 DATA_PKT_LOG_SZ - DATA_PKT_LOG_SZ_MIN); in wilc_spi_init()
1107 dev_err(&spi->dev, in wilc_spi_init()
1108 "[wilc spi %d]: Failed internal write reg\n", in wilc_spi_init()
1113 spi_priv->crc7_enabled = enable_crc7; in wilc_spi_init()
1114 spi_priv->crc16_enabled = enable_crc16; in wilc_spi_init()
1116 /* re-read to make sure new settings are in effect: */ in wilc_spi_init()
1119 spi_priv->probing_crc = false; in wilc_spi_init()
1126 dev_err(&spi->dev, "Fail cmd read chip id...\n"); in wilc_spi_init()
1130 spi_priv->isinit = true; in wilc_spi_init()
1140 WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, size); in wilc_spi_read_size()
1148 return spi_internal_read(wilc, WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, in wilc_spi_read_int()
1160 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, in wilc_spi_clear_int_ext()
1166 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, in wilc_spi_clear_int_ext()
1171 retry--; in wilc_spi_clear_int_ext()
1178 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_sync_ext() local
1183 dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint); in wilc_spi_sync_ext()
1184 return -EINVAL; in wilc_spi_sync_ext()
1192 dev_err(&spi->dev, "Failed read reg (%08x)...\n", in wilc_spi_sync_ext()
1199 dev_err(&spi->dev, "Failed write reg (%08x)...\n", in wilc_spi_sync_ext()
1209 dev_err(&spi->dev, "Failed read reg (%08x)...\n", in wilc_spi_sync_ext()
1214 for (i = 0; (i < 5) && (nint > 0); i++, nint--) in wilc_spi_sync_ext()
1219 dev_err(&spi->dev, "Failed write reg (%08x)...\n", in wilc_spi_sync_ext()
1226 dev_err(&spi->dev, "Failed read reg (%08x)...\n", in wilc_spi_sync_ext()
1231 for (i = 0; (i < 3) && (nint > 0); i++, nint--) in wilc_spi_sync_ext()
1236 dev_err(&spi->dev, "Failed write reg (%08x)...\n", in wilc_spi_sync_ext()
1245 /* Global spi HIF function table */