Lines Matching +full:0 +full:x54000000
8 #define MT_MCU_WFDMA1_BASE 0x3000
11 #define MT_MCU_INT_EVENT MT_MCU_WFDMA1(0x108)
12 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
17 #define MT_PLE_BASE 0x820c0000
20 #define MT_PLE_FL_Q0_CTRL MT_PLE(0x3e0)
21 #define MT_PLE_FL_Q1_CTRL MT_PLE(0x3e4)
22 #define MT_PLE_FL_Q2_CTRL MT_PLE(0x3e8)
23 #define MT_PLE_FL_Q3_CTRL MT_PLE(0x3ec)
25 #define MT_PLE_AC_QEMPTY(_n) MT_PLE(0x500 + 0x40 * (_n))
26 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
28 #define MT_MDP_BASE 0x820cd000
31 #define MT_MDP_DCR0 MT_MDP(0x000)
35 #define MT_MDP_DCR1 MT_MDP(0x004)
38 #define MT_MDP_BNRCFR0(_band) MT_MDP(0x070 + ((_band) << 8))
43 #define MT_MDP_BNRCFR1(_band) MT_MDP(0x074 + ((_band) << 8))
47 #define MT_MDP_TO_HIF 0
50 /* TMAC: band 0(0x21000), band 1(0xa1000) */
51 #define MT_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000)
54 #define MT_TMAC_TCR0(_band) MT_WF_TMAC(_band, 0)
57 #define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, 0x090)
58 #define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, 0x094)
59 #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)
62 #define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, 0x0a4)
63 #define MT_IFS_EIFS GENMASK(8, 0)
68 #define MT_TMAC_CTCR0(_band) MT_WF_TMAC(_band, 0x0f4)
69 #define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0)
73 #define MT_TMAC_TRCR0(_band) MT_WF_TMAC(_band, 0x09c)
74 #define MT_TMAC_TFCR0(_band) MT_WF_TMAC(_band, 0x1e0)
76 #define MT_WF_DMA_BASE(_band) ((_band) ? 0x820f7000 : 0x820e7000)
79 #define MT_DMA_DCR0(_band) MT_WF_DMA(_band, 0x000)
83 /* LPON: band 0(0x24200), band 1(0xa4200) */
84 #define MT_WF_LPON_BASE(_band) ((_band) ? 0x820fb000 : 0x820eb000)
87 #define MT_LPON_UTTR0(_band) MT_WF_LPON(_band, 0x080)
88 #define MT_LPON_UTTR1(_band) MT_WF_LPON(_band, 0x084)
90 #define MT_LPON_TCR(_band, n) MT_WF_LPON(_band, 0x0a8 + (n) * 4)
91 #define MT_LPON_TCR_SW_MODE GENMASK(1, 0)
92 #define MT_LPON_TCR_SW_WRITE BIT(0)
94 /* ETBF: band 0(0x24000), band 1(0xa4000) */
95 #define MT_WF_ETBF_BASE(_band) ((_band) ? 0x820fa000 : 0x820ea000)
98 #define MT_ETBF_TX_APP_CNT(_band) MT_WF_ETBF(_band, 0x150)
100 #define MT_ETBF_TX_EBF_CNT GENMASK(15, 0)
102 #define MT_ETBF_RX_FB_CNT(_band) MT_WF_ETBF(_band, 0x158)
106 #define MT_ETBF_RX_FB_HT GENMASK(7, 0)
108 /* MIB: band 0(0x24800), band 1(0xa4800) */
109 #define MT_WF_MIB_BASE(_band) ((_band) ? 0x820fd000 : 0x820ed000)
112 #define MT_MIB_SCR1(_band) MT_WF_MIB(_band, 0x004)
116 #define MT_MIB_SDR3(_band) MT_WF_MIB(_band, 0x698)
119 #define MT_MIB_SDR5(_band) MT_WF_MIB(_band, 0x780)
121 #define MT_MIB_SDR9(_band) MT_WF_MIB(_band, 0x02c)
122 #define MT_MIB_SDR9_BUSY_MASK GENMASK(23, 0)
124 #define MT_MIB_SDR12(_band) MT_WF_MIB(_band, 0x558)
125 #define MT_MIB_SDR14(_band) MT_WF_MIB(_band, 0x564)
126 #define MT_MIB_SDR15(_band) MT_WF_MIB(_band, 0x568)
128 #define MT_MIB_SDR16(_band) MT_WF_MIB(_band, 0x048)
129 #define MT_MIB_SDR16_BUSY_MASK GENMASK(23, 0)
131 #define MT_MIB_SDR22(_band) MT_WF_MIB(_band, 0x770)
132 #define MT_MIB_SDR23(_band) MT_WF_MIB(_band, 0x774)
133 #define MT_MIB_SDR31(_band) MT_WF_MIB(_band, 0x55c)
135 #define MT_MIB_SDR32(_band) MT_WF_MIB(_band, 0x7a8)
137 #define MT_MIB_SDR9_EBF_CNT_MASK GENMASK(15, 0)
139 #define MT_MIB_SDR34(_band) MT_WF_MIB(_band, 0x090)
140 #define MT_MIB_MU_BF_TX_CNT GENMASK(15, 0)
142 #define MT_MIB_SDR36(_band) MT_WF_MIB(_band, 0x054)
143 #define MT_MIB_SDR36_TXTIME_MASK GENMASK(23, 0)
144 #define MT_MIB_SDR37(_band) MT_WF_MIB(_band, 0x058)
145 #define MT_MIB_SDR37_RXTIME_MASK GENMASK(23, 0)
147 #define MT_MIB_DR8(_band) MT_WF_MIB(_band, 0x0c0)
148 #define MT_MIB_DR9(_band) MT_WF_MIB(_band, 0x0c4)
149 #define MT_MIB_DR11(_band) MT_WF_MIB(_band, 0x0cc)
151 #define MT_MIB_MB_SDR0(_band, n) MT_WF_MIB(_band, 0x100 + ((n) << 4))
153 #define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0)
155 #define MT_MIB_MB_BSDR0(_band) MT_WF_MIB(_band, 0x688)
156 #define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0)
157 #define MT_MIB_MB_BSDR1(_band) MT_WF_MIB(_band, 0x690)
158 #define MT_MIB_RTS_FAIL_COUNT_MASK GENMASK(15, 0)
159 #define MT_MIB_MB_BSDR2(_band) MT_WF_MIB(_band, 0x518)
160 #define MT_MIB_BA_FAIL_COUNT_MASK GENMASK(15, 0)
161 #define MT_MIB_MB_BSDR3(_band) MT_WF_MIB(_band, 0x520)
162 #define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(15, 0)
164 #define MT_MIB_MB_SDR2(_band, n) MT_WF_MIB(_band, 0x108 + ((n) << 4))
165 #define MT_MIB_FRAME_RETRIES_COUNT_MASK GENMASK(15, 0)
167 #define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, 0x7dc + ((n) << 2))
168 #define MT_TX_AGG_CNT2(_band, n) MT_WF_MIB(_band, 0x7ec + ((n) << 2))
169 #define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, 0x0b0 + ((n) << 2))
170 #define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(7, 0))
172 #define MT_WTBLON_TOP_BASE 0x820d4000
174 #define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(0x200)
175 #define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0)
177 #define MT_WTBL_UPDATE MT_WTBLON_TOP(0x230)
178 #define MT_WTBL_UPDATE_WLAN_IDX GENMASK(9, 0)
182 #define MT_WTBL_BASE 0x820d8000
189 /* AGG: band 0(0x20800), band 1(0xa0800) */
190 #define MT_WF_AGG_BASE(_band) ((_band) ? 0x820f2000 : 0x820e2000)
193 #define MT_AGG_AWSCR0(_band, _n) MT_WF_AGG(_band, 0x05c + (_n) * 4)
194 #define MT_AGG_PCR0(_band, _n) MT_WF_AGG(_band, 0x06c + (_n) * 4)
195 #define MT_AGG_PCR0_MM_PROT BIT(0)
205 #define MT_AGG_PCR1_RTS0_LEN_THRES GENMASK(19, 0)
207 #define MT_AGG_ACR0(_band) MT_WF_AGG(_band, 0x084)
208 #define MT_AGG_ACR_CFEND_RATE GENMASK(13, 0)
211 #define MT_AGG_MRCR(_band) MT_WF_AGG(_band, 0x098)
217 #define MT_AGG_ATCR1(_band) MT_WF_AGG(_band, 0x0f0)
218 #define MT_AGG_ATCR3(_band) MT_WF_AGG(_band, 0x0f4)
220 /* ARB: band 0(0x20c00), band 1(0xa0c00) */
221 #define MT_WF_ARB_BASE(_band) ((_band) ? 0x820f3000 : 0x820e3000)
224 #define MT_ARB_SCR(_band) MT_WF_ARB(_band, 0x080)
228 #define MT_ARB_DRNGR0(_band, _n) MT_WF_ARB(_band, 0x194 + (_n) * 4)
230 /* RMAC: band 0(0x21400), band 1(0xa1400) */
231 #define MT_WF_RMAC_BASE(_band) ((_band) ? 0x820f5000 : 0x820e5000)
234 #define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000)
235 #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0)
257 #define MT_WF_RFCR1(_band) MT_WF_RMAC(_band, 0x004)
264 #define MT_WF_RMAC_MIB_TIME0(_band) MT_WF_RMAC(_band, 0x03c4)
268 #define MT_WF_RMAC_MIB_AIRTIME14(_band) MT_WF_RMAC(_band, 0x03b8)
269 #define MT_MIB_OBSSTIME_MASK GENMASK(23, 0)
270 #define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_WF_RMAC(_band, 0x0380)
273 #define MT_WFDMA0_BASE 0xd4000
276 #define MT_WFDMA0_RST MT_WFDMA0(0x100)
280 #define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c)
281 #define MT_WFDMA0_BUSY_ENA_TX_FIFO0 BIT(0)
285 #define MT_MCU_CMD MT_WFDMA0(0x1f0)
286 #define MT_MCU_CMD_WAKE_RX_PCIE BIT(0)
294 #define MT_MCU2HOST_SW_INT_ENA MT_WFDMA0(0x1f4)
296 #define MT_WFDMA0_HOST_INT_STA MT_WFDMA0(0x200)
297 #define HOST_RX_DONE_INT_STS0 BIT(0) /* Rx mcu */
303 #define MT_WFDMA0_HOST_INT_ENA MT_WFDMA0(0x204)
304 #define HOST_RX_DONE_INT_ENA0 BIT(0)
350 #define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208)
351 #define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0)
364 #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)
365 #define MT_WFDMA0_GLO_CFG_EXT0 MT_WFDMA0(0x2b0)
367 #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0)
369 #define MT_RX_DATA_RING_BASE MT_WFDMA0(0x520)
371 #define MT_WFDMA0_TX_RING0_EXT_CTRL MT_WFDMA0(0x600)
372 #define MT_WFDMA0_TX_RING1_EXT_CTRL MT_WFDMA0(0x604)
373 #define MT_WFDMA0_TX_RING2_EXT_CTRL MT_WFDMA0(0x608)
374 #define MT_WFDMA0_TX_RING3_EXT_CTRL MT_WFDMA0(0x60c)
375 #define MT_WFDMA0_TX_RING4_EXT_CTRL MT_WFDMA0(0x610)
376 #define MT_WFDMA0_TX_RING5_EXT_CTRL MT_WFDMA0(0x614)
377 #define MT_WFDMA0_TX_RING6_EXT_CTRL MT_WFDMA0(0x618)
378 #define MT_WFDMA0_TX_RING16_EXT_CTRL MT_WFDMA0(0x640)
379 #define MT_WFDMA0_TX_RING17_EXT_CTRL MT_WFDMA0(0x644)
381 #define MT_WPDMA0_MAX_CNT_MASK GENMASK(7, 0)
384 #define MT_WFDMA0_RX_RING0_EXT_CTRL MT_WFDMA0(0x680)
385 #define MT_WFDMA0_RX_RING1_EXT_CTRL MT_WFDMA0(0x684)
386 #define MT_WFDMA0_RX_RING2_EXT_CTRL MT_WFDMA0(0x688)
387 #define MT_WFDMA0_RX_RING3_EXT_CTRL MT_WFDMA0(0x68c)
388 #define MT_WFDMA0_RX_RING4_EXT_CTRL MT_WFDMA0(0x690)
389 #define MT_WFDMA0_RX_RING5_EXT_CTRL MT_WFDMA0(0x694)
391 #define MT_TX_RING_BASE MT_WFDMA0(0x300)
392 #define MT_RX_EVENT_RING_BASE MT_WFDMA0(0x500)
395 #define MT_WFDMA_EXT_CSR_BASE 0xd7000
397 #define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44)
398 #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0)
400 #define MT_INFRA_CFG_BASE 0xfe000
403 #define MT_HIF_REMAP_L1 MT_INFRA(0x24c)
404 #define MT_HIF_REMAP_L1_MASK GENMASK(15, 0)
405 #define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0)
407 #define MT_HIF_REMAP_BASE_L1 0x40000
409 #define MT_SWDEF_BASE 0x41f200
411 #define MT_SWDEF_MODE MT_SWDEF(0x3c)
412 #define MT_SWDEF_NORMAL_MODE 0
416 #define MT_TOP_BASE 0x18060000
419 #define MT_TOP_LPCR_HOST_BAND0 MT_TOP(0x10)
420 #define MT_TOP_LPCR_HOST_FW_OWN BIT(0)
423 #define MT_TOP_MISC MT_TOP(0xf0)
424 #define MT_TOP_MISC_FW_STATE GENMASK(2, 0)
426 #define MT_MCU_WPDMA0_BASE 0x54000000
429 #define MT_WFDMA_DUMMY_CR MT_MCU_WPDMA0(0x120)
432 #define MT_CBTOP_RGU(ofs) (0x70002000 + (ofs))
433 #define MT_CBTOP_RGU_WF_SUBSYS_RST MT_CBTOP_RGU(0x600)
434 #define MT_CBTOP_RGU_WF_SUBSYS_RST_WF_WHOLE_PATH BIT(0)
436 #define MT_HW_BOUND 0x70010020
437 #define MT_HW_CHIPID 0x70010200
438 #define MT_HW_REV 0x70010204
440 #define MT_PCIE_MAC_BASE 0x10000
442 #define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188)
443 #define MT_PCIE_MAC_PM MT_PCIE_MAC(0x194)
446 #define MT_DMA_SHDL(ofs) (0x7c026000 + (ofs))
447 #define MT_DMASHDL_SW_CONTROL MT_DMA_SHDL(0x004)
449 #define MT_DMASHDL_OPTIONAL MT_DMA_SHDL(0x008)
450 #define MT_DMASHDL_PAGE MT_DMA_SHDL(0x00c)
452 #define MT_DMASHDL_REFILL MT_DMA_SHDL(0x010)
454 #define MT_DMASHDL_PKT_MAX_SIZE MT_DMA_SHDL(0x01c)
455 #define MT_DMASHDL_PKT_MAX_SIZE_PLE GENMASK(11, 0)
458 #define MT_DMASHDL_GROUP_QUOTA(_n) MT_DMA_SHDL(0x020 + ((_n) << 2))
459 #define MT_DMASHDL_GROUP_QUOTA_MIN GENMASK(11, 0)
462 #define MT_DMASHDL_Q_MAP(_n) MT_DMA_SHDL(0x060 + ((_n) << 2))
463 #define MT_DMASHDL_Q_MAP_MASK GENMASK(3, 0)
466 #define MT_DMASHDL_SCHED_SET(_n) MT_DMA_SHDL(0x070 + ((_n) << 2))
468 #define MT_WFDMA_HOST_CONFIG 0x7c027030
471 #define MT_UMAC(ofs) (0x74000000 + (ofs))
472 #define MT_UDMA_TX_QSEL MT_UMAC(0x008)
475 #define MT_UDMA_WLCFG_1 MT_UMAC(0x00c)
476 #define MT_WL_RX_AGG_PKT_LMT GENMASK(7, 0)
479 #define MT_UDMA_WLCFG_0 MT_UMAC(0x18)
480 #define MT_WL_RX_AGG_TO GENMASK(7, 0)
493 #define MT_UDMA_CONN_INFRA_STATUS MT_UMAC(0xa20)
495 #define MT_UDMA_CONN_INFRA_STATUS_SEL MT_UMAC(0xa24)
497 #define MT_SSUSB_EPCTL_CSR(ofs) (0x74011800 + (ofs))
498 #define MT_SSUSB_EPCTL_CSR_EP_RST_OPT MT_SSUSB_EPCTL_CSR(0x090)
500 #define MT_UWFDMA0(ofs) (0x7c024000 + (ofs))
501 #define MT_UWFDMA0_GLO_CFG MT_UWFDMA0(0x208)
502 #define MT_UWFDMA0_GLO_CFG_EXT0 MT_UWFDMA0(0x2b0)
503 #define MT_UWFDMA0_TX_RING_EXT_CTRL(_n) MT_UWFDMA0(0x600 + ((_n) << 2))
505 #define MT_CONN_STATUS 0x7c053c10
506 #define MT_WIFI_PATCH_DL_STATE BIT(0)
508 #define MT_CONN_ON_LPCTL 0x7c060010
511 #define PCIE_LPCR_HOST_SET_OWN BIT(0)
513 #define MT_WFSYS_SW_RST_B 0x18000140
514 #define WFSYS_SW_RST_B BIT(0)
517 #define MT_CONN_ON_MISC 0x7c0600f0
518 #define MT_TOP_MISC2_FW_PWR_ON BIT(0)
519 #define MT_TOP_MISC2_FW_N9_RDY GENMASK(1, 0)
521 #define MT_WF_SW_DEF_CR(ofs) (0x401a00 + (ofs))
522 #define MT_WF_SW_DEF_CR_USB_MCU_EVENT MT_WF_SW_DEF_CR(0x028)