Lines Matching +full:0 +full:x02000

16 	{ PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961) },
17 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922) },
18 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608) },
19 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616) },
44 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0); in mt7921_irq_handler()
57 u32 intr, mask = 0; in mt7921_irq_tasklet()
59 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0); in mt7921_irq_tasklet()
83 mt76_set_irq_mask(&dev->mt76, MT_WFDMA0_HOST_INT_ENA, mask, 0); in mt7921_irq_tasklet()
127 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ in __mt7921_reg_addr()
128 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ in __mt7921_reg_addr()
129 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ in __mt7921_reg_addr()
130 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ in __mt7921_reg_addr()
131 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ in __mt7921_reg_addr()
132 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ in __mt7921_reg_addr()
133 { 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ in __mt7921_reg_addr()
134 { 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ in __mt7921_reg_addr()
135 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */ in __mt7921_reg_addr()
136 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */ in __mt7921_reg_addr()
137 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */ in __mt7921_reg_addr()
138 { 0x54000000, 0x02000, 0x01000 }, /* WFDMA PCIE0 MCU DMA0 */ in __mt7921_reg_addr()
139 { 0x55000000, 0x03000, 0x01000 }, /* WFDMA PCIE0 MCU DMA1 */ in __mt7921_reg_addr()
140 { 0x58000000, 0x06000, 0x01000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ in __mt7921_reg_addr()
141 { 0x59000000, 0x07000, 0x01000 }, /* WFDMA PCIE1 MCU DMA1 */ in __mt7921_reg_addr()
142 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */ in __mt7921_reg_addr()
143 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */ in __mt7921_reg_addr()
144 { 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */ in __mt7921_reg_addr()
145 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ in __mt7921_reg_addr()
146 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ in __mt7921_reg_addr()
147 { 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */ in __mt7921_reg_addr()
148 { 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */ in __mt7921_reg_addr()
149 { 0x820cc000, 0x0e000, 0x01000 }, /* WF_UMAC_TOP (PP) */ in __mt7921_reg_addr()
150 { 0x820cd000, 0x0f000, 0x01000 }, /* WF_MDP_TOP */ in __mt7921_reg_addr()
151 { 0x74030000, 0x10000, 0x10000 }, /* PCIE_MAC_IREG */ in __mt7921_reg_addr()
152 { 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */ in __mt7921_reg_addr()
153 { 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */ in __mt7921_reg_addr()
154 { 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ in __mt7921_reg_addr()
155 { 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ in __mt7921_reg_addr()
156 { 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ in __mt7921_reg_addr()
157 { 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ in __mt7921_reg_addr()
158 { 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ in __mt7921_reg_addr()
159 { 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ in __mt7921_reg_addr()
160 { 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ in __mt7921_reg_addr()
161 { 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ in __mt7921_reg_addr()
162 { 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ in __mt7921_reg_addr()
163 { 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ in __mt7921_reg_addr()
164 { 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ in __mt7921_reg_addr()
165 { 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ in __mt7921_reg_addr()
166 { 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ in __mt7921_reg_addr()
167 { 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ in __mt7921_reg_addr()
168 { 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ in __mt7921_reg_addr()
169 { 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ in __mt7921_reg_addr()
170 { 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ in __mt7921_reg_addr()
174 if (addr < 0x100000) in __mt7921_reg_addr()
177 for (i = 0; i < ARRAY_SIZE(fixed_map); i++) { in __mt7921_reg_addr()
190 if ((addr >= 0x18000000 && addr < 0x18c00000) || in __mt7921_reg_addr()
191 (addr >= 0x70000000 && addr < 0x78000000) || in __mt7921_reg_addr()
192 (addr >= 0x7c000000 && addr < 0x7c400000)) in __mt7921_reg_addr()
198 return 0; in __mt7921_reg_addr()
264 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev)); in mt7921_pci_probe()
271 if (ret < 0) in mt7921_pci_probe()
293 mt76_mmio_init(&dev->mt76, pcim_iomap_table(pdev)[0]); in mt7921_pci_probe()
317 (mt7921_l1_rr(dev, MT_HW_REV) & 0xff); in mt7921_pci_probe()
320 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0); in mt7921_pci_probe()
322 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); in mt7921_pci_probe()
337 return 0; in mt7921_pci_probe()
374 if (err < 0) in mt7921_pci_suspend()
396 MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000); in mt7921_pci_suspend()
403 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0); in mt7921_pci_suspend()
404 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0); in mt7921_pci_suspend()
412 return 0; in mt7921_pci_suspend()
428 if (err < 0) in mt7921_pci_suspend()
443 if (err < 0) in mt7921_pci_resume()
449 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); in mt7921_pci_resume()
477 if (err < 0) in mt7921_pci_resume()