Lines Matching +full:0 +full:xb0000
14 [INT_SOURCE_CSR] = 0xd7010,
15 [INT_MASK_CSR] = 0xd7014,
16 [INT1_SOURCE_CSR] = 0xd7088,
17 [INT1_MASK_CSR] = 0xd708c,
18 [INT_MCU_CMD_SOURCE] = 0xd51f0,
19 [INT_MCU_CMD_EVENT] = 0x3108,
20 [WFDMA0_ADDR] = 0xd4000,
21 [WFDMA0_PCIE1_ADDR] = 0xd8000,
22 [WFDMA_EXT_CSR_ADDR] = 0xd7000,
23 [CBTOP1_PHY_END] = 0x77ffffff,
24 [INFRA_MCU_ADDR_END] = 0x7c3fffff,
25 [FW_EXCEPTION_ADDR] = 0x219848,
26 [SWDEF_BASE_ADDR] = 0x41f200,
30 [INT_SOURCE_CSR] = 0xd4200,
31 [INT_MASK_CSR] = 0xd4204,
32 [INT1_SOURCE_CSR] = 0xd8200,
33 [INT1_MASK_CSR] = 0xd8204,
34 [INT_MCU_CMD_SOURCE] = 0xd41f0,
35 [INT_MCU_CMD_EVENT] = 0x2108,
36 [WFDMA0_ADDR] = 0xd4000,
37 [WFDMA0_PCIE1_ADDR] = 0xd8000,
38 [WFDMA_EXT_CSR_ADDR] = 0xd7000,
39 [CBTOP1_PHY_END] = 0x7fffffff,
40 [INFRA_MCU_ADDR_END] = 0x7c085fff,
41 [FW_EXCEPTION_ADDR] = 0x022050bc,
42 [SWDEF_BASE_ADDR] = 0x411400,
46 [INT_SOURCE_CSR] = 0x24200,
47 [INT_MASK_CSR] = 0x24204,
48 [INT1_SOURCE_CSR] = 0x28200,
49 [INT1_MASK_CSR] = 0x28204,
50 [INT_MCU_CMD_SOURCE] = 0x241f0,
51 [INT_MCU_CMD_EVENT] = 0x54000108,
52 [WFDMA0_ADDR] = 0x24000,
53 [WFDMA0_PCIE1_ADDR] = 0x28000,
54 [WFDMA_EXT_CSR_ADDR] = 0x27000,
55 [CBTOP1_PHY_END] = 0x7fffffff,
56 [INFRA_MCU_ADDR_END] = 0x7c085fff,
57 [FW_EXCEPTION_ADDR] = 0x02204ffc,
58 [SWDEF_BASE_ADDR] = 0x411400,
62 [TMAC_CDTR] = 0x090,
63 [TMAC_ODTR] = 0x094,
64 [TMAC_ATCR] = 0x098,
65 [TMAC_TRCR0] = 0x09c,
66 [TMAC_ICR0] = 0x0a4,
67 [TMAC_ICR1] = 0x0b4,
68 [TMAC_CTCR0] = 0x0f4,
69 [TMAC_TFCR0] = 0x1e0,
70 [MDP_BNRCFR0] = 0x070,
71 [MDP_BNRCFR1] = 0x074,
72 [ARB_DRNGR0] = 0x194,
73 [ARB_SCR] = 0x080,
74 [RMAC_MIB_AIRTIME14] = 0x3b8,
75 [AGG_AWSCR0] = 0x05c,
76 [AGG_PCR0] = 0x06c,
77 [AGG_ACR0] = 0x084,
78 [AGG_ACR4] = 0x08c,
79 [AGG_MRCR] = 0x098,
80 [AGG_ATCR1] = 0x0f0,
81 [AGG_ATCR3] = 0x0f4,
82 [LPON_UTTR0] = 0x080,
83 [LPON_UTTR1] = 0x084,
84 [LPON_FRCR] = 0x314,
85 [MIB_SDR3] = 0x014,
86 [MIB_SDR4] = 0x018,
87 [MIB_SDR5] = 0x01c,
88 [MIB_SDR7] = 0x024,
89 [MIB_SDR8] = 0x028,
90 [MIB_SDR9] = 0x02c,
91 [MIB_SDR10] = 0x030,
92 [MIB_SDR11] = 0x034,
93 [MIB_SDR12] = 0x038,
94 [MIB_SDR13] = 0x03c,
95 [MIB_SDR14] = 0x040,
96 [MIB_SDR15] = 0x044,
97 [MIB_SDR16] = 0x048,
98 [MIB_SDR17] = 0x04c,
99 [MIB_SDR18] = 0x050,
100 [MIB_SDR19] = 0x054,
101 [MIB_SDR20] = 0x058,
102 [MIB_SDR21] = 0x05c,
103 [MIB_SDR22] = 0x060,
104 [MIB_SDR23] = 0x064,
105 [MIB_SDR24] = 0x068,
106 [MIB_SDR25] = 0x06c,
107 [MIB_SDR27] = 0x074,
108 [MIB_SDR28] = 0x078,
109 [MIB_SDR29] = 0x07c,
110 [MIB_SDRVEC] = 0x080,
111 [MIB_SDR31] = 0x084,
112 [MIB_SDR32] = 0x088,
113 [MIB_SDRMUBF] = 0x090,
114 [MIB_DR8] = 0x0c0,
115 [MIB_DR9] = 0x0c4,
116 [MIB_DR11] = 0x0cc,
117 [MIB_MB_SDR0] = 0x100,
118 [MIB_MB_SDR1] = 0x104,
119 [TX_AGG_CNT] = 0x0a8,
120 [TX_AGG_CNT2] = 0x164,
121 [MIB_ARNG] = 0x4b8,
122 [WTBLON_TOP_WDUCR] = 0x0,
123 [WTBL_UPDATE] = 0x030,
124 [PLE_FL_Q_EMPTY] = 0x0b0,
125 [PLE_FL_Q_CTRL] = 0x1b0,
126 [PLE_AC_QEMPTY] = 0x500,
127 [PLE_FREEPG_CNT] = 0x100,
128 [PLE_FREEPG_HEAD_TAIL] = 0x104,
129 [PLE_PG_HIF_GROUP] = 0x110,
130 [PLE_HIF_PG_INFO] = 0x114,
131 [AC_OFFSET] = 0x040,
132 [ETBF_PAR_RPT0] = 0x068,
136 [TMAC_CDTR] = 0x0c8,
137 [TMAC_ODTR] = 0x0cc,
138 [TMAC_ATCR] = 0x00c,
139 [TMAC_TRCR0] = 0x010,
140 [TMAC_ICR0] = 0x014,
141 [TMAC_ICR1] = 0x018,
142 [TMAC_CTCR0] = 0x114,
143 [TMAC_TFCR0] = 0x0e4,
144 [MDP_BNRCFR0] = 0x090,
145 [MDP_BNRCFR1] = 0x094,
146 [ARB_DRNGR0] = 0x1e0,
147 [ARB_SCR] = 0x000,
148 [RMAC_MIB_AIRTIME14] = 0x0398,
149 [AGG_AWSCR0] = 0x030,
150 [AGG_PCR0] = 0x040,
151 [AGG_ACR0] = 0x054,
152 [AGG_ACR4] = 0x05c,
153 [AGG_MRCR] = 0x068,
154 [AGG_ATCR1] = 0x1a8,
155 [AGG_ATCR3] = 0x080,
156 [LPON_UTTR0] = 0x360,
157 [LPON_UTTR1] = 0x364,
158 [LPON_FRCR] = 0x37c,
159 [MIB_SDR3] = 0x698,
160 [MIB_SDR4] = 0x788,
161 [MIB_SDR5] = 0x780,
162 [MIB_SDR7] = 0x5a8,
163 [MIB_SDR8] = 0x78c,
164 [MIB_SDR9] = 0x024,
165 [MIB_SDR10] = 0x76c,
166 [MIB_SDR11] = 0x790,
167 [MIB_SDR12] = 0x558,
168 [MIB_SDR13] = 0x560,
169 [MIB_SDR14] = 0x564,
170 [MIB_SDR15] = 0x568,
171 [MIB_SDR16] = 0x7fc,
172 [MIB_SDR17] = 0x800,
173 [MIB_SDR18] = 0x030,
174 [MIB_SDR19] = 0x5ac,
175 [MIB_SDR20] = 0x5b0,
176 [MIB_SDR21] = 0x5b4,
177 [MIB_SDR22] = 0x770,
178 [MIB_SDR23] = 0x774,
179 [MIB_SDR24] = 0x778,
180 [MIB_SDR25] = 0x77c,
181 [MIB_SDR27] = 0x080,
182 [MIB_SDR28] = 0x084,
183 [MIB_SDR29] = 0x650,
184 [MIB_SDRVEC] = 0x5a8,
185 [MIB_SDR31] = 0x55c,
186 [MIB_SDR32] = 0x7a8,
187 [MIB_SDRMUBF] = 0x7ac,
188 [MIB_DR8] = 0x56c,
189 [MIB_DR9] = 0x570,
190 [MIB_DR11] = 0x574,
191 [MIB_MB_SDR0] = 0x688,
192 [MIB_MB_SDR1] = 0x690,
193 [TX_AGG_CNT] = 0x7dc,
194 [TX_AGG_CNT2] = 0x7ec,
195 [MIB_ARNG] = 0x0b0,
196 [WTBLON_TOP_WDUCR] = 0x200,
197 [WTBL_UPDATE] = 0x230,
198 [PLE_FL_Q_EMPTY] = 0x360,
199 [PLE_FL_Q_CTRL] = 0x3e0,
200 [PLE_AC_QEMPTY] = 0x600,
201 [PLE_FREEPG_CNT] = 0x380,
202 [PLE_FREEPG_HEAD_TAIL] = 0x384,
203 [PLE_PG_HIF_GROUP] = 0x00c,
204 [PLE_HIF_PG_INFO] = 0x388,
205 [AC_OFFSET] = 0x080,
206 [ETBF_PAR_RPT0] = 0x100,
210 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
211 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure regs) */
212 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
213 { 0x54000000, 0x02000, 0x01000 }, /* WFDMA PCIE0 MCU DMA0 */
214 { 0x55000000, 0x03000, 0x01000 }, /* WFDMA PCIE0 MCU DMA1 */
215 { 0x58000000, 0x06000, 0x01000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
216 { 0x59000000, 0x07000, 0x01000 }, /* WFDMA PCIE1 MCU DMA1 */
217 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
218 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
219 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
220 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
221 { 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
222 { 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
223 { 0x820cc000, 0x0e000, 0x02000 }, /* WF_UMAC_TOP (PP) */
224 { 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
225 { 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
226 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
227 { 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
228 { 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
229 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
230 { 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
231 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
232 { 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
233 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
234 { 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
235 { 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
236 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
237 { 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
238 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
239 { 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
240 { 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
241 { 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
242 { 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
243 { 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
244 { 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
245 { 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
246 { 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
247 { 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
248 { 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
249 { 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
250 { 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
251 { 0x0, 0x0, 0x0 }, /* imply end of search */
255 { 0x54000000, 0x02000, 0x01000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
256 { 0x55000000, 0x03000, 0x01000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
257 { 0x56000000, 0x04000, 0x01000 }, /* WFDMA_2 (Reserved) */
258 { 0x57000000, 0x05000, 0x01000 }, /* WFDMA_3 (MCU wrap CR) */
259 { 0x58000000, 0x06000, 0x01000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */
260 { 0x59000000, 0x07000, 0x01000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */
261 { 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
262 { 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
263 { 0x820cc000, 0x0e000, 0x02000 }, /* WF_UMAC_TOP (PP) */
264 { 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
265 { 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
266 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
267 { 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
268 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
269 { 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
270 { 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
271 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
272 { 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
273 { 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
274 { 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
275 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
276 { 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
277 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
278 { 0x820ca000, 0x26000, 0x02000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
279 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
280 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
281 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure cr) */
282 { 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
283 { 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
284 { 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
285 { 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
286 { 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
287 { 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
288 { 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
289 { 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
290 { 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
291 { 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
292 { 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
293 { 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
294 { 0x820c4000, 0xa8000, 0x01000 }, /* WF_LMAC_TOP (WF_UWTBL ) */
295 { 0x820b0000, 0xae000, 0x01000 }, /* [APB2] WFSYS_ON */
296 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
297 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
298 { 0x0, 0x0, 0x0 }, /* imply end of search */
302 { 0x54000000, 0x402000, 0x01000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
303 { 0x55000000, 0x403000, 0x01000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
304 { 0x56000000, 0x404000, 0x01000 }, /* WFDMA_2 (Reserved) */
305 { 0x57000000, 0x405000, 0x01000 }, /* WFDMA_3 (MCU wrap CR) */
306 { 0x58000000, 0x406000, 0x01000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */
307 { 0x59000000, 0x407000, 0x01000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */
308 { 0x820c0000, 0x408000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
309 { 0x820c8000, 0x40c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
310 { 0x820cc000, 0x40e000, 0x02000 }, /* WF_UMAC_TOP (PP) */
311 { 0x820e0000, 0x420000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
312 { 0x820e1000, 0x420400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
313 { 0x820e2000, 0x420800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
314 { 0x820e3000, 0x420c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
315 { 0x820e4000, 0x421000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
316 { 0x820e5000, 0x421400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
317 { 0x820ce000, 0x421c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
318 { 0x820e7000, 0x421e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
319 { 0x820cf000, 0x422000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
320 { 0x820e9000, 0x423400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
321 { 0x820ea000, 0x424000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
322 { 0x820eb000, 0x424200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
323 { 0x820ec000, 0x424600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
324 { 0x820ed000, 0x424800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
325 { 0x820ca000, 0x426000, 0x02000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
326 { 0x820d0000, 0x430000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
327 { 0x00400000, 0x480000, 0x10000 }, /* WF_MCU_SYSRAM */
328 { 0x00410000, 0x490000, 0x10000 }, /* WF_MCU_SYSRAM */
329 { 0x820f0000, 0x4a0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
330 { 0x820f1000, 0x4a0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
331 { 0x820f2000, 0x4a0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
332 { 0x820f3000, 0x4a0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
333 { 0x820f4000, 0x4a1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
334 { 0x820f5000, 0x4a1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
335 { 0x820f7000, 0x4a1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
336 { 0x820f9000, 0x4a3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
337 { 0x820fa000, 0x4a4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
338 { 0x820fb000, 0x4a4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
339 { 0x820fc000, 0x4a4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
340 { 0x820fd000, 0x4a4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
341 { 0x820c4000, 0x4a8000, 0x01000 }, /* WF_LMAC_TOP (WF_UWTBL ) */
342 { 0x820b0000, 0x4ae000, 0x01000 }, /* [APB2] WFSYS_ON */
343 { 0x80020000, 0x4b0000, 0x10000 }, /* WF_TOP_MISC_OFF */
344 { 0x81020000, 0x4c0000, 0x10000 }, /* WF_TOP_MISC_ON */
345 { 0x89000000, 0x4d0000, 0x01000 }, /* WF_MCU_CFG_ON */
346 { 0x89010000, 0x4d1000, 0x01000 }, /* WF_MCU_CIRQ */
347 { 0x89020000, 0x4d2000, 0x01000 }, /* WF_MCU_GPT */
348 { 0x89030000, 0x4d3000, 0x01000 }, /* WF_MCU_WDT */
349 { 0x80010000, 0x4d4000, 0x01000 }, /* WF_AXIDMA */
350 { 0x0, 0x0, 0x0 }, /* imply end of search */
389 u32 ofs = is_mt7986(&dev->mt76) ? 0x400000 : 0; in mt7915_reg_map_l2()
411 if (addr < 0x100000) in __mt7915_reg_addr()
419 for (i = 0; i < dev->reg.map_size; i++) { in __mt7915_reg_addr()
486 case 0x7915: in mt7915_mmio_init()
492 case 0x7906: in mt7915_mmio_init()
498 case 0x7986: in mt7915_mmio_init()
520 (mt76_rr(dev, MT_HW_REV) & 0xff); in mt7915_mmio_init()
523 return 0; in mt7915_mmio_init()
562 mtk_wed_device_irq_set_mask(wed, 0); in mt7915_irq_tasklet()
565 mt76_wr(dev, MT_INT_MASK_CSR, 0); in mt7915_irq_tasklet()
567 mt76_wr(dev, MT_INT1_MASK_CSR, 0); in mt7915_irq_tasklet()
630 mtk_wed_device_irq_set_mask(wed, 0); in mt7915_irq_handler()
632 mt76_wr(dev, MT_INT_MASK_CSR, 0); in mt7915_irq_handler()
634 mt76_wr(dev, MT_INT1_MASK_CSR, 0); in mt7915_irq_handler()
708 return 0; in mt7915_init()