37 	mt76x2_adjust_high_lna_gain(dev, 4, gain_adj[0]);  in mt76x2_apply_gain_adj()
40 	mt76x2_adjust_agc_gain(dev, 8, gain_adj[0]);  in mt76x2_apply_gain_adj()
52 		pa_mode[0] = 0x010055ff;  in mt76x2_phy_set_txpower_regs()
53 		pa_mode[1] = 0x00550055;  in mt76x2_phy_set_txpower_regs()
55 		mt76_wr(dev, MT_TX_ALC_CFG_2, 0x35160a00);  in mt76x2_phy_set_txpower_regs()
56 		mt76_wr(dev, MT_TX_ALC_CFG_3, 0x35160a06);  in mt76x2_phy_set_txpower_regs()
59 			mt76_wr(dev, MT_RF_PA_MODE_ADJ0, 0x0000ec00);  in mt76x2_phy_set_txpower_regs()
60 			mt76_wr(dev, MT_RF_PA_MODE_ADJ1, 0x0000ec00);  in mt76x2_phy_set_txpower_regs()
62 			mt76_wr(dev, MT_RF_PA_MODE_ADJ0, 0xf4000200);  in mt76x2_phy_set_txpower_regs()
63 			mt76_wr(dev, MT_RF_PA_MODE_ADJ1, 0xfa000200);  in mt76x2_phy_set_txpower_regs()
66 		pa_mode[0] = 0x0000ffff;  in mt76x2_phy_set_txpower_regs()
67 		pa_mode[1] = 0x00ff00ff;  in mt76x2_phy_set_txpower_regs()
70 			mt76_wr(dev, MT_TX_ALC_CFG_2, 0x2f0f0400);  in mt76x2_phy_set_txpower_regs()
71 			mt76_wr(dev, MT_TX_ALC_CFG_3, 0x2f0f0476);  in mt76x2_phy_set_txpower_regs()
73 			mt76_wr(dev, MT_TX_ALC_CFG_2, 0x1b0f0400);  in mt76x2_phy_set_txpower_regs()
74 			mt76_wr(dev, MT_TX_ALC_CFG_3, 0x1b0f0476);  in mt76x2_phy_set_txpower_regs()
78 			pa_mode_adj = 0x04000000;  in mt76x2_phy_set_txpower_regs()
80 			pa_mode_adj = 0;  in mt76x2_phy_set_txpower_regs()
86 	mt76_wr(dev, MT_BB_PA_MODE_CFG0, pa_mode[0]);  in mt76x2_phy_set_txpower_regs()
88 	mt76_wr(dev, MT_RF_PA_MODE_CFG0, pa_mode[0]);  in mt76x2_phy_set_txpower_regs()
95 			val = 0x3c3c023c;  in mt76x2_phy_set_txpower_regs()
97 			val = 0x363c023c;  in mt76x2_phy_set_txpower_regs()
101 		mt76_wr(dev, MT_TX_ALC_CFG_4, 0x00001818);  in mt76x2_phy_set_txpower_regs()
104 			u32 val = 0x0f3c3c3c;  in mt76x2_phy_set_txpower_regs()
108 			mt76_wr(dev, MT_TX_ALC_CFG_4, 0x00000606);  in mt76x2_phy_set_txpower_regs()
110 			mt76_wr(dev, MT_TX0_RF_GAIN_CORR, 0x383c023c);  in mt76x2_phy_set_txpower_regs()
111 			mt76_wr(dev, MT_TX1_RF_GAIN_CORR, 0x24282e28);  in mt76x2_phy_set_txpower_regs()
112 			mt76_wr(dev, MT_TX_ALC_CFG_4, 0);  in mt76x2_phy_set_txpower_regs()
122 	s8 ret = 0;  in mt76x2_get_min_rate_power()
124 	for (i = 0; i < sizeof(r->all); i++) {  in mt76x2_get_min_rate_power()
142 	int txp_0, txp_1, delta = 0;  in mt76x2_phy_set_txpower()
160 	txp_0 = txp.chain[0].target_power + txp.chain[0].delta + delta;  in mt76x2_phy_set_txpower()
164 	if (gain < 0) {  in mt76x2_phy_set_txpower()
168 	} else if (gain > 0x2f) {  in mt76x2_phy_set_txpower()
169 		base_power -= gain - 0x2f;  in mt76x2_phy_set_txpower()
170 		txp_0 = 0x2f;  in mt76x2_phy_set_txpower()
171 		txp_1 = 0x2f;  in mt76x2_phy_set_txpower()
176 	dev->target_power_delta[0] = txp_0 - txp.chain[0].target_power;  in mt76x2_phy_set_txpower()
177 	dev->target_power_delta[1] = txp_1 - txp.chain[0].target_power;  in mt76x2_phy_set_txpower()
190 		cfg0 = bw ? 0x000b0c01 : 0x00101101;  in mt76x2_configure_tx_delay()
191 		cfg1 = 0x00011414;  in mt76x2_configure_tx_delay()
193 		cfg0 = bw ? 0x000b0b01 : 0x00101001;  in mt76x2_configure_tx_delay()
194 		cfg1 = 0x00021414;  in mt76x2_configure_tx_delay()
214 		t.cal_mode = BIT(0);  in mt76x2_phy_tssi_compensate()
228 		t.slope0 = txp.chain[0].tssi_slope;  in mt76x2_phy_tssi_compensate()
229 		t.offset0 = txp.chain[0].tssi_offset;  in mt76x2_phy_tssi_compensate()
250 	gain_val[0] = dev->cal.agc_gain_cur[0] - dev->cal.agc_gain_adjust;  in mt76x2_phy_set_gain_val()
253 	val = 0x1836 << 16;  in mt76x2_phy_set_gain_val()
256 		val = 0x1e42 << 16;  in mt76x2_phy_set_gain_val()
261 		val = 0x0f36 << 16;  in mt76x2_phy_set_gain_val()
263 	val |= 0xf8;  in mt76x2_phy_set_gain_val()
266 		val | FIELD_PREP(MT_BBP_AGC_GAIN, gain_val[0]));  in mt76x2_phy_set_gain_val()
290 	gain_change = dev->cal.low_gain < 0 ||  in mt76x2_phy_update_channel_gain()
301 		mt76_wr(dev, MT_BBP(RXO, 14), 0x00560211);  in mt76x2_phy_update_channel_gain()
302 		val = mt76_rr(dev, MT_BBP(AGC, 26)) & ~0xf;  in mt76x2_phy_update_channel_gain()
304 			val |= 0x3;  in mt76x2_phy_update_channel_gain()
306 			val |= 0x5;  in mt76x2_phy_update_channel_gain()
309 		mt76_wr(dev, MT_BBP(RXO, 14), 0x00560423);  in mt76x2_phy_update_channel_gain()
317 	agc_37 = 0x2121262c;  in mt76x2_phy_update_channel_gain()
319 		agc_35 = 0x11111516;  in mt76x2_phy_update_channel_gain()
321 		agc_35 = agc_37 = 0x08080808;  in mt76x2_phy_update_channel_gain()
323 		agc_35 = 0x10101014;  in mt76x2_phy_update_channel_gain()
325 		agc_35 = 0x11111116;  in mt76x2_phy_update_channel_gain()
328 		mt76_wr(dev, MT_BBP(RXO, 18), 0xf000a990);  in mt76x2_phy_update_channel_gain()
329 		mt76_wr(dev, MT_BBP(AGC, 35), 0x08080808);  in mt76x2_phy_update_channel_gain()
330 		mt76_wr(dev, MT_BBP(AGC, 37), 0x08080808);  in mt76x2_phy_update_channel_gain()
332 		dev->cal.agc_gain_adjust = 0;  in mt76x2_phy_update_channel_gain()
334 		mt76_wr(dev, MT_BBP(RXO, 18), 0xf000a991);  in mt76x2_phy_update_channel_gain()
335 		gain_delta = 0;  in mt76x2_phy_update_channel_gain()
342 	dev->cal.agc_gain_cur[0] = gain[0] - gain_delta;  in mt76x2_phy_update_channel_gain()