Lines Matching full:31
35 #define MT_TXD0_Q_IDX GENMASK(31, 25)
40 #define MT_TXD1_LONG_FORMAT BIT(31)
52 #define MT_TXD2_FIX_RATE BIT(31)
68 #define MT_TXD3_SN_VALID BIT(31)
82 #define MT_TXD4_PN_LOW GENMASK(31, 0)
84 #define MT_TXD5_PN_HIGH GENMASK(31, 16)
92 #define MT_TXD6_TX_IBF BIT(31)
104 #define MT_TXD7_TXD_LEN GENMASK(31, 30)
126 #define MT_TXS0_FIXED_RATE BIT(31)
145 #define MT_TXS1_SEQNO GENMASK(31, 20)
150 #define MT_TXS2_BF_STATUS GENMASK(31, 30)
156 #define MT_TXS3_PID GENMASK(31, 24)
159 #define MT_TXS4_TIMESTAMP GENMASK(31, 0)
163 #define MT_TXS5_MPDU_TX_CNT GENMASK(31, 23)
165 #define MT_TXS6_MPDU_FAIL_CNT GENMASK(31, 23)
167 #define MT_TXS7_MPDU_RETRY_CNT GENMASK(31, 23)
186 #define MT_RXD1_NORMAL_SEC_DONE BIT(31)
206 #define MT_RXD2_NORMAL_BF_REPORT BIT(31)
220 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
242 #define MT_RXD3_NORMAL_VLAN2ETH BIT(31)
246 #define MT_RXD6_TA_LO GENMASK(31, 16)
248 #define MT_RXD7_TA_HI GENMASK(31, 0)
251 #define MT_RXD8_QOS_CTL GENMASK(31, 16)
253 #define MT_RXD9_HT_CONTROL GENMASK(31, 0)
262 #define MT_PRXV_HE_RU_ALLOC_L GENMASK(31, 28)
272 #define MT_PRXV_RCPI3 GENMASK(31, 24)
287 #define MT_CRXV_HE_UPLINK BIT(31)
292 #define MT_CRXV_HE_RU3 GENMASK(31, 24)
307 #define MT_CRXV_FOE_LO GENMASK(31, 19)