Lines Matching +full:24 +full:- +full:bit
1 /* SPDX-License-Identifier: ISC */
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
35 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
37 #define MT_RXD1_MID_AMSDU_FRAME BIT(1)
38 #define MT_RXD1_LAST_AMSDU_FRAME BIT(0)
39 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
40 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
44 #define MT_RXD1_NORMAL_BEACON_UC BIT(5)
45 #define MT_RXD1_NORMAL_BEACON_MC BIT(4)
46 #define MT_RXD1_NORMAL_BF_REPORT BIT(3)
49 #define MT_RXD1_NORMAL_MCAST BIT(2)
50 #define MT_RXD1_NORMAL_U2M BIT(1)
51 #define MT_RXD1_NORMAL_HTC_VLD BIT(0)
53 #define MT_RXD2_NORMAL_NON_AMPDU BIT(31)
54 #define MT_RXD2_NORMAL_NON_AMPDU_SUB BIT(30)
55 #define MT_RXD2_NORMAL_NDATA BIT(29)
56 #define MT_RXD2_NORMAL_NULL_FRAME BIT(28)
57 #define MT_RXD2_NORMAL_FRAG BIT(27)
58 #define MT_RXD2_NORMAL_INT_FRAME BIT(26)
59 #define MT_RXD2_NORMAL_HDR_TRANS_ERROR BIT(25)
60 #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
61 #define MT_RXD2_NORMAL_AMSDU_ERR BIT(23)
62 #define MT_RXD2_NORMAL_LEN_MISMATCH BIT(22)
63 #define MT_RXD2_NORMAL_TKIP_MIC_ERR BIT(21)
64 #define MT_RXD2_NORMAL_ICV_ERR BIT(20)
65 #define MT_RXD2_NORMAL_CLM BIT(19)
66 #define MT_RXD2_NORMAL_CM BIT(18)
67 #define MT_RXD2_NORMAL_FCS_ERR BIT(17)
68 #define MT_RXD2_NORMAL_SW_BIT BIT(16)
74 #define MT_RXD3_NORMAL_PF_MODE BIT(29)
77 #define MT_RXD3_NORMAL_MAGIC_PKT BIT(13)
79 #define MT_RXD3_NORMAL_CLS BIT(10)
80 #define MT_RXD3_NORMAL_PATTERN_DROP BIT(9)
81 #define MT_RXD3_NORMAL_TSF_COMPARE_LOSS BIT(8)
91 #define MT_RXV1_ACID_DET_H BIT(31)
92 #define MT_RXV1_ACID_DET_L BIT(30)
93 #define MT_RXV1_VHTA2_B8_B3 GENMASK(29, 24)
95 #define MT_RXV1_HT_NO_SOUND BIT(21)
96 #define MT_RXV1_HT_SMOOTH BIT(20)
97 #define MT_RXV1_HT_SHORT_GI BIT(19)
98 #define MT_RXV1_HT_AGGR BIT(18)
99 #define MT_RXV1_VHTA1_B22 BIT(17)
103 #define MT_RXV1_HT_AD_CODE BIT(9)
107 #define MT_RXV2_SEL_ANT BIT(31)
108 #define MT_RXV2_VALID_BIT BIT(30)
113 #define MT_RXV3_WB_RSSI GENMASK(31, 24)
116 #define MT_RXV4_RCPI3 GENMASK(31, 24)
123 #define MT_RXV6_NF3 GENMASK(31, 24)
162 #define MT_CT_INFO_APPLY_TXD BIT(0)
163 #define MT_CT_INFO_COPY_HOST_TXD_ALL BIT(1)
164 #define MT_CT_INFO_MGMT_FRAME BIT(2)
165 #define MT_CT_INFO_NONE_CIPHER_FRAME BIT(3)
166 #define MT_CT_INFO_HSR2_TX BIT(4)
168 #define MT_TXD0_P_IDX BIT(31)
170 #define MT_TXD0_UDP_TCP_SUM BIT(24)
171 #define MT_TXD0_IP_SUM BIT(23)
176 #define MT_TXD1_PKT_FMT GENMASK(25, 24)
178 #define MT_TXD1_AMSDU BIT(20)
179 #define MT_TXD1_UNXV BIT(19)
181 #define MT_TXD1_TXD_LEN BIT(16)
182 #define MT_TXD1_LONG_FORMAT BIT(15)
187 #define MT_TXD2_FIX_RATE BIT(31)
188 #define MT_TXD2_TIMING_MEASURE BIT(30)
189 #define MT_TXD2_BA_DISABLE BIT(29)
190 #define MT_TXD2_POWER_OFFSET GENMASK(28, 24)
193 #define MT_TXD2_HTC_VLD BIT(13)
194 #define MT_TXD2_DURATION BIT(12)
195 #define MT_TXD2_BIP BIT(11)
196 #define MT_TXD2_MULTICAST BIT(10)
197 #define MT_TXD2_RTS BIT(9)
198 #define MT_TXD2_SOUNDING BIT(8)
199 #define MT_TXD2_NDPA BIT(7)
200 #define MT_TXD2_NDP BIT(6)
204 #define MT_TXD3_SN_VALID BIT(31)
205 #define MT_TXD3_PN_VALID BIT(30)
209 #define MT_TXD3_PROTECT_FRAME BIT(1)
210 #define MT_TXD3_NO_ACK BIT(0)
215 #define MT_TXD5_SW_POWER_MGMT BIT(13)
216 #define MT_TXD5_DA_SELECT BIT(11)
217 #define MT_TXD5_TX_STATUS_HOST BIT(10)
218 #define MT_TXD5_TX_STATUS_MCU BIT(9)
219 #define MT_TXD5_TX_STATUS_FMT BIT(8)
222 #define MT_TXD6_FIXED_RATE BIT(31)
223 #define MT_TXD6_SGI BIT(30)
224 #define MT_TXD6_LDPC BIT(29)
225 #define MT_TXD6_TX_BF BIT(28)
228 #define MT_TXD6_DYN_BW BIT(3)
229 #define MT_TXD6_FIXED_BW BIT(2)
232 /* MT7663 DW7 HW-AMSDU */
233 #define MT_TXD7_HW_AMSDU_CAP BIT(30)
237 #define MT_TXD7_SPE_IDX_SLE BIT(10)
242 #define MT_TX_RATE_STBC BIT(11)
249 #define MT_TXS0_PID GENMASK(31, 24)
250 #define MT_TXS0_BA_ERROR BIT(22)
251 #define MT_TXS0_PS_FLAG BIT(21)
252 #define MT_TXS0_TXOP_TIMEOUT BIT(20)
253 #define MT_TXS0_BIP_ERROR BIT(19)
255 #define MT_TXS0_QUEUE_TIMEOUT BIT(18)
256 #define MT_TXS0_RTS_TIMEOUT BIT(17)
257 #define MT_TXS0_ACK_TIMEOUT BIT(16)
260 #define MT_TXS0_TX_STATUS_HOST BIT(15)
261 #define MT_TXS0_TX_STATUS_MCU BIT(14)
262 #define MT_TXS0_TXS_FORMAT BIT(13)
263 #define MT_TXS0_FIXED_RATE BIT(12)
269 #define MT_TXS1_I_TXBF BIT(13)
270 #define MT_TXS1_E_TXBF BIT(12)
272 #define MT_TXS1_AMPDU BIT(8)
273 #define MT_TXS1_ACKED_MPDU BIT(7)
276 #define MT_TXS2_WCID GENMASK(31, 24)
281 #define MT_TXS3_TX_COUNT GENMASK(28, 24)
290 #define MT_TXS5_F0_FRONT_TIME GENMASK(24, 0)
295 #define MT_TXS6_F1_RCPI_3 GENMASK(31, 24)