Lines Matching +full:20 +full:us
64 #define MT_RXD2_NORMAL_ICV_ERR BIT(20)
96 #define MT_RXV1_HT_SMOOTH BIT(20)
111 #define MT_RXV2_LENGTH GENMASK(20, 0)
178 #define MT_TXD1_AMSDU BIT(20)
234 #define MT_TXD7_TYPE GENMASK(21, 20)
252 #define MT_TXS0_TXOP_TIMEOUT BIT(20)
266 #define MT_TXS1_ANT_ID GENMASK(31, 20)
301 u32 max_width; /* us */
304 u32 min_stgr_pri; /* us */
305 u32 max_stgr_pri; /* us */
306 u32 min_cr_pri; /* us */
307 u32 max_cr_pri; /* us */