Lines Matching full:31
7 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
27 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
41 #define MT_RXD2_NORMAL_NON_AMPDU BIT(31)
61 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
72 #define MT_RXV1_VHTA1_B5_B4 GENMASK(31, 30)
86 #define MT_RXV2_VHTA1_B16_B6 GENMASK(31, 21)
89 #define MT_RXV3_F_AGC1_CAL_GAIN GENMASK(31, 29)
100 #define MT_RXV4_F_AGC_CAL_GAIN GENMASK(31, 29)
107 #define MT_RXV5_LTF_SNR0 GENMASK(31, 26)
130 #define MT_TXD0_P_IDX BIT(31)
139 #define MT_TXD1_OWN_MAC GENMASK(31, 26)
149 #define MT_TXD2_FIX_RATE BIT(31)
166 #define MT_TXD3_SN_VALID BIT(31)
172 #define MT_TXD4_PN_LOW GENMASK(31, 0)
174 #define MT_TXD5_PN_HIGH GENMASK(31, 16)
183 #define MT_TXD6_SGI BIT(31)
201 #define MT_TXS0_ANTENNA GENMASK(31, 26)
219 #define MT_TXS1_F0_TIMESTAMP GENMASK(31, 0)
229 #define MT_TXS3_WCID GENMASK(31, 24)
233 #define MT_TXS4_LAST_TX_RATE GENMASK(31, 29)