Lines Matching +full:0 +full:- +full:19
1 /* SPDX-License-Identifier: ISC */
6 #define MT_RXD0_LENGTH GENMASK(15, 0)
18 PKT_TYPE_TXS = 0,
39 #define MT_RXD1_NORMAL_HTC_VLD BIT(0)
53 #define MT_RXD2_NORMAL_CLM BIT(19)
59 #define MT_RXD2_NORMAL_WLAN_IDX GENMASK(7, 0)
63 #define MT_RXD3_NORMAL_CLS_BITMAP GENMASK(28, 19)
70 #define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)
76 #define MT_RXV1_HT_SHORT_GI BIT(19)
84 #define MT_RXV1_TX_RATE GENMASK(6, 0)
87 #define MT_RXV2_LENGTH GENMASK(20, 0)
92 #define MT_RXV3_F_AGC0_CAL_GAIN GENMASK(19, 17)
98 #define MT_RXV3_VHTA1_B21_B17 GENMASK(4, 0)
103 #define MT_RXV4_F_AGC_LPF_GAIN_X GENMASK(19, 16)
105 #define MT_RXV4_IB_RSSI0 GENMASK(7, 0)
108 #define MT_RXV5_LTF_PROC_TIME GENMASK(25, 19)
112 #define MT_RXV5_F_AGC_LNA_GAIN_1 GENMASK(1, 0)
119 #define MT_RXV6_NF0 GENMASK(7, 0)
137 #define MT_TXD0_TX_BYTES GENMASK(15, 0)
142 #define MT_TXD1_NO_ACK BIT(19)
147 #define MT_TXD1_WLAN_IDX GENMASK(7, 0)
164 #define MT_TXD2_SUB_TYPE GENMASK(3, 0)
172 #define MT_TXD4_PN_LOW GENMASK(31, 0)
181 #define MT_TXD5_PID GENMASK(7, 0)
194 #define MT_TXD6_FIXED_RATE BIT(0)
199 #define MT_TX_RATE_IDX GENMASK(5, 0)
206 #define MT_TXS0_BIP_ERROR BIT(19)
217 #define MT_TXS0_TX_RATE GENMASK(11, 0)
219 #define MT_TXS1_F0_TIMESTAMP GENMASK(31, 0)
222 #define MT_TXS1_F1_NOISE_0 GENMASK(7, 0)
224 #define MT_TXS2_F0_FRONT_TIME GENMASK(24, 0)
227 #define MT_TXS2_F1_RCPI_0 GENMASK(7, 0)
231 #define MT_TXS3_TX_DELAY GENMASK(15, 0)
239 #define MT_TXS4_F0_SEQNO GENMASK(11, 0)
240 #define MT_TXS4_F1_TSSI GENMASK(11, 0)