Lines Matching +full:rates +full:- +full:cck
1 // SPDX-License-Identifier: ISC
42 memset(dev->mt76.aggr_stats, 0, sizeof(dev->mt76.aggr_stats)); in mt7603_mac_reset_counters()
47 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | in mt7603_mac_set_timing() local
51 int offset = 3 * dev->coverage_class; in mt7603_mac_set_timing()
54 bool is_5ghz = dev->mphy.chandef.chan->band == NL80211_BAND_5GHZ; in mt7603_mac_set_timing()
67 mt76_wr(dev, MT_TIMEOUT_CCK, cck + reg_offset); in mt7603_mac_set_timing()
73 FIELD_PREP(MT_IFS_SLOT, dev->slottime)); in mt7603_mac_set_timing()
75 if (dev->slottime < 20 || is_5ghz) in mt7603_mac_set_timing()
218 u32 addr = mt7603_wtbl1_addr(sta->wcid.idx); in mt7603_wtbl_set_smps()
220 if (sta->smps == enabled) in mt7603_wtbl_set_smps()
224 sta->smps = enabled; in mt7603_wtbl_set_smps()
230 int idx = sta->wcid.idx; in mt7603_wtbl_set_ps()
233 spin_lock_bh(&dev->ps_lock); in mt7603_wtbl_set_ps()
235 if (sta->ps == enabled) in mt7603_wtbl_set_ps()
255 sta->ps = enabled; in mt7603_wtbl_set_ps()
258 spin_unlock_bh(&dev->ps_lock); in mt7603_wtbl_set_ps()
321 struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv; in mt7603_wtbl_update_cap()
322 int idx = msta->wcid.idx; in mt7603_wtbl_update_cap()
329 ampdu_density = sta->deflink.ht_cap.ampdu_density; in mt7603_wtbl_update_cap()
336 sta->deflink.ht_cap.ampdu_factor) | in mt7603_wtbl_update_cap()
338 sta->deflink.ht_cap.ampdu_density) | in mt7603_wtbl_update_cap()
341 if (sta->deflink.ht_cap.cap) in mt7603_wtbl_update_cap()
343 if (sta->deflink.vht_cap.cap) in mt7603_wtbl_update_cap()
352 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) in mt7603_wtbl_update_cap()
354 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) in mt7603_wtbl_update_cap()
384 for (i = 7; i > 0; i--) { in mt7603_mac_tx_ba_reset()
415 spin_lock_bh(&dev->sta_poll_lock); in mt7603_mac_sta_poll()
416 if (list_empty(&dev->sta_poll_list)) { in mt7603_mac_sta_poll()
417 spin_unlock_bh(&dev->sta_poll_lock); in mt7603_mac_sta_poll()
421 msta = list_first_entry(&dev->sta_poll_list, struct mt7603_sta, in mt7603_mac_sta_poll()
423 list_del_init(&msta->poll_list); in mt7603_mac_sta_poll()
424 spin_unlock_bh(&dev->sta_poll_lock); in mt7603_mac_sta_poll()
426 addr = mt7603_wtbl4_addr(msta->wcid.idx); in mt7603_mac_sta_poll()
428 u32 airtime_last = msta->tx_airtime_ac[i]; in mt7603_mac_sta_poll()
430 msta->tx_airtime_ac[i] = mt76_rr(dev, addr + i * 8); in mt7603_mac_sta_poll()
431 airtime[i] = msta->tx_airtime_ac[i] - airtime_last; in mt7603_mac_sta_poll()
435 if (msta->tx_airtime_ac[i] & BIT(22)) in mt7603_mac_sta_poll()
440 mt7603_wtbl_update(dev, msta->wcid.idx, in mt7603_mac_sta_poll()
442 memset(msta->tx_airtime_ac, 0, in mt7603_mac_sta_poll()
443 sizeof(msta->tx_airtime_ac)); in mt7603_mac_sta_poll()
446 if (!msta->wcid.sta) in mt7603_mac_sta_poll()
451 struct mt76_queue *q = dev->mphy.q_tx[i]; in mt7603_mac_sta_poll()
452 u8 qidx = q->hw_idx; in mt7603_mac_sta_poll()
468 spin_lock_bh(&dev->mt76.cc_lock); in mt7603_mac_sta_poll()
469 dev->mphy.chan_state->cc_tx += total_airtime; in mt7603_mac_sta_poll()
470 spin_unlock_bh(&dev->mt76.cc_lock); in mt7603_mac_sta_poll()
482 wcid = rcu_dereference(dev->mt76.wcid[idx]); in mt7603_rx_get_wcid()
486 if (!wcid->sta) in mt7603_rx_get_wcid()
490 if (!sta->vif) in mt7603_rx_get_wcid()
493 return &sta->vif->sta.wcid; in mt7603_rx_get_wcid()
499 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; in mt7603_mac_fill_rx()
502 __le32 *rxd = (__le32 *)skb->data; in mt7603_mac_fill_rx()
515 sband = (i & 1) ? &dev->mphy.sband_5g.sband : &dev->mphy.sband_2g.sband; in mt7603_mac_fill_rx()
519 status->wcid = mt7603_rx_get_wcid(dev, idx, unicast); in mt7603_mac_fill_rx()
521 status->band = sband->band; in mt7603_mac_fill_rx()
522 if (i < sband->n_channels) in mt7603_mac_fill_rx()
523 status->freq = sband->channels[i].center_freq; in mt7603_mac_fill_rx()
526 status->flag |= RX_FLAG_FAILED_FCS_CRC; in mt7603_mac_fill_rx()
529 status->flag |= RX_FLAG_MMIC_ERROR; in mt7603_mac_fill_rx()
533 status->flag |= RX_FLAG_ONLY_MONITOR; in mt7603_mac_fill_rx()
537 status->flag |= RX_FLAG_DECRYPTED; in mt7603_mac_fill_rx()
538 status->flag |= RX_FLAG_IV_STRIPPED; in mt7603_mac_fill_rx()
539 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; in mt7603_mac_fill_rx()
545 return -EINVAL; in mt7603_mac_fill_rx()
547 if (!sband->channels) in mt7603_mac_fill_rx()
548 return -EINVAL; in mt7603_mac_fill_rx()
553 if ((u8 *)rxd - skb->data >= skb->len) in mt7603_mac_fill_rx()
554 return -EINVAL; in mt7603_mac_fill_rx()
559 if (status->flag & RX_FLAG_DECRYPTED) { in mt7603_mac_fill_rx()
571 status->iv[0] = data[5]; in mt7603_mac_fill_rx()
572 status->iv[1] = data[4]; in mt7603_mac_fill_rx()
573 status->iv[2] = data[3]; in mt7603_mac_fill_rx()
574 status->iv[3] = data[2]; in mt7603_mac_fill_rx()
575 status->iv[4] = data[1]; in mt7603_mac_fill_rx()
576 status->iv[5] = data[0]; in mt7603_mac_fill_rx()
584 if ((u8 *)rxd - skb->data >= skb->len) in mt7603_mac_fill_rx()
585 return -EINVAL; in mt7603_mac_fill_rx()
588 status->timestamp = le32_to_cpu(rxd[0]); in mt7603_mac_fill_rx()
589 status->flag |= RX_FLAG_MACTIME_START; in mt7603_mac_fill_rx()
593 status->flag |= RX_FLAG_AMPDU_DETAILS; in mt7603_mac_fill_rx()
595 /* all subframes of an A-MPDU have the same timestamp */ in mt7603_mac_fill_rx()
596 if (dev->rx_ampdu_ts != status->timestamp) { in mt7603_mac_fill_rx()
597 if (!++dev->ampdu_ref) in mt7603_mac_fill_rx()
598 dev->ampdu_ref++; in mt7603_mac_fill_rx()
600 dev->rx_ampdu_ts = status->timestamp; in mt7603_mac_fill_rx()
602 status->ampdu_ref = dev->ampdu_ref; in mt7603_mac_fill_rx()
606 if ((u8 *)rxd - skb->data >= skb->len) in mt7603_mac_fill_rx()
607 return -EINVAL; in mt7603_mac_fill_rx()
612 bool cck = false; in mt7603_mac_fill_rx() local
617 cck = true; in mt7603_mac_fill_rx()
620 i = mt76_get_rate(&dev->mt76, sband, i, cck); in mt7603_mac_fill_rx()
624 status->encoding = RX_ENC_HT; in mt7603_mac_fill_rx()
626 return -EINVAL; in mt7603_mac_fill_rx()
629 return -EINVAL; in mt7603_mac_fill_rx()
633 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; in mt7603_mac_fill_rx()
635 status->enc_flags |= RX_ENC_FLAG_LDPC; in mt7603_mac_fill_rx()
637 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * in mt7603_mac_fill_rx()
640 status->rate_idx = i; in mt7603_mac_fill_rx()
642 status->chains = dev->mphy.antenna_mask; in mt7603_mac_fill_rx()
643 status->chain_signal[0] = FIELD_GET(MT_RXV4_IB_RSSI0, rxdg3) + in mt7603_mac_fill_rx()
644 dev->rssi_offset[0]; in mt7603_mac_fill_rx()
645 status->chain_signal[1] = FIELD_GET(MT_RXV4_IB_RSSI1, rxdg3) + in mt7603_mac_fill_rx()
646 dev->rssi_offset[1]; in mt7603_mac_fill_rx()
649 status->bw = RATE_INFO_BW_40; in mt7603_mac_fill_rx()
652 if ((u8 *)rxd - skb->data >= skb->len) in mt7603_mac_fill_rx()
653 return -EINVAL; in mt7603_mac_fill_rx()
655 return -EINVAL; in mt7603_mac_fill_rx()
658 skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad); in mt7603_mac_fill_rx()
666 hdr = (struct ieee80211_hdr *)skb->data; in mt7603_mac_fill_rx()
667 if (!status->wcid || !ieee80211_is_data_qos(hdr->frame_control)) in mt7603_mac_fill_rx()
670 status->aggr = unicast && in mt7603_mac_fill_rx()
671 !ieee80211_is_qos_nullfunc(hdr->frame_control); in mt7603_mac_fill_rx()
672 status->qos_ctl = *ieee80211_get_qos_ctl(hdr); in mt7603_mac_fill_rx()
673 status->seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); in mt7603_mac_fill_rx()
686 if (rate->flags & IEEE80211_TX_RC_MCS) { in mt7603_mac_tx_rate_val()
687 rate_idx = rate->idx; in mt7603_mac_tx_rate_val()
688 nss = 1 + (rate->idx >> 3); in mt7603_mac_tx_rate_val()
690 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD) in mt7603_mac_tx_rate_val()
692 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) in mt7603_mac_tx_rate_val()
696 int band = dev->mphy.chandef.chan->band; in mt7603_mac_tx_rate_val()
700 r = &mt76_hw(dev)->wiphy->bands[band]->bitrates[rate->idx]; in mt7603_mac_tx_rate_val()
701 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) in mt7603_mac_tx_rate_val()
702 val = r->hw_value_short; in mt7603_mac_tx_rate_val()
704 val = r->hw_value; in mt7603_mac_tx_rate_val()
721 struct ieee80211_tx_rate *rates) in mt7603_wtbl_set_rates() argument
724 int wcid = sta->wcid.idx; in mt7603_wtbl_set_rates()
727 int n_rates = sta->n_rates; in mt7603_wtbl_set_rates()
739 rates[i] = rates[n_rates - 1]; in mt7603_wtbl_set_rates()
741 rateset = !(sta->rate_set_tsf & BIT(0)); in mt7603_wtbl_set_rates()
742 memcpy(sta->rateset[rateset].rates, rates, in mt7603_wtbl_set_rates()
743 sizeof(sta->rateset[rateset].rates)); in mt7603_wtbl_set_rates()
745 sta->rateset[rateset].probe_rate = *probe_rate; in mt7603_wtbl_set_rates()
746 ref = &sta->rateset[rateset].probe_rate; in mt7603_wtbl_set_rates()
748 sta->rateset[rateset].probe_rate.idx = -1; in mt7603_wtbl_set_rates()
749 ref = &sta->rateset[rateset].rates[0]; in mt7603_wtbl_set_rates()
752 rates = sta->rateset[rateset].rates; in mt7603_wtbl_set_rates()
753 for (i = 0; i < ARRAY_SIZE(sta->rateset[rateset].rates); i++) { in mt7603_wtbl_set_rates()
761 if ((ref->flags ^ rates[i].flags) & IEEE80211_TX_RC_SHORT_GI) in mt7603_wtbl_set_rates()
762 rates[i].flags ^= IEEE80211_TX_RC_SHORT_GI; in mt7603_wtbl_set_rates()
765 if (rates[i].idx != rates[k].idx) in mt7603_wtbl_set_rates()
767 if ((rates[i].flags ^ rates[k].flags) & in mt7603_wtbl_set_rates()
771 if (!rates[i].idx) in mt7603_wtbl_set_rates()
774 rates[i].idx--; in mt7603_wtbl_set_rates()
781 val[0] = mt7603_mac_tx_rate_val(dev, &rates[0], stbc, &bw); in mt7603_wtbl_set_rates()
797 val[1] = mt7603_mac_tx_rate_val(dev, &rates[1], stbc, &bw); in mt7603_wtbl_set_rates()
803 val[2] = mt7603_mac_tx_rate_val(dev, &rates[2], stbc, &bw); in mt7603_wtbl_set_rates()
809 val[3] = mt7603_mac_tx_rate_val(dev, &rates[3], stbc, &bw); in mt7603_wtbl_set_rates()
814 bw_idx ? bw_idx - 1 : 7); in mt7603_wtbl_set_rates()
835 sta->rate_set_tsf = (mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0)) | rateset; in mt7603_wtbl_set_rates()
842 if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET)) in mt7603_wtbl_set_rates()
845 sta->rate_count = 2 * MT7603_RATE_RETRY * n_rates; in mt7603_wtbl_set_rates()
846 sta->wcid.tx_info |= MT_WCID_TX_INFO_SET; in mt7603_wtbl_set_rates()
856 if (key->keylen > 32) in mt7603_mac_get_key_info()
859 memcpy(key_data, key->key, key->keylen); in mt7603_mac_get_key_info()
861 switch (key->cipher) { in mt7603_mac_get_key_info()
868 memcpy(key_data + 16, key->key + 24, 8); in mt7603_mac_get_key_info()
869 memcpy(key_data + 24, key->key + 16, 8); in mt7603_mac_get_key_info()
888 return -EOPNOTSUPP; in mt7603_wtbl_set_key()
891 addr += key->keyidx * 16; in mt7603_wtbl_set_key()
900 mt76_rmw_field(dev, addr, MT_WTBL1_W0_KEY_IDX, key->keyidx); in mt7603_wtbl_set_key()
913 struct ieee80211_tx_rate *rate = &info->control.rates[0]; in mt7603_mac_write_txwi()
914 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; in mt7603_mac_write_txwi()
915 struct ieee80211_bar *bar = (struct ieee80211_bar *)skb->data; in mt7603_mac_write_txwi()
916 struct ieee80211_vif *vif = info->control.vif; in mt7603_mac_write_txwi()
917 struct mt76_queue *q = dev->mphy.q_tx[qid]; in mt7603_mac_write_txwi()
923 u16 fc = le16_to_cpu(hdr->frame_control); in mt7603_mac_write_txwi()
930 mvif = (struct mt7603_vif *)vif->drv_priv; in mt7603_mac_write_txwi()
931 vif_idx = mvif->idx; in mt7603_mac_write_txwi()
937 struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv; in mt7603_mac_write_txwi()
939 tx_count = msta->rate_count; in mt7603_mac_write_txwi()
943 wlan_idx = wcid->idx; in mt7603_mac_write_txwi()
950 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) | in mt7603_mac_write_txwi()
951 FIELD_PREP(MT_TXD0_Q_IDX, q->hw_idx); in mt7603_mac_write_txwi()
957 skb->priority & IEEE80211_QOS_CTL_TID_MASK) | in mt7603_mac_write_txwi()
964 if (info->flags & IEEE80211_TX_CTL_NO_ACK) in mt7603_mac_write_txwi()
970 is_multicast_ether_addr(hdr->addr1)); in mt7603_mac_write_txwi()
973 if (!(info->flags & IEEE80211_TX_CTL_AMPDU)) in mt7603_mac_write_txwi()
984 if (rate->idx >= 0 && rate->count && in mt7603_mac_write_txwi()
985 !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) { in mt7603_mac_write_txwi()
986 bool stbc = info->flags & IEEE80211_TX_CTL_STBC; in mt7603_mac_write_txwi()
996 if (rate->flags & IEEE80211_TX_RC_SHORT_GI) in mt7603_mac_write_txwi()
999 if (!(rate->flags & IEEE80211_TX_RC_MCS)) in mt7603_mac_write_txwi()
1002 tx_count = rate->count; in mt7603_mac_write_txwi()
1012 if (ieee80211_is_data_qos(hdr->frame_control)) in mt7603_mac_write_txwi()
1013 seqno = le16_to_cpu(hdr->seq_ctrl); in mt7603_mac_write_txwi()
1014 else if (ieee80211_is_back_req(hdr->frame_control)) in mt7603_mac_write_txwi()
1015 seqno = le16_to_cpu(bar->start_seq_num); in mt7603_mac_write_txwi()
1024 u64 pn = atomic64_inc_return(&key->tx_pn); in mt7603_mac_write_txwi()
1043 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb); in mt7603_tx_prepare_skb()
1044 struct ieee80211_key_conf *key = info->control.hw_key; in mt7603_tx_prepare_skb()
1048 wcid = &dev->global_sta.wcid; in mt7603_tx_prepare_skb()
1051 msta = (struct mt7603_sta *)sta->drv_priv; in mt7603_tx_prepare_skb()
1053 if ((info->flags & (IEEE80211_TX_CTL_NO_PS_BUFFER | in mt7603_tx_prepare_skb()
1055 (info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE)) in mt7603_tx_prepare_skb()
1058 mt76_tx_check_agg_ssn(sta, tx_info->skb); in mt7603_tx_prepare_skb()
1061 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb); in mt7603_tx_prepare_skb()
1063 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) { in mt7603_tx_prepare_skb()
1064 spin_lock_bh(&dev->mt76.lock); in mt7603_tx_prepare_skb()
1065 mt7603_wtbl_set_rates(dev, msta, &info->control.rates[0], in mt7603_tx_prepare_skb()
1066 msta->rates); in mt7603_tx_prepare_skb()
1067 msta->rate_probe = true; in mt7603_tx_prepare_skb()
1068 spin_unlock_bh(&dev->mt76.lock); in mt7603_tx_prepare_skb()
1071 mt7603_mac_write_txwi(dev, txwi_ptr, tx_info->skb, qid, wcid, in mt7603_tx_prepare_skb()
1092 bool cck = false; in mt7603_fill_txs() local
1098 fixed_rate = info->status.rates[0].count; in mt7603_fill_txs()
1099 probe = !!(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE); in mt7603_fill_txs()
1117 info->flags |= IEEE80211_TX_STAT_ACK; in mt7603_fill_txs()
1119 info->status.ampdu_len = 1; in mt7603_fill_txs()
1120 info->status.ampdu_ack_len = !!(info->flags & in mt7603_fill_txs()
1123 if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU)) in mt7603_fill_txs()
1124 info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU; in mt7603_fill_txs()
1126 first_idx = max_t(int, 0, last_idx - (count - 1) / MT7603_RATE_RETRY); in mt7603_fill_txs()
1129 info->status.rates[0].count = count; in mt7603_fill_txs()
1134 rate_set_tsf = READ_ONCE(sta->rate_set_tsf); in mt7603_fill_txs()
1135 rs_idx = !((u32)(le32_get_bits(txs_data[1], MT_TXS1_F0_TIMESTAMP) - in mt7603_fill_txs()
1138 rs = &sta->rateset[rs_idx]; in mt7603_fill_txs()
1140 if (!first_idx && rs->probe_rate.idx >= 0) { in mt7603_fill_txs()
1141 info->status.rates[0] = rs->probe_rate; in mt7603_fill_txs()
1143 spin_lock_bh(&dev->mt76.lock); in mt7603_fill_txs()
1144 if (sta->rate_probe) { in mt7603_fill_txs()
1146 sta->rates); in mt7603_fill_txs()
1147 sta->rate_probe = false; in mt7603_fill_txs()
1149 spin_unlock_bh(&dev->mt76.lock); in mt7603_fill_txs()
1151 info->status.rates[0] = rs->rates[first_idx / 2]; in mt7603_fill_txs()
1153 info->status.rates[0].count = 0; in mt7603_fill_txs()
1159 cur_rate = &rs->rates[idx / 2]; in mt7603_fill_txs()
1161 count -= cur_count; in mt7603_fill_txs()
1163 if (idx && (cur_rate->idx != info->status.rates[i].idx || in mt7603_fill_txs()
1164 cur_rate->flags != info->status.rates[i].flags)) { in mt7603_fill_txs()
1166 if (i == ARRAY_SIZE(info->status.rates)) { in mt7603_fill_txs()
1167 i--; in mt7603_fill_txs()
1171 info->status.rates[i] = *cur_rate; in mt7603_fill_txs()
1172 info->status.rates[i].count = 0; in mt7603_fill_txs()
1175 info->status.rates[i].count += cur_count; in mt7603_fill_txs()
1179 final_rate_flags = info->status.rates[i].flags; in mt7603_fill_txs()
1183 cck = true; in mt7603_fill_txs()
1186 if (dev->mphy.chandef.chan->band == NL80211_BAND_5GHZ) in mt7603_fill_txs()
1187 sband = &dev->mphy.sband_5g.sband; in mt7603_fill_txs()
1189 sband = &dev->mphy.sband_2g.sband; in mt7603_fill_txs()
1191 final_rate = mt76_get_rate(&dev->mt76, sband, final_rate, in mt7603_fill_txs()
1192 cck); in mt7603_fill_txs()
1206 info->status.rates[i].idx = final_rate; in mt7603_fill_txs()
1207 info->status.rates[i].flags = final_rate_flags; in mt7603_fill_txs()
1216 struct mt76_dev *mdev = &dev->mt76; in mt7603_mac_add_txs_skb()
1223 trace_mac_txdone(mdev, sta->wcid.idx, pid); in mt7603_mac_add_txs_skb()
1226 skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list); in mt7603_mac_add_txs_skb()
1231 info->status.rates[0].count = 0; in mt7603_mac_add_txs_skb()
1232 info->status.rates[0].idx = -1; in mt7603_mac_add_txs_skb()
1263 wcid = rcu_dereference(dev->mt76.wcid[wcidx]); in mt7603_mac_add_txs()
1270 if (list_empty(&msta->poll_list)) { in mt7603_mac_add_txs()
1271 spin_lock_bh(&dev->sta_poll_lock); in mt7603_mac_add_txs()
1272 list_add_tail(&msta->poll_list, &dev->sta_poll_list); in mt7603_mac_add_txs()
1273 spin_unlock_bh(&dev->sta_poll_lock); in mt7603_mac_add_txs()
1292 struct sk_buff *skb = e->skb; in mt7603_tx_complete_skb()
1294 if (!e->txwi) { in mt7603_tx_complete_skb()
1299 dev->tx_hang_check = 0; in mt7603_tx_complete_skb()
1300 mt76_tx_complete_skb(mdev, e->wcid, skb); in mt7603_tx_complete_skb()
1315 if (!dev->reset_cause[RESET_CAUSE_RESET_FAILED]) in mt7603_pse_reset()
1324 dev->reset_cause[RESET_CAUSE_RESET_FAILED]++; in mt7603_pse_reset()
1327 dev->reset_cause[RESET_CAUSE_RESET_FAILED] = 0; in mt7603_pse_reset()
1331 if (dev->reset_cause[RESET_CAUSE_RESET_FAILED] >= 3) in mt7603_pse_reset()
1332 dev->reset_cause[RESET_CAUSE_RESET_FAILED] = 0; in mt7603_pse_reset()
1410 int beacon_int = dev->mt76.beacon_int; in mt7603_mac_watchdog_reset()
1411 u32 mask = dev->mt76.mmio.irqmask; in mt7603_mac_watchdog_reset()
1414 ieee80211_stop_queues(dev->mt76.hw); in mt7603_mac_watchdog_reset()
1415 set_bit(MT76_RESET, &dev->mphy.state); in mt7603_mac_watchdog_reset()
1418 mt76_txq_schedule_all(&dev->mphy); in mt7603_mac_watchdog_reset()
1420 mt76_worker_disable(&dev->mt76.tx_worker); in mt7603_mac_watchdog_reset()
1421 tasklet_disable(&dev->mt76.pre_tbtt_tasklet); in mt7603_mac_watchdog_reset()
1422 napi_disable(&dev->mt76.napi[0]); in mt7603_mac_watchdog_reset()
1423 napi_disable(&dev->mt76.napi[1]); in mt7603_mac_watchdog_reset()
1424 napi_disable(&dev->mt76.tx_napi); in mt7603_mac_watchdog_reset()
1426 mutex_lock(&dev->mt76.mutex); in mt7603_mac_watchdog_reset()
1428 mt7603_beacon_set_timer(dev, -1, 0); in mt7603_mac_watchdog_reset()
1430 if (dev->reset_cause[RESET_CAUSE_RESET_FAILED] || in mt7603_mac_watchdog_reset()
1431 dev->cur_reset_cause == RESET_CAUSE_RX_PSE_BUSY || in mt7603_mac_watchdog_reset()
1432 dev->cur_reset_cause == RESET_CAUSE_BEACON_STUCK || in mt7603_mac_watchdog_reset()
1433 dev->cur_reset_cause == RESET_CAUSE_TX_HANG) in mt7603_mac_watchdog_reset()
1436 if (dev->reset_cause[RESET_CAUSE_RESET_FAILED]) in mt7603_mac_watchdog_reset()
1452 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], true); in mt7603_mac_watchdog_reset()
1454 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true); in mt7603_mac_watchdog_reset()
1456 mt76_for_each_q_rx(&dev->mt76, i) { in mt7603_mac_watchdog_reset()
1460 mt76_tx_status_check(&dev->mt76, true); in mt7603_mac_watchdog_reset()
1469 clear_bit(MT76_RESET, &dev->mphy.state); in mt7603_mac_watchdog_reset()
1470 mutex_unlock(&dev->mt76.mutex); in mt7603_mac_watchdog_reset()
1472 mt76_worker_enable(&dev->mt76.tx_worker); in mt7603_mac_watchdog_reset()
1474 tasklet_enable(&dev->mt76.pre_tbtt_tasklet); in mt7603_mac_watchdog_reset()
1475 mt7603_beacon_set_timer(dev, -1, beacon_int); in mt7603_mac_watchdog_reset()
1478 napi_enable(&dev->mt76.tx_napi); in mt7603_mac_watchdog_reset()
1479 napi_schedule(&dev->mt76.tx_napi); in mt7603_mac_watchdog_reset()
1481 napi_enable(&dev->mt76.napi[0]); in mt7603_mac_watchdog_reset()
1482 napi_schedule(&dev->mt76.napi[0]); in mt7603_mac_watchdog_reset()
1484 napi_enable(&dev->mt76.napi[1]); in mt7603_mac_watchdog_reset()
1485 napi_schedule(&dev->mt76.napi[1]); in mt7603_mac_watchdog_reset()
1488 ieee80211_wake_queues(dev->mt76.hw); in mt7603_mac_watchdog_reset()
1489 mt76_txq_schedule_all(&dev->mphy); in mt7603_mac_watchdog_reset()
1538 q = dev->mphy.q_tx[i]; in mt7603_tx_hang()
1540 if (!q->queued) in mt7603_tx_hang()
1543 prev_dma_idx = dev->tx_dma_idx[i]; in mt7603_tx_hang()
1544 dma_idx = readl(&q->regs->dma_idx); in mt7603_tx_hang()
1545 dev->tx_dma_idx[i] = dma_idx; in mt7603_tx_hang()
1548 dma_idx != readl(&q->regs->cpu_idx)) in mt7603_tx_hang()
1580 if (dev->reset_test == cause + 1) { in mt7603_watchdog_check()
1581 dev->reset_test = 0; in mt7603_watchdog_check()
1597 dev->cur_reset_cause = cause; in mt7603_watchdog_check()
1598 dev->reset_cause[cause]++; in mt7603_watchdog_check()
1604 struct mt7603_dev *dev = container_of(mphy->dev, struct mt7603_dev, mt76); in mt7603_update_channel()
1607 state = mphy->chan_state; in mt7603_update_channel()
1608 state->cc_busy += mt76_rr(dev, MT_MIB_STAT_CCA); in mt7603_update_channel()
1616 if (val == dev->ed_strict_mode) in mt7603_edcca_set_strict()
1619 dev->ed_strict_mode = val; in mt7603_edcca_set_strict()
1622 if (!dev->ed_monitor) in mt7603_edcca_set_strict()
1627 if (dev->ed_monitor && !dev->ed_strict_mode) in mt7603_edcca_set_strict()
1635 dev->ed_monitor && !dev->ed_strict_mode); in mt7603_edcca_set_strict()
1647 if (!dev->ed_monitor) in mt7603_edcca_check()
1652 rssi0 -= 256; in mt7603_edcca_check()
1654 if (dev->mphy.antenna_mask & BIT(1)) { in mt7603_edcca_check()
1657 rssi1 -= 256; in mt7603_edcca_check()
1662 if (max(rssi0, rssi1) >= -40 && in mt7603_edcca_check()
1663 dev->ed_strong_signal < MT7603_EDCCA_BLOCK_TH) in mt7603_edcca_check()
1664 dev->ed_strong_signal++; in mt7603_edcca_check()
1665 else if (dev->ed_strong_signal > 0) in mt7603_edcca_check()
1666 dev->ed_strong_signal--; in mt7603_edcca_check()
1671 active = ktime_to_us(ktime_sub(cur_time, dev->ed_time)); in mt7603_edcca_check()
1672 dev->ed_time = cur_time; in mt7603_edcca_check()
1678 if (dev->ed_trigger < 0) in mt7603_edcca_check()
1679 dev->ed_trigger = 0; in mt7603_edcca_check()
1680 dev->ed_trigger++; in mt7603_edcca_check()
1682 if (dev->ed_trigger > 0) in mt7603_edcca_check()
1683 dev->ed_trigger = 0; in mt7603_edcca_check()
1684 dev->ed_trigger--; in mt7603_edcca_check()
1687 if (dev->ed_trigger > MT7603_EDCCA_BLOCK_TH || in mt7603_edcca_check()
1688 dev->ed_strong_signal < MT7603_EDCCA_BLOCK_TH / 2) { in mt7603_edcca_check()
1690 } else if (dev->ed_trigger < -MT7603_EDCCA_BLOCK_TH) { in mt7603_edcca_check()
1694 if (dev->ed_trigger > MT7603_EDCCA_BLOCK_TH) in mt7603_edcca_check()
1695 dev->ed_trigger = MT7603_EDCCA_BLOCK_TH; in mt7603_edcca_check()
1696 else if (dev->ed_trigger < -MT7603_EDCCA_BLOCK_TH) in mt7603_edcca_check()
1697 dev->ed_trigger = -MT7603_EDCCA_BLOCK_TH; in mt7603_edcca_check()
1710 u32 agc0 = dev->agc0, agc3 = dev->agc3; in mt7603_adjust_sensitivity()
1713 if (!dev->sensitivity || dev->sensitivity < -100) { in mt7603_adjust_sensitivity()
1714 dev->sensitivity = 0; in mt7603_adjust_sensitivity()
1715 } else if (dev->sensitivity <= -84) { in mt7603_adjust_sensitivity()
1716 adj = 7 + (dev->sensitivity + 92) / 2; in mt7603_adjust_sensitivity()
1722 } else if (dev->sensitivity <= -72) { in mt7603_adjust_sensitivity()
1723 adj = 7 + (dev->sensitivity + 80) / 2; in mt7603_adjust_sensitivity()
1732 if (dev->sensitivity > -54) in mt7603_adjust_sensitivity()
1733 dev->sensitivity = -54; in mt7603_adjust_sensitivity()
1735 adj = 7 + (dev->sensitivity + 80) / 2; in mt7603_adjust_sensitivity()
1761 if (!dev->dynamic_sensitivity) in mt7603_false_cca_check()
1772 dev->false_cca_ofdm = pd_ofdm - mdrdy_ofdm; in mt7603_false_cca_check()
1773 dev->false_cca_cck = pd_cck - mdrdy_cck; in mt7603_false_cca_check()
1777 min_signal = mt76_get_min_avg_rssi(&dev->mt76, false); in mt7603_false_cca_check()
1779 dev->sensitivity = 0; in mt7603_false_cca_check()
1780 dev->last_cca_adj = jiffies; in mt7603_false_cca_check()
1784 min_signal -= 15; in mt7603_false_cca_check()
1786 false_cca = dev->false_cca_ofdm + dev->false_cca_cck; in mt7603_false_cca_check()
1788 dev->sensitivity < -100 + dev->sensitivity_limit) { in mt7603_false_cca_check()
1789 if (!dev->sensitivity) in mt7603_false_cca_check()
1790 dev->sensitivity = -92; in mt7603_false_cca_check()
1792 dev->sensitivity += 2; in mt7603_false_cca_check()
1793 dev->last_cca_adj = jiffies; in mt7603_false_cca_check()
1795 time_after(jiffies, dev->last_cca_adj + 10 * HZ)) { in mt7603_false_cca_check()
1796 dev->last_cca_adj = jiffies; in mt7603_false_cca_check()
1797 if (!dev->sensitivity) in mt7603_false_cca_check()
1800 dev->sensitivity -= 2; in mt7603_false_cca_check()
1803 if (dev->sensitivity && dev->sensitivity > min_signal) { in mt7603_false_cca_check()
1804 dev->sensitivity = min_signal; in mt7603_false_cca_check()
1805 dev->last_cca_adj = jiffies; in mt7603_false_cca_check()
1819 mt76_tx_status_check(&dev->mt76, false); in mt7603_mac_work()
1821 mutex_lock(&dev->mt76.mutex); in mt7603_mac_work()
1823 dev->mphy.mac_work_count++; in mt7603_mac_work()
1824 mt76_update_survey(&dev->mphy); in mt7603_mac_work()
1830 dev->mt76.aggr_stats[idx++] += val & 0xffff; in mt7603_mac_work()
1831 dev->mt76.aggr_stats[idx++] += val >> 16; in mt7603_mac_work()
1834 if (dev->mphy.mac_work_count == 10) in mt7603_mac_work()
1837 if (mt7603_watchdog_check(dev, &dev->rx_pse_check, in mt7603_mac_work()
1840 mt7603_watchdog_check(dev, &dev->beacon_check, in mt7603_mac_work()
1843 mt7603_watchdog_check(dev, &dev->tx_hang_check, in mt7603_mac_work()
1846 mt7603_watchdog_check(dev, &dev->tx_dma_check, in mt7603_mac_work()
1849 mt7603_watchdog_check(dev, &dev->rx_dma_check, in mt7603_mac_work()
1852 mt7603_watchdog_check(dev, &dev->mcu_hang, in mt7603_mac_work()
1855 dev->reset_cause[RESET_CAUSE_RESET_FAILED]) { in mt7603_mac_work()
1856 dev->beacon_check = 0; in mt7603_mac_work()
1857 dev->tx_dma_check = 0; in mt7603_mac_work()
1858 dev->tx_hang_check = 0; in mt7603_mac_work()
1859 dev->rx_dma_check = 0; in mt7603_mac_work()
1860 dev->rx_pse_check = 0; in mt7603_mac_work()
1861 dev->mcu_hang = 0; in mt7603_mac_work()
1862 dev->rx_dma_idx = ~0; in mt7603_mac_work()
1863 memset(dev->tx_dma_idx, 0xff, sizeof(dev->tx_dma_idx)); in mt7603_mac_work()
1865 dev->mphy.mac_work_count = 0; in mt7603_mac_work()
1868 if (dev->mphy.mac_work_count >= 10) in mt7603_mac_work()
1869 dev->mphy.mac_work_count = 0; in mt7603_mac_work()
1871 mutex_unlock(&dev->mt76.mutex); in mt7603_mac_work()
1876 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, in mt7603_mac_work()