Lines Matching +full:cmdq +full:- +full:sync
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2007-2015, 2018-2022 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
18 #include "iwl-drv.h"
19 #include "iwl-trans.h"
20 #include "iwl-csr.h"
21 #include "iwl-prph.h"
22 #include "iwl-scd.h"
23 #include "iwl-agn-hw.h"
24 #include "fw/error-dump.h"
27 #include "mei/iwl-mei.h"
29 #include "iwl-fh.h"
30 #include "iwl-context-info-gen3.h"
43 struct pci_dev *pdev = trans_pcie->pci_dev; in iwl_trans_pcie_dump_regs()
47 if (trans_pcie->pcie_dbg_dumped_once) in iwl_trans_pcie_dump_regs()
64 prefix = (char *)buf + alloc_size - PREFIX_LEN; in iwl_trans_pcie_dump_regs()
92 if (!pdev->bus->self) in iwl_trans_pcie_dump_regs()
95 pdev = pdev->bus->self; in iwl_trans_pcie_dump_regs()
126 trans_pcie->pcie_dbg_dumped_once = 1; in iwl_trans_pcie_dump_regs()
133 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ in iwl_trans_pcie_sw_reset()
134 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in iwl_trans_pcie_sw_reset()
150 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_pcie_free_fw_monitor()
152 if (!fw_mon->size) in iwl_pcie_free_fw_monitor()
155 dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, in iwl_pcie_free_fw_monitor()
156 fw_mon->physical); in iwl_pcie_free_fw_monitor()
158 fw_mon->block = NULL; in iwl_pcie_free_fw_monitor()
159 fw_mon->physical = 0; in iwl_pcie_free_fw_monitor()
160 fw_mon->size = 0; in iwl_pcie_free_fw_monitor()
166 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_pcie_alloc_fw_monitor_block()
172 if (fw_mon->size) in iwl_pcie_alloc_fw_monitor_block()
175 for (power = max_power; power >= min_power; power--) { in iwl_pcie_alloc_fw_monitor_block()
177 block = dma_alloc_coherent(trans->dev, size, &physical, in iwl_pcie_alloc_fw_monitor_block()
193 "Sorry - debug buffer is only %luK while you requested %luK\n", in iwl_pcie_alloc_fw_monitor_block()
194 (unsigned long)BIT(power - 10), in iwl_pcie_alloc_fw_monitor_block()
195 (unsigned long)BIT(max_power - 10)); in iwl_pcie_alloc_fw_monitor_block()
197 fw_mon->block = block; in iwl_pcie_alloc_fw_monitor_block()
198 fw_mon->physical = physical; in iwl_pcie_alloc_fw_monitor_block()
199 fw_mon->size = size; in iwl_pcie_alloc_fw_monitor_block()
216 if (trans->dbg.fw_mon.size) in iwl_pcie_alloc_fw_monitor()
238 if (trans->cfg->apmg_not_supported) in iwl_pcie_set_pwr()
241 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) in iwl_pcie_set_pwr()
267 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); in iwl_pcie_apm_config()
268 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); in iwl_pcie_apm_config()
270 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); in iwl_pcie_apm_config()
271 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; in iwl_pcie_apm_config()
272 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", in iwl_pcie_apm_config()
274 trans->ltr_enabled ? "En" : "Dis"); in iwl_pcie_apm_config()
294 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) in iwl_pcie_apm_init()
310 * wake device's PCI Express link L1a -> L0s in iwl_pcie_apm_init()
317 /* Configure analog phase-lock-loop before activating to D0A */ in iwl_pcie_apm_init()
318 if (trans->trans_cfg->base_params->pll_cfg) in iwl_pcie_apm_init()
325 if (trans->cfg->host_interrupt_operation_mode) { in iwl_pcie_apm_init()
327 * This is a bit of an abuse - This is needed for 7260 / 3160 in iwl_pcie_apm_init()
332 * consumes slightly more power (100uA) - but allows to be sure in iwl_pcie_apm_init()
354 if (!trans->cfg->apmg_not_supported) { in iwl_pcie_apm_init()
359 /* Disable L1-Active */ in iwl_pcie_apm_init()
368 set_bit(STATUS_DEVICE_ENABLED, &trans->status); in iwl_pcie_apm_init()
445 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. in iwl_pcie_apm_lp_xtal_enable()
470 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { in iwl_pcie_apm_stop_master()
498 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) in iwl_pcie_apm_stop()
502 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) in iwl_pcie_apm_stop()
505 else if (trans->trans_cfg->device_family >= in iwl_pcie_apm_stop()
519 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); in iwl_pcie_apm_stop()
524 if (trans->cfg->lp_xtal_workaround) { in iwl_pcie_apm_stop()
533 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. in iwl_pcie_apm_stop()
544 spin_lock_bh(&trans_pcie->irq_lock); in iwl_pcie_nic_init()
546 spin_unlock_bh(&trans_pcie->irq_lock); in iwl_pcie_nic_init()
553 iwl_op_mode_nic_config(trans->op_mode); in iwl_pcie_nic_init()
563 return -ENOMEM; in iwl_pcie_nic_init()
566 if (trans->trans_cfg->base_params->shadow_reg_enable) { in iwl_pcie_nic_init()
598 /* Note: returns standard 0/-ERROR code */
610 trans->csme_own = false; in iwl_pcie_prepare_card_hw()
626 trans->csme_own = false; in iwl_pcie_prepare_card_hw()
633 trans->csme_own = true; in iwl_pcie_prepare_card_hw()
634 if (trans->trans_cfg->device_family != in iwl_pcie_prepare_card_hw()
639 return -EBUSY; in iwl_pcie_prepare_card_hw()
691 trans_pcie->ucode_write_complete = false; in iwl_pcie_load_firmware_chunk()
694 return -EIO; in iwl_pcie_load_firmware_chunk()
700 ret = wait_event_timeout(trans_pcie->ucode_write_waitq, in iwl_pcie_load_firmware_chunk()
701 trans_pcie->ucode_write_complete, 5 * HZ); in iwl_pcie_load_firmware_chunk()
705 return -ETIMEDOUT; in iwl_pcie_load_firmware_chunk()
716 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); in iwl_pcie_load_section()
722 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, in iwl_pcie_load_section()
727 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, in iwl_pcie_load_section()
730 return -ENOMEM; in iwl_pcie_load_section()
733 for (offset = 0; offset < section->len; offset += chunk_sz) { in iwl_pcie_load_section()
737 copy_size = min_t(u32, chunk_sz, section->len - offset); in iwl_pcie_load_section()
738 dst_addr = section->offset + offset; in iwl_pcie_load_section()
748 memcpy(v_addr, (const u8 *)section->data + offset, copy_size); in iwl_pcie_load_section()
764 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); in iwl_pcie_load_section()
785 for (i = *first_ucode_section; i < image->num_sec; i++) { in iwl_pcie_load_cpu_sections_8000()
789 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between in iwl_pcie_load_cpu_sections_8000()
791 * PAGING_SEPARATOR_SECTION delimiter - separate between in iwl_pcie_load_cpu_sections_8000()
794 if (!image->sec[i].data || in iwl_pcie_load_cpu_sections_8000()
795 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || in iwl_pcie_load_cpu_sections_8000()
796 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { in iwl_pcie_load_cpu_sections_8000()
803 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); in iwl_pcie_load_cpu_sections_8000()
819 if (trans->trans_cfg->use_tfh) { in iwl_pcie_load_cpu_sections_8000()
851 for (i = *first_ucode_section; i < image->num_sec; i++) { in iwl_pcie_load_cpu_sections()
855 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between in iwl_pcie_load_cpu_sections()
857 * PAGING_SEPARATOR_SECTION delimiter - separate between in iwl_pcie_load_cpu_sections()
860 if (!image->sec[i].data || in iwl_pcie_load_cpu_sections()
861 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || in iwl_pcie_load_cpu_sections()
862 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { in iwl_pcie_load_cpu_sections()
869 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); in iwl_pcie_load_cpu_sections()
883 &trans->dbg.fw_mon_cfg[alloc_id]; in iwl_pcie_apply_destination_ini()
889 if (le32_to_cpu(fw_mon_cfg->buf_location) == in iwl_pcie_apply_destination_ini()
899 if (le32_to_cpu(fw_mon_cfg->buf_location) != in iwl_pcie_apply_destination_ini()
901 !trans->dbg.fw_mon_ini[alloc_id].num_frags) in iwl_pcie_apply_destination_ini()
904 frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; in iwl_pcie_apply_destination_ini()
910 frag->physical >> MON_BUFF_SHIFT_VER2); in iwl_pcie_apply_destination_ini()
912 (frag->physical + frag->size - 256) >> in iwl_pcie_apply_destination_ini()
918 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; in iwl_pcie_apply_destination()
919 const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_pcie_apply_destination()
928 get_fw_dbg_mode_string(dest->monitor_mode)); in iwl_pcie_apply_destination()
930 if (dest->monitor_mode == EXTERNAL_MODE) in iwl_pcie_apply_destination()
931 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); in iwl_pcie_apply_destination()
935 for (i = 0; i < trans->dbg.n_dest_reg; i++) { in iwl_pcie_apply_destination()
936 u32 addr = le32_to_cpu(dest->reg_ops[i].addr); in iwl_pcie_apply_destination()
937 u32 val = le32_to_cpu(dest->reg_ops[i].val); in iwl_pcie_apply_destination()
939 switch (dest->reg_ops[i].op) { in iwl_pcie_apply_destination()
967 IWL_ERR(trans, "FW debug - unknown OP %d\n", in iwl_pcie_apply_destination()
968 dest->reg_ops[i].op); in iwl_pcie_apply_destination()
974 if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) { in iwl_pcie_apply_destination()
975 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), in iwl_pcie_apply_destination()
976 fw_mon->physical >> dest->base_shift); in iwl_pcie_apply_destination()
977 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) in iwl_pcie_apply_destination()
978 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), in iwl_pcie_apply_destination()
979 (fw_mon->physical + fw_mon->size - in iwl_pcie_apply_destination()
980 256) >> dest->end_shift); in iwl_pcie_apply_destination()
982 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), in iwl_pcie_apply_destination()
983 (fw_mon->physical + fw_mon->size) >> in iwl_pcie_apply_destination()
984 dest->end_shift); in iwl_pcie_apply_destination()
995 image->is_dual_cpus ? "Dual" : "Single"); in iwl_pcie_load_given_ucode()
1002 if (image->is_dual_cpus) { in iwl_pcie_load_given_ucode()
1033 image->is_dual_cpus ? "Dual" : "Single"); in iwl_pcie_load_given_ucode_8000()
1067 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_pcie_check_hw_rf_kill()
1071 set_bit(STATUS_RFKILL_HW, &trans->status); in iwl_pcie_check_hw_rf_kill()
1072 set_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_pcie_check_hw_rf_kill()
1074 clear_bit(STATUS_RFKILL_HW, &trans->status); in iwl_pcie_check_hw_rf_kill()
1075 if (trans_pcie->opmode_down) in iwl_pcie_check_hw_rf_kill()
1076 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_pcie_check_hw_rf_kill()
1079 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_pcie_check_hw_rf_kill()
1098 ((reg) == CSR_MSIX_FH_INT_MASK_AD ? -16 : \
1144 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; in iwl_pcie_map_non_rx_causes()
1148 * the first interrupt vector will serve non-RX and FBQ causes. in iwl_pcie_map_non_rx_causes()
1152 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in iwl_pcie_map_non_rx_causes()
1164 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; in iwl_pcie_map_rx_causes()
1168 * The first RX queue - fallback queue, which is designated for in iwl_pcie_map_rx_causes()
1171 * the other (N - 2) interrupt vectors. in iwl_pcie_map_rx_causes()
1174 for (idx = 1; idx < trans->num_rx_queues; idx++) { in iwl_pcie_map_rx_causes()
1176 MSIX_FH_INT_CAUSES_Q(idx - offset)); in iwl_pcie_map_rx_causes()
1182 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) in iwl_pcie_map_rx_causes()
1186 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) in iwl_pcie_map_rx_causes()
1192 struct iwl_trans *trans = trans_pcie->trans; in iwl_pcie_conf_msix_hw()
1194 if (!trans_pcie->msix_enabled) { in iwl_pcie_conf_msix_hw()
1195 if (trans->trans_cfg->mq_rx_supported && in iwl_pcie_conf_msix_hw()
1196 test_bit(STATUS_DEVICE_ENABLED, &trans->status)) in iwl_pcie_conf_msix_hw()
1206 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) in iwl_pcie_conf_msix_hw()
1223 struct iwl_trans *trans = trans_pcie->trans; in iwl_pcie_init_msix()
1227 if (!trans_pcie->msix_enabled) in iwl_pcie_init_msix()
1230 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); in iwl_pcie_init_msix()
1231 trans_pcie->fh_mask = trans_pcie->fh_init_mask; in iwl_pcie_init_msix()
1232 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); in iwl_pcie_init_msix()
1233 trans_pcie->hw_mask = trans_pcie->hw_init_mask; in iwl_pcie_init_msix()
1240 lockdep_assert_held(&trans_pcie->mutex); in _iwl_trans_pcie_stop_device()
1242 if (trans_pcie->is_down) in _iwl_trans_pcie_stop_device()
1245 trans_pcie->is_down = true; in _iwl_trans_pcie_stop_device()
1260 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { in _iwl_trans_pcie_stop_device()
1266 /* Power-down device's busmaster DMA clocks */ in _iwl_trans_pcie_stop_device()
1267 if (!trans->cfg->apmg_not_supported) { in _iwl_trans_pcie_stop_device()
1275 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in _iwl_trans_pcie_stop_device()
1285 /* re-take ownership to prevent other users from stealing the device */ in _iwl_trans_pcie_stop_device()
1289 * Upon stop, the IVAR table gets erased, so msi-x won't in _iwl_trans_pcie_stop_device()
1290 * work. This causes a bug in RF-KILL flows, since the interrupt in _iwl_trans_pcie_stop_device()
1302 * should be masked. Re-ACK all the interrupts here. in _iwl_trans_pcie_stop_device()
1307 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); in _iwl_trans_pcie_stop_device()
1308 clear_bit(STATUS_INT_ENABLED, &trans->status); in _iwl_trans_pcie_stop_device()
1309 clear_bit(STATUS_TPOWER_PMI, &trans->status); in _iwl_trans_pcie_stop_device()
1322 if (trans_pcie->msix_enabled) { in iwl_pcie_synchronize_irqs()
1325 for (i = 0; i < trans_pcie->alloc_vecs; i++) in iwl_pcie_synchronize_irqs()
1326 synchronize_irq(trans_pcie->msix_entries[i].vector); in iwl_pcie_synchronize_irqs()
1328 synchronize_irq(trans_pcie->pci_dev->irq); in iwl_pcie_synchronize_irqs()
1342 return -EIO; in iwl_trans_pcie_start_fw()
1350 * We enabled the RF-Kill interrupt and the handler may very in iwl_trans_pcie_start_fw()
1359 mutex_lock(&trans_pcie->mutex); in iwl_trans_pcie_start_fw()
1364 ret = -ERFKILL; in iwl_trans_pcie_start_fw()
1369 if (trans_pcie->is_down) { in iwl_trans_pcie_start_fw()
1372 ret = -EIO; in iwl_trans_pcie_start_fw()
1392 * by the RF-Kill interrupt (hence mask all the interrupt besides the in iwl_trans_pcie_start_fw()
1394 * RF-Kill switch is toggled, we will find out after having loaded in iwl_trans_pcie_start_fw()
1404 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) in iwl_trans_pcie_start_fw()
1409 /* re-check RF-Kill state since we may have missed the interrupt */ in iwl_trans_pcie_start_fw()
1412 ret = -ERFKILL; in iwl_trans_pcie_start_fw()
1415 mutex_unlock(&trans_pcie->mutex); in iwl_trans_pcie_start_fw()
1444 set_bit(STATUS_RFKILL_HW, &trans->status); in iwl_trans_pcie_handle_stop_rfkill()
1445 set_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_trans_pcie_handle_stop_rfkill()
1447 clear_bit(STATUS_RFKILL_HW, &trans->status); in iwl_trans_pcie_handle_stop_rfkill()
1448 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_trans_pcie_handle_stop_rfkill()
1459 iwl_op_mode_time_point(trans->op_mode, in iwl_trans_pcie_stop_device()
1463 mutex_lock(&trans_pcie->mutex); in iwl_trans_pcie_stop_device()
1464 trans_pcie->opmode_down = true; in iwl_trans_pcie_stop_device()
1465 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_trans_pcie_stop_device()
1468 mutex_unlock(&trans_pcie->mutex); in iwl_trans_pcie_stop_device()
1476 lockdep_assert_held(&trans_pcie->mutex); in iwl_trans_pcie_rf_kill()
1480 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { in iwl_trans_pcie_rf_kill()
1481 if (trans->trans_cfg->gen2) in iwl_trans_pcie_rf_kill()
1510 * reset TX queues -- some of their registers reset during S3 in iwl_pcie_d3_complete_suspend()
1525 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) { in iwl_pcie_d3_handshake()
1529 } else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { in iwl_pcie_d3_handshake()
1539 ret = wait_event_timeout(trans_pcie->sx_waitq, in iwl_pcie_d3_handshake()
1540 trans_pcie->sx_complete, 2 * HZ); in iwl_pcie_d3_handshake()
1543 trans_pcie->sx_complete = false; in iwl_pcie_d3_handshake()
1548 return -ETIMEDOUT; in iwl_pcie_d3_handshake()
1598 * Also enables interrupts - none will happen as in iwl_trans_pcie_d3_resume()
1603 if (!trans_pcie->msix_enabled) in iwl_trans_pcie_d3_resume()
1649 if (!cfg_trans->mq_rx_supported) in iwl_pcie_set_interrupt_capa()
1652 if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000) in iwl_pcie_set_interrupt_capa()
1657 trans_pcie->msix_entries[i].entry = i; in iwl_pcie_set_interrupt_capa()
1659 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, in iwl_pcie_set_interrupt_capa()
1664 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", in iwl_pcie_set_interrupt_capa()
1668 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; in iwl_pcie_set_interrupt_capa()
1671 "MSI-X enabled. %d interrupt vectors were allocated\n", in iwl_pcie_set_interrupt_capa()
1681 if (num_irqs <= max_irqs - 2) { in iwl_pcie_set_interrupt_capa()
1682 trans_pcie->trans->num_rx_queues = num_irqs + 1; in iwl_pcie_set_interrupt_capa()
1683 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | in iwl_pcie_set_interrupt_capa()
1685 } else if (num_irqs == max_irqs - 1) { in iwl_pcie_set_interrupt_capa()
1686 trans_pcie->trans->num_rx_queues = num_irqs; in iwl_pcie_set_interrupt_capa()
1687 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; in iwl_pcie_set_interrupt_capa()
1689 trans_pcie->trans->num_rx_queues = num_irqs - 1; in iwl_pcie_set_interrupt_capa()
1693 "MSI-X enabled with rx queues %d, vec mask 0x%x\n", in iwl_pcie_set_interrupt_capa()
1694 trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask); in iwl_pcie_set_interrupt_capa()
1696 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); in iwl_pcie_set_interrupt_capa()
1698 trans_pcie->alloc_vecs = num_irqs; in iwl_pcie_set_interrupt_capa()
1699 trans_pcie->msix_enabled = true; in iwl_pcie_set_interrupt_capa()
1705 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); in iwl_pcie_set_interrupt_capa()
1720 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; in iwl_pcie_irq_set_affinity()
1721 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; in iwl_pcie_irq_set_affinity()
1726 * (i.e. return will be > i - 1). in iwl_pcie_irq_set_affinity()
1728 cpu = cpumask_next(i - offset, cpu_online_mask); in iwl_pcie_irq_set_affinity()
1729 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); in iwl_pcie_irq_set_affinity()
1730 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, in iwl_pcie_irq_set_affinity()
1731 &trans_pcie->affinity_mask[i]); in iwl_pcie_irq_set_affinity()
1733 IWL_ERR(trans_pcie->trans, in iwl_pcie_irq_set_affinity()
1735 trans_pcie->msix_entries[i].vector); in iwl_pcie_irq_set_affinity()
1744 for (i = 0; i < trans_pcie->alloc_vecs; i++) { in iwl_pcie_init_msix_handler()
1747 const char *qname = queue_name(&pdev->dev, trans_pcie, i); in iwl_pcie_init_msix_handler()
1750 return -ENOMEM; in iwl_pcie_init_msix_handler()
1752 msix_entry = &trans_pcie->msix_entries[i]; in iwl_pcie_init_msix_handler()
1753 ret = devm_request_threaded_irq(&pdev->dev, in iwl_pcie_init_msix_handler()
1754 msix_entry->vector, in iwl_pcie_init_msix_handler()
1756 (i == trans_pcie->def_irq) ? in iwl_pcie_init_msix_handler()
1763 IWL_ERR(trans_pcie->trans, in iwl_pcie_init_msix_handler()
1769 iwl_pcie_irq_set_affinity(trans_pcie->trans); in iwl_pcie_init_msix_handler()
1778 switch (trans->trans_cfg->device_family) { in iwl_trans_pcie_clear_persistence_bit()
1796 return -EPERM; in iwl_trans_pcie_clear_persistence_bit()
1831 lockdep_assert_held(&trans_pcie->mutex); in _iwl_trans_pcie_start_hw()
1847 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && in _iwl_trans_pcie_start_hw()
1848 trans->trans_cfg->integrated) { in _iwl_trans_pcie_start_hw()
1863 trans_pcie->opmode_down = false; in _iwl_trans_pcie_start_hw()
1866 trans_pcie->is_down = false; in _iwl_trans_pcie_start_hw()
1879 mutex_lock(&trans_pcie->mutex); in iwl_trans_pcie_start_hw()
1881 mutex_unlock(&trans_pcie->mutex); in iwl_trans_pcie_start_hw()
1890 mutex_lock(&trans_pcie->mutex); in iwl_trans_pcie_op_mode_leave()
1892 /* disable interrupts - don't enable HW RF kill interrupt */ in iwl_trans_pcie_op_mode_leave()
1901 mutex_unlock(&trans_pcie->mutex); in iwl_trans_pcie_op_mode_leave()
1908 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); in iwl_trans_pcie_write8()
1913 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); in iwl_trans_pcie_write32()
1918 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); in iwl_trans_pcie_read32()
1923 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) in iwl_trans_pcie_prph_msk()
1953 /* free all first - we might be reconfigured for a different size */ in iwl_trans_pcie_configure()
1956 trans->txqs.cmd.q_id = trans_cfg->cmd_queue; in iwl_trans_pcie_configure()
1957 trans->txqs.cmd.fifo = trans_cfg->cmd_fifo; in iwl_trans_pcie_configure()
1958 trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout; in iwl_trans_pcie_configure()
1959 trans->txqs.page_offs = trans_cfg->cb_data_offs; in iwl_trans_pcie_configure()
1960 trans->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); in iwl_trans_pcie_configure()
1961 trans->txqs.queue_alloc_cmd_ver = trans_cfg->queue_alloc_cmd_ver; in iwl_trans_pcie_configure()
1963 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) in iwl_trans_pcie_configure()
1964 trans_pcie->n_no_reclaim_cmds = 0; in iwl_trans_pcie_configure()
1966 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; in iwl_trans_pcie_configure()
1967 if (trans_pcie->n_no_reclaim_cmds) in iwl_trans_pcie_configure()
1968 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, in iwl_trans_pcie_configure()
1969 trans_pcie->n_no_reclaim_cmds * sizeof(u8)); in iwl_trans_pcie_configure()
1971 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; in iwl_trans_pcie_configure()
1972 trans_pcie->rx_page_order = in iwl_trans_pcie_configure()
1973 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); in iwl_trans_pcie_configure()
1974 trans_pcie->rx_buf_bytes = in iwl_trans_pcie_configure()
1975 iwl_trans_get_rb_size(trans_pcie->rx_buf_size); in iwl_trans_pcie_configure()
1976 trans_pcie->supported_dma_mask = DMA_BIT_MASK(12); in iwl_trans_pcie_configure()
1977 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) in iwl_trans_pcie_configure()
1978 trans_pcie->supported_dma_mask = DMA_BIT_MASK(11); in iwl_trans_pcie_configure()
1980 trans->txqs.bc_table_dword = trans_cfg->bc_table_dword; in iwl_trans_pcie_configure()
1981 trans_pcie->scd_set_active = trans_cfg->scd_set_active; in iwl_trans_pcie_configure()
1983 trans->command_groups = trans_cfg->command_groups; in iwl_trans_pcie_configure()
1984 trans->command_groups_size = trans_cfg->command_groups_size; in iwl_trans_pcie_configure()
1986 /* Initialize NAPI here - it should be before registering to mac80211 in iwl_trans_pcie_configure()
1991 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) in iwl_trans_pcie_configure()
1992 init_dummy_netdev(&trans_pcie->napi_dev); in iwl_trans_pcie_configure()
1994 trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake; in iwl_trans_pcie_configure()
2004 if (trans->trans_cfg->gen2) in iwl_trans_pcie_free()
2010 if (trans_pcie->rba.alloc_wq) { in iwl_trans_pcie_free()
2011 destroy_workqueue(trans_pcie->rba.alloc_wq); in iwl_trans_pcie_free()
2012 trans_pcie->rba.alloc_wq = NULL; in iwl_trans_pcie_free()
2015 if (trans_pcie->msix_enabled) { in iwl_trans_pcie_free()
2016 for (i = 0; i < trans_pcie->alloc_vecs; i++) { in iwl_trans_pcie_free()
2018 trans_pcie->msix_entries[i].vector, in iwl_trans_pcie_free()
2022 trans_pcie->msix_enabled = false; in iwl_trans_pcie_free()
2029 if (trans_pcie->pnvm_dram.size) in iwl_trans_pcie_free()
2030 dma_free_coherent(trans->dev, trans_pcie->pnvm_dram.size, in iwl_trans_pcie_free()
2031 trans_pcie->pnvm_dram.block, in iwl_trans_pcie_free()
2032 trans_pcie->pnvm_dram.physical); in iwl_trans_pcie_free()
2034 if (trans_pcie->reduce_power_dram.size) in iwl_trans_pcie_free()
2035 dma_free_coherent(trans->dev, in iwl_trans_pcie_free()
2036 trans_pcie->reduce_power_dram.size, in iwl_trans_pcie_free()
2037 trans_pcie->reduce_power_dram.block, in iwl_trans_pcie_free()
2038 trans_pcie->reduce_power_dram.physical); in iwl_trans_pcie_free()
2040 mutex_destroy(&trans_pcie->mutex); in iwl_trans_pcie_free()
2047 set_bit(STATUS_TPOWER_PMI, &trans->status); in iwl_trans_pcie_set_pmi()
2049 clear_bit(STATUS_TPOWER_PMI, &trans->status); in iwl_trans_pcie_set_pmi()
2061 struct pci_dev *pdev = removal->pdev; in iwl_trans_pcie_removal_wk()
2064 dev_err(&pdev->dev, "Device gone - attempting removal\n"); in iwl_trans_pcie_removal_wk()
2065 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); in iwl_trans_pcie_removal_wk()
2088 spin_lock(&trans_pcie->reg_lock); in __iwl_trans_pcie_grab_nic_access()
2090 if (trans_pcie->cmd_hold_nic_awake) in __iwl_trans_pcie_grab_nic_access()
2093 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { in __iwl_trans_pcie_grab_nic_access()
2101 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) in __iwl_trans_pcie_grab_nic_access()
2109 * host DRAM when sleeping/waking for power-saving. in __iwl_trans_pcie_grab_nic_access()
2121 * 5000 series and later (including 1000 series) have non-volatile SRAM, in __iwl_trans_pcie_grab_nic_access()
2137 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) in __iwl_trans_pcie_grab_nic_access()
2140 IWL_ERR(trans, "Device gone - scheduling removal!\n"); in __iwl_trans_pcie_grab_nic_access()
2150 "Module is being unloaded - abort\n"); in __iwl_trans_pcie_grab_nic_access()
2163 set_bit(STATUS_TRANS_DEAD, &trans->status); in __iwl_trans_pcie_grab_nic_access()
2165 removal->pdev = to_pci_dev(trans->dev); in __iwl_trans_pcie_grab_nic_access()
2166 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); in __iwl_trans_pcie_grab_nic_access()
2167 pci_dev_get(removal->pdev); in __iwl_trans_pcie_grab_nic_access()
2168 schedule_work(&removal->work); in __iwl_trans_pcie_grab_nic_access()
2175 spin_unlock(&trans_pcie->reg_lock); in __iwl_trans_pcie_grab_nic_access()
2181 * Fool sparse by faking we release the lock - sparse will in __iwl_trans_pcie_grab_nic_access()
2184 __release(&trans_pcie->reg_lock); in __iwl_trans_pcie_grab_nic_access()
2206 lockdep_assert_held(&trans_pcie->reg_lock); in iwl_trans_pcie_release_nic_access()
2209 * Fool sparse by faking we acquiring the lock - sparse will in iwl_trans_pcie_release_nic_access()
2212 __acquire(&trans_pcie->reg_lock); in iwl_trans_pcie_release_nic_access()
2214 if (trans_pcie->cmd_hold_nic_awake) in iwl_trans_pcie_release_nic_access()
2216 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in iwl_trans_pcie_release_nic_access()
2229 spin_unlock_bh(&trans_pcie->reg_lock); in iwl_trans_pcie_release_nic_access()
2262 return -EBUSY; in iwl_trans_pcie_read_mem()
2282 ret = -EBUSY; in iwl_trans_pcie_write_mem()
2290 return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev, in iwl_trans_pcie_read_config32()
2298 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { in iwl_trans_pcie_block_txq_ptrs()
2299 struct iwl_txq *txq = trans->txqs.txq[i]; in iwl_trans_pcie_block_txq_ptrs()
2301 if (i == trans->txqs.cmd.q_id) in iwl_trans_pcie_block_txq_ptrs()
2304 spin_lock_bh(&txq->lock); in iwl_trans_pcie_block_txq_ptrs()
2306 if (!block && !(WARN_ON_ONCE(!txq->block))) { in iwl_trans_pcie_block_txq_ptrs()
2307 txq->block--; in iwl_trans_pcie_block_txq_ptrs()
2308 if (!txq->block) { in iwl_trans_pcie_block_txq_ptrs()
2310 txq->write_ptr | (i << 8)); in iwl_trans_pcie_block_txq_ptrs()
2313 txq->block++; in iwl_trans_pcie_block_txq_ptrs()
2316 spin_unlock_bh(&txq->lock); in iwl_trans_pcie_block_txq_ptrs()
2327 if (queue >= trans->num_rx_queues || !trans_pcie->rxq) in iwl_trans_pcie_rxq_dma_data()
2328 return -EINVAL; in iwl_trans_pcie_rxq_dma_data()
2330 data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; in iwl_trans_pcie_rxq_dma_data()
2331 data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; in iwl_trans_pcie_rxq_dma_data()
2332 data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; in iwl_trans_pcie_rxq_dma_data()
2333 data->fr_bd_wid = 0; in iwl_trans_pcie_rxq_dma_data()
2346 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) in iwl_trans_pcie_wait_txq_empty()
2347 return -ENODEV; in iwl_trans_pcie_wait_txq_empty()
2349 if (!test_bit(txq_idx, trans->txqs.queue_used)) in iwl_trans_pcie_wait_txq_empty()
2350 return -EINVAL; in iwl_trans_pcie_wait_txq_empty()
2353 txq = trans->txqs.txq[txq_idx]; in iwl_trans_pcie_wait_txq_empty()
2355 spin_lock_bh(&txq->lock); in iwl_trans_pcie_wait_txq_empty()
2356 overflow_tx = txq->overflow_tx || in iwl_trans_pcie_wait_txq_empty()
2357 !skb_queue_empty(&txq->overflow_q); in iwl_trans_pcie_wait_txq_empty()
2358 spin_unlock_bh(&txq->lock); in iwl_trans_pcie_wait_txq_empty()
2360 wr_ptr = READ_ONCE(txq->write_ptr); in iwl_trans_pcie_wait_txq_empty()
2362 while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || in iwl_trans_pcie_wait_txq_empty()
2366 u8 write_ptr = READ_ONCE(txq->write_ptr); in iwl_trans_pcie_wait_txq_empty()
2374 "WR pointer moved while flushing %d -> %d\n", in iwl_trans_pcie_wait_txq_empty()
2376 return -ETIMEDOUT; in iwl_trans_pcie_wait_txq_empty()
2381 spin_lock_bh(&txq->lock); in iwl_trans_pcie_wait_txq_empty()
2382 overflow_tx = txq->overflow_tx || in iwl_trans_pcie_wait_txq_empty()
2383 !skb_queue_empty(&txq->overflow_q); in iwl_trans_pcie_wait_txq_empty()
2384 spin_unlock_bh(&txq->lock); in iwl_trans_pcie_wait_txq_empty()
2387 if (txq->read_ptr != txq->write_ptr) { in iwl_trans_pcie_wait_txq_empty()
2391 return -ETIMEDOUT; in iwl_trans_pcie_wait_txq_empty()
2406 cnt < trans->trans_cfg->base_params->num_of_queues; in iwl_trans_pcie_wait_txqs_empty()
2409 if (cnt == trans->txqs.cmd.q_id) in iwl_trans_pcie_wait_txqs_empty()
2411 if (!test_bit(cnt, trans->txqs.queue_used)) in iwl_trans_pcie_wait_txqs_empty()
2429 spin_lock_bh(&trans_pcie->reg_lock); in iwl_trans_pcie_set_bits_mask()
2431 spin_unlock_bh(&trans_pcie->reg_lock); in iwl_trans_pcie_set_bits_mask()
2547 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; in iwl_dbgfs_tx_queue_seq_start()
2550 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) in iwl_dbgfs_tx_queue_seq_start()
2556 state->pos = *pos; in iwl_dbgfs_tx_queue_seq_start()
2563 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; in iwl_dbgfs_tx_queue_seq_next()
2566 *pos = ++state->pos; in iwl_dbgfs_tx_queue_seq_next()
2568 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) in iwl_dbgfs_tx_queue_seq_next()
2581 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; in iwl_dbgfs_tx_queue_seq_show()
2583 struct iwl_trans *trans = priv->trans; in iwl_dbgfs_tx_queue_seq_show()
2584 struct iwl_txq *txq = trans->txqs.txq[state->pos]; in iwl_dbgfs_tx_queue_seq_show()
2587 (unsigned int)state->pos, in iwl_dbgfs_tx_queue_seq_show()
2588 !!test_bit(state->pos, trans->txqs.queue_used), in iwl_dbgfs_tx_queue_seq_show()
2589 !!test_bit(state->pos, trans->txqs.queue_stopped)); in iwl_dbgfs_tx_queue_seq_show()
2593 txq->read_ptr, txq->write_ptr, in iwl_dbgfs_tx_queue_seq_show()
2594 txq->need_update, txq->frozen, in iwl_dbgfs_tx_queue_seq_show()
2595 txq->n_window, txq->ampdu); in iwl_dbgfs_tx_queue_seq_show()
2599 if (state->pos == trans->txqs.cmd.q_id) in iwl_dbgfs_tx_queue_seq_show()
2621 return -ENOMEM; in iwl_dbgfs_tx_queue_open()
2623 priv->trans = inode->i_private; in iwl_dbgfs_tx_queue_open()
2631 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rx_queue_read()
2637 bufsz = sizeof(char) * 121 * trans->num_rx_queues; in iwl_dbgfs_rx_queue_read()
2639 if (!trans_pcie->rxq) in iwl_dbgfs_rx_queue_read()
2640 return -EAGAIN; in iwl_dbgfs_rx_queue_read()
2644 return -ENOMEM; in iwl_dbgfs_rx_queue_read()
2646 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { in iwl_dbgfs_rx_queue_read()
2647 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; in iwl_dbgfs_rx_queue_read()
2649 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", in iwl_dbgfs_rx_queue_read()
2651 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", in iwl_dbgfs_rx_queue_read()
2652 rxq->read); in iwl_dbgfs_rx_queue_read()
2653 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", in iwl_dbgfs_rx_queue_read()
2654 rxq->write); in iwl_dbgfs_rx_queue_read()
2655 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", in iwl_dbgfs_rx_queue_read()
2656 rxq->write_actual); in iwl_dbgfs_rx_queue_read()
2657 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", in iwl_dbgfs_rx_queue_read()
2658 rxq->need_update); in iwl_dbgfs_rx_queue_read()
2659 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", in iwl_dbgfs_rx_queue_read()
2660 rxq->free_count); in iwl_dbgfs_rx_queue_read()
2661 if (rxq->rb_stts) { in iwl_dbgfs_rx_queue_read()
2664 pos += scnprintf(buf + pos, bufsz - pos, in iwl_dbgfs_rx_queue_read()
2668 pos += scnprintf(buf + pos, bufsz - pos, in iwl_dbgfs_rx_queue_read()
2682 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_interrupt_read()
2684 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; in iwl_dbgfs_interrupt_read()
2693 return -ENOMEM; in iwl_dbgfs_interrupt_read()
2695 pos += scnprintf(buf + pos, bufsz - pos, in iwl_dbgfs_interrupt_read()
2698 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", in iwl_dbgfs_interrupt_read()
2699 isr_stats->hw); in iwl_dbgfs_interrupt_read()
2700 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", in iwl_dbgfs_interrupt_read()
2701 isr_stats->sw); in iwl_dbgfs_interrupt_read()
2702 if (isr_stats->sw || isr_stats->hw) { in iwl_dbgfs_interrupt_read()
2703 pos += scnprintf(buf + pos, bufsz - pos, in iwl_dbgfs_interrupt_read()
2705 isr_stats->err_code); in iwl_dbgfs_interrupt_read()
2708 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", in iwl_dbgfs_interrupt_read()
2709 isr_stats->sch); in iwl_dbgfs_interrupt_read()
2710 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", in iwl_dbgfs_interrupt_read()
2711 isr_stats->alive); in iwl_dbgfs_interrupt_read()
2713 pos += scnprintf(buf + pos, bufsz - pos, in iwl_dbgfs_interrupt_read()
2714 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); in iwl_dbgfs_interrupt_read()
2716 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", in iwl_dbgfs_interrupt_read()
2717 isr_stats->ctkill); in iwl_dbgfs_interrupt_read()
2719 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", in iwl_dbgfs_interrupt_read()
2720 isr_stats->wakeup); in iwl_dbgfs_interrupt_read()
2722 pos += scnprintf(buf + pos, bufsz - pos, in iwl_dbgfs_interrupt_read()
2723 "Rx command responses:\t\t %u\n", isr_stats->rx); in iwl_dbgfs_interrupt_read()
2725 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", in iwl_dbgfs_interrupt_read()
2726 isr_stats->tx); in iwl_dbgfs_interrupt_read()
2728 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", in iwl_dbgfs_interrupt_read()
2729 isr_stats->unhandled); in iwl_dbgfs_interrupt_read()
2740 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_interrupt_write()
2742 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; in iwl_dbgfs_interrupt_write()
2759 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_csr_write()
2770 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_fh_reg_read()
2778 return -EINVAL; in iwl_dbgfs_fh_reg_read()
2788 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rfkill_read()
2794 trans_pcie->debug_rfkill, in iwl_dbgfs_rfkill_read()
2805 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rfkill_write()
2813 if (new_value == trans_pcie->debug_rfkill) in iwl_dbgfs_rfkill_write()
2815 IWL_WARN(trans, "changing debug rfkill %d->%d\n", in iwl_dbgfs_rfkill_write()
2816 trans_pcie->debug_rfkill, new_value); in iwl_dbgfs_rfkill_write()
2817 trans_pcie->debug_rfkill = new_value; in iwl_dbgfs_rfkill_write()
2826 struct iwl_trans *trans = inode->i_private; in iwl_dbgfs_monitor_data_open()
2829 if (!trans->dbg.dest_tlv || in iwl_dbgfs_monitor_data_open()
2830 trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { in iwl_dbgfs_monitor_data_open()
2832 return -ENOENT; in iwl_dbgfs_monitor_data_open()
2835 if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) in iwl_dbgfs_monitor_data_open()
2836 return -EBUSY; in iwl_dbgfs_monitor_data_open()
2838 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; in iwl_dbgfs_monitor_data_open()
2846 IWL_TRANS_GET_PCIE_TRANS(inode->i_private); in iwl_dbgfs_monitor_data_release()
2848 if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) in iwl_dbgfs_monitor_data_release()
2849 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; in iwl_dbgfs_monitor_data_release()
2857 int buf_size_left = count - *bytes_copied; in iwl_write_to_user_buf()
2859 buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); in iwl_write_to_user_buf()
2863 *size -= copy_to_user(user_buf, buf, *size); in iwl_write_to_user_buf()
2875 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_monitor_data_read()
2877 u8 *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; in iwl_dbgfs_monitor_data_read()
2878 struct cont_rec *data = &trans_pcie->fw_mon_data; in iwl_dbgfs_monitor_data_read()
2883 if (trans->dbg.dest_tlv) { in iwl_dbgfs_monitor_data_read()
2885 le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); in iwl_dbgfs_monitor_data_read()
2886 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); in iwl_dbgfs_monitor_data_read()
2892 if (unlikely(!trans->dbg.rec_on)) in iwl_dbgfs_monitor_data_read()
2895 mutex_lock(&data->mutex); in iwl_dbgfs_monitor_data_read()
2896 if (data->state == in iwl_dbgfs_monitor_data_read()
2898 mutex_unlock(&data->mutex); in iwl_dbgfs_monitor_data_read()
2906 if (data->prev_wrap_cnt == wrap_cnt) { in iwl_dbgfs_monitor_data_read()
2907 size = write_ptr - data->prev_wr_ptr; in iwl_dbgfs_monitor_data_read()
2908 curr_buf = cpu_addr + data->prev_wr_ptr; in iwl_dbgfs_monitor_data_read()
2912 data->prev_wr_ptr += size; in iwl_dbgfs_monitor_data_read()
2914 } else if (data->prev_wrap_cnt == wrap_cnt - 1 && in iwl_dbgfs_monitor_data_read()
2915 write_ptr < data->prev_wr_ptr) { in iwl_dbgfs_monitor_data_read()
2916 size = trans->dbg.fw_mon.size - data->prev_wr_ptr; in iwl_dbgfs_monitor_data_read()
2917 curr_buf = cpu_addr + data->prev_wr_ptr; in iwl_dbgfs_monitor_data_read()
2921 data->prev_wr_ptr += size; in iwl_dbgfs_monitor_data_read()
2928 data->prev_wr_ptr = size; in iwl_dbgfs_monitor_data_read()
2929 data->prev_wrap_cnt++; in iwl_dbgfs_monitor_data_read()
2932 if (data->prev_wrap_cnt == wrap_cnt - 1 && in iwl_dbgfs_monitor_data_read()
2933 write_ptr > data->prev_wr_ptr) in iwl_dbgfs_monitor_data_read()
2936 else if (!unlikely(data->prev_wrap_cnt == 0 && in iwl_dbgfs_monitor_data_read()
2937 data->prev_wr_ptr == 0)) in iwl_dbgfs_monitor_data_read()
2939 "monitor data is out of sync, start copying from the beginning\n"); in iwl_dbgfs_monitor_data_read()
2945 data->prev_wr_ptr = size; in iwl_dbgfs_monitor_data_read()
2946 data->prev_wrap_cnt = wrap_cnt; in iwl_dbgfs_monitor_data_read()
2949 mutex_unlock(&data->mutex); in iwl_dbgfs_monitor_data_read()
2958 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rf_read()
2961 if (!trans_pcie->rf_name[0]) in iwl_dbgfs_rf_read()
2962 return -ENODEV; in iwl_dbgfs_rf_read()
2965 trans_pcie->rf_name, in iwl_dbgfs_rf_read()
2966 strlen(trans_pcie->rf_name)); in iwl_dbgfs_rf_read()
2993 struct dentry *dir = trans->dbgfs_dir; in iwl_trans_pcie_dbgfs_register()
3008 struct cont_rec *data = &trans_pcie->fw_mon_data; in iwl_trans_pcie_debugfs_cleanup()
3010 mutex_lock(&data->mutex); in iwl_trans_pcie_debugfs_cleanup()
3011 data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; in iwl_trans_pcie_debugfs_cleanup()
3012 mutex_unlock(&data->mutex); in iwl_trans_pcie_debugfs_cleanup()
3021 for (i = 0; i < trans->txqs.tfd.max_tbs; i++) in iwl_trans_pcie_get_cmdlen()
3032 int max_len = trans_pcie->rx_buf_bytes; in iwl_trans_pcie_dump_rbs()
3033 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ in iwl_trans_pcie_dump_rbs()
3034 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; in iwl_trans_pcie_dump_rbs()
3037 spin_lock(&rxq->lock); in iwl_trans_pcie_dump_rbs()
3041 for (i = rxq->read, j = 0; in iwl_trans_pcie_dump_rbs()
3044 struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; in iwl_trans_pcie_dump_rbs()
3047 dma_sync_single_for_cpu(trans->dev, rxb->page_dma, in iwl_trans_pcie_dump_rbs()
3052 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); in iwl_trans_pcie_dump_rbs()
3053 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); in iwl_trans_pcie_dump_rbs()
3054 rb = (void *)(*data)->data; in iwl_trans_pcie_dump_rbs()
3055 rb->index = cpu_to_le32(i); in iwl_trans_pcie_dump_rbs()
3056 memcpy(rb->data, page_address(rxb->page), max_len); in iwl_trans_pcie_dump_rbs()
3061 spin_unlock(&rxq->lock); in iwl_trans_pcie_dump_rbs()
3074 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); in iwl_trans_pcie_dump_csr()
3075 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); in iwl_trans_pcie_dump_csr()
3076 val = (void *)(*data)->data; in iwl_trans_pcie_dump_csr()
3089 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; in iwl_trans_pcie_fh_regs_dump()
3096 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); in iwl_trans_pcie_fh_regs_dump()
3097 (*data)->len = cpu_to_le32(fh_regs_len); in iwl_trans_pcie_fh_regs_dump()
3098 val = (void *)(*data)->data; in iwl_trans_pcie_fh_regs_dump()
3100 if (!trans->trans_cfg->gen2) in iwl_trans_pcie_fh_regs_dump()
3124 u32 *buffer = (u32 *)fw_mon_data->data; in iwl_trans_pci_dump_marbh_monitor()
3147 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { in iwl_trans_pcie_dump_pointers()
3152 } else if (trans->dbg.dest_tlv) { in iwl_trans_pcie_dump_pointers()
3153 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); in iwl_trans_pcie_dump_pointers()
3154 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); in iwl_trans_pcie_dump_pointers()
3155 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); in iwl_trans_pcie_dump_pointers()
3163 fw_mon_data->fw_mon_cycle_cnt = in iwl_trans_pcie_dump_pointers()
3165 fw_mon_data->fw_mon_base_ptr = in iwl_trans_pcie_dump_pointers()
3167 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { in iwl_trans_pcie_dump_pointers()
3168 fw_mon_data->fw_mon_base_high_ptr = in iwl_trans_pcie_dump_pointers()
3174 fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); in iwl_trans_pcie_dump_pointers()
3182 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_trans_pcie_dump_monitor()
3185 if (trans->dbg.dest_tlv || in iwl_trans_pcie_dump_monitor()
3186 (fw_mon->size && in iwl_trans_pcie_dump_monitor()
3187 (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 || in iwl_trans_pcie_dump_monitor()
3188 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { in iwl_trans_pcie_dump_monitor()
3191 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); in iwl_trans_pcie_dump_monitor()
3192 fw_mon_data = (void *)(*data)->data; in iwl_trans_pcie_dump_monitor()
3197 if (fw_mon->size) { in iwl_trans_pcie_dump_monitor()
3198 memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size); in iwl_trans_pcie_dump_monitor()
3199 monitor_len = fw_mon->size; in iwl_trans_pcie_dump_monitor()
3200 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { in iwl_trans_pcie_dump_monitor()
3201 u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); in iwl_trans_pcie_dump_monitor()
3206 if (trans->dbg.dest_tlv->version) { in iwl_trans_pcie_dump_monitor()
3209 trans->dbg.dest_tlv->base_shift; in iwl_trans_pcie_dump_monitor()
3211 base += trans->cfg->smem_offset; in iwl_trans_pcie_dump_monitor()
3214 trans->dbg.dest_tlv->base_shift; in iwl_trans_pcie_dump_monitor()
3217 iwl_trans_read_mem(trans, base, fw_mon_data->data, in iwl_trans_pcie_dump_monitor()
3219 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { in iwl_trans_pcie_dump_monitor()
3225 /* Didn't match anything - output no monitor data */ in iwl_trans_pcie_dump_monitor()
3230 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); in iwl_trans_pcie_dump_monitor()
3238 if (trans->dbg.fw_mon.size) { in iwl_trans_get_fw_monitor_len()
3241 trans->dbg.fw_mon.size; in iwl_trans_get_fw_monitor_len()
3242 return trans->dbg.fw_mon.size; in iwl_trans_get_fw_monitor_len()
3243 } else if (trans->dbg.dest_tlv) { in iwl_trans_get_fw_monitor_len()
3246 if (trans->dbg.dest_tlv->version == 1) { in iwl_trans_get_fw_monitor_len()
3247 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); in iwl_trans_get_fw_monitor_len()
3250 trans->dbg.dest_tlv->base_shift; in iwl_trans_get_fw_monitor_len()
3252 base += trans->cfg->smem_offset; in iwl_trans_get_fw_monitor_len()
3256 trans->dbg.dest_tlv->end_shift; in iwl_trans_get_fw_monitor_len()
3259 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); in iwl_trans_get_fw_monitor_len()
3260 end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); in iwl_trans_get_fw_monitor_len()
3263 trans->dbg.dest_tlv->base_shift; in iwl_trans_get_fw_monitor_len()
3265 trans->dbg.dest_tlv->end_shift; in iwl_trans_get_fw_monitor_len()
3268 if (trans->trans_cfg->device_family >= in iwl_trans_get_fw_monitor_len()
3270 trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) in iwl_trans_get_fw_monitor_len()
3271 end += (1 << trans->dbg.dest_tlv->end_shift); in iwl_trans_get_fw_monitor_len()
3272 monitor_len = end - base; in iwl_trans_get_fw_monitor_len()
3290 struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id]; in iwl_trans_pcie_dump_data() local
3295 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && in iwl_trans_pcie_dump_data()
3296 !trans->trans_cfg->mq_rx_supported && in iwl_trans_pcie_dump_data()
3306 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) in iwl_trans_pcie_dump_data()
3308 cmdq->n_window * (sizeof(*txcmd) + in iwl_trans_pcie_dump_data()
3321 if (trans->trans_cfg->gen2) in iwl_trans_pcie_dump_data()
3323 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - in iwl_trans_pcie_dump_data()
3327 (FH_MEM_UPPER_BOUND - in iwl_trans_pcie_dump_data()
3332 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ in iwl_trans_pcie_dump_data()
3333 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; in iwl_trans_pcie_dump_data()
3338 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; in iwl_trans_pcie_dump_data()
3341 (PAGE_SIZE << trans_pcie->rx_page_order)); in iwl_trans_pcie_dump_data()
3345 if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) in iwl_trans_pcie_dump_data()
3346 for (i = 0; i < trans->init_dram.paging_cnt; i++) in iwl_trans_pcie_dump_data()
3349 trans->init_dram.paging[i].size; in iwl_trans_pcie_dump_data()
3356 data = (void *)dump_data->data; in iwl_trans_pcie_dump_data()
3358 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { in iwl_trans_pcie_dump_data()
3359 u16 tfd_size = trans->txqs.tfd.size; in iwl_trans_pcie_dump_data()
3361 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); in iwl_trans_pcie_dump_data()
3362 txcmd = (void *)data->data; in iwl_trans_pcie_dump_data()
3363 spin_lock_bh(&cmdq->lock); in iwl_trans_pcie_dump_data()
3364 ptr = cmdq->write_ptr; in iwl_trans_pcie_dump_data()
3365 for (i = 0; i < cmdq->n_window; i++) { in iwl_trans_pcie_dump_data()
3366 u8 idx = iwl_txq_get_cmd_index(cmdq, ptr); in iwl_trans_pcie_dump_data()
3370 if (trans->trans_cfg->use_tfh) in iwl_trans_pcie_dump_data()
3376 (u8 *)cmdq->tfds + in iwl_trans_pcie_dump_data()
3382 txcmd->cmdlen = cpu_to_le32(cmdlen); in iwl_trans_pcie_dump_data()
3383 txcmd->caplen = cpu_to_le32(caplen); in iwl_trans_pcie_dump_data()
3384 memcpy(txcmd->data, cmdq->entries[idx].cmd, in iwl_trans_pcie_dump_data()
3386 if (sanitize_ops && sanitize_ops->frob_hcmd) in iwl_trans_pcie_dump_data()
3387 sanitize_ops->frob_hcmd(sanitize_ctx, in iwl_trans_pcie_dump_data()
3388 txcmd->data, in iwl_trans_pcie_dump_data()
3390 txcmd = (void *)((u8 *)txcmd->data + caplen); in iwl_trans_pcie_dump_data()
3395 spin_unlock_bh(&cmdq->lock); in iwl_trans_pcie_dump_data()
3397 data->len = cpu_to_le32(len); in iwl_trans_pcie_dump_data()
3410 if (trans->trans_cfg->gen2 && in iwl_trans_pcie_dump_data()
3412 for (i = 0; i < trans->init_dram.paging_cnt; i++) { in iwl_trans_pcie_dump_data()
3414 u32 page_len = trans->init_dram.paging[i].size; in iwl_trans_pcie_dump_data()
3416 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); in iwl_trans_pcie_dump_data()
3417 data->len = cpu_to_le32(sizeof(*paging) + page_len); in iwl_trans_pcie_dump_data()
3418 paging = (void *)data->data; in iwl_trans_pcie_dump_data()
3419 paging->index = cpu_to_le32(i); in iwl_trans_pcie_dump_data()
3420 memcpy(paging->data, in iwl_trans_pcie_dump_data()
3421 trans->init_dram.paging[i].block, page_len); in iwl_trans_pcie_dump_data()
3430 dump_data->len = len; in iwl_trans_pcie_dump_data()
3448 if (trans_pcie->msix_enabled) { in iwl_trans_pcie_sync_nmi()
3450 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in iwl_trans_pcie_sync_nmi()
3546 if (!cfg_trans->gen2) in iwl_trans_pcie_alloc()
3553 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops, in iwl_trans_pcie_alloc()
3556 return ERR_PTR(-ENOMEM); in iwl_trans_pcie_alloc()
3560 trans_pcie->trans = trans; in iwl_trans_pcie_alloc()
3561 trans_pcie->opmode_down = true; in iwl_trans_pcie_alloc()
3562 spin_lock_init(&trans_pcie->irq_lock); in iwl_trans_pcie_alloc()
3563 spin_lock_init(&trans_pcie->reg_lock); in iwl_trans_pcie_alloc()
3564 spin_lock_init(&trans_pcie->alloc_page_lock); in iwl_trans_pcie_alloc()
3565 mutex_init(&trans_pcie->mutex); in iwl_trans_pcie_alloc()
3566 init_waitqueue_head(&trans_pcie->ucode_write_waitq); in iwl_trans_pcie_alloc()
3567 init_waitqueue_head(&trans_pcie->fw_reset_waitq); in iwl_trans_pcie_alloc()
3568 init_waitqueue_head(&trans_pcie->imr_waitq); in iwl_trans_pcie_alloc()
3570 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", in iwl_trans_pcie_alloc()
3572 if (!trans_pcie->rba.alloc_wq) { in iwl_trans_pcie_alloc()
3573 ret = -ENOMEM; in iwl_trans_pcie_alloc()
3576 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); in iwl_trans_pcie_alloc()
3578 trans_pcie->debug_rfkill = -1; in iwl_trans_pcie_alloc()
3580 if (!cfg_trans->base_params->pcie_l1_allowed) { in iwl_trans_pcie_alloc()
3582 * W/A - seems to solve weird behavior. We need to remove this in iwl_trans_pcie_alloc()
3591 trans_pcie->def_rx_queue = 0; in iwl_trans_pcie_alloc()
3595 addr_size = trans->txqs.tfd.addr_size; in iwl_trans_pcie_alloc()
3596 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_size)); in iwl_trans_pcie_alloc()
3598 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in iwl_trans_pcie_alloc()
3601 dev_err(&pdev->dev, "No suitable DMA available\n"); in iwl_trans_pcie_alloc()
3608 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); in iwl_trans_pcie_alloc()
3614 dev_err(&pdev->dev, "pcim_iomap_table failed\n"); in iwl_trans_pcie_alloc()
3615 ret = -ENOMEM; in iwl_trans_pcie_alloc()
3619 trans_pcie->hw_base = table[0]; in iwl_trans_pcie_alloc()
3620 if (!trans_pcie->hw_base) { in iwl_trans_pcie_alloc()
3621 dev_err(&pdev->dev, "couldn't find IO mem in first BAR\n"); in iwl_trans_pcie_alloc()
3622 ret = -ENODEV; in iwl_trans_pcie_alloc()
3630 trans_pcie->pci_dev = pdev; in iwl_trans_pcie_alloc()
3633 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); in iwl_trans_pcie_alloc()
3634 if (trans->hw_rev == 0xffffffff) { in iwl_trans_pcie_alloc()
3635 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); in iwl_trans_pcie_alloc()
3636 ret = -EIO; in iwl_trans_pcie_alloc()
3642 * changed, and now the revision step also includes bit 0-1 (no more in iwl_trans_pcie_alloc()
3643 * "dash" value). To keep hw_rev backwards compatible - we'll store it in iwl_trans_pcie_alloc()
3646 if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) in iwl_trans_pcie_alloc()
3647 trans->hw_rev_step = trans->hw_rev & 0xF; in iwl_trans_pcie_alloc()
3649 trans->hw_rev_step = (trans->hw_rev & 0xC) >> 2; in iwl_trans_pcie_alloc()
3651 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); in iwl_trans_pcie_alloc()
3654 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; in iwl_trans_pcie_alloc()
3655 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), in iwl_trans_pcie_alloc()
3656 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); in iwl_trans_pcie_alloc()
3658 init_waitqueue_head(&trans_pcie->sx_waitq); in iwl_trans_pcie_alloc()
3661 if (trans_pcie->msix_enabled) { in iwl_trans_pcie_alloc()
3670 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, in iwl_trans_pcie_alloc()
3675 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); in iwl_trans_pcie_alloc()
3681 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; in iwl_trans_pcie_alloc()
3682 mutex_init(&trans_pcie->fw_mon_data.mutex); in iwl_trans_pcie_alloc()
3692 destroy_workqueue(trans_pcie->rba.alloc_wq); in iwl_trans_pcie_alloc()
3720 int ret = -1; in iwl_trans_pcie_copy_imr()
3722 trans_pcie->imr_status = IMR_D2S_REQUESTED; in iwl_trans_pcie_copy_imr()
3724 ret = wait_event_timeout(trans_pcie->imr_waitq, in iwl_trans_pcie_copy_imr()
3725 trans_pcie->imr_status != in iwl_trans_pcie_copy_imr()
3727 if (!ret || trans_pcie->imr_status == IMR_D2S_ERROR) { in iwl_trans_pcie_copy_imr()
3730 return -ETIMEDOUT; in iwl_trans_pcie_copy_imr()
3732 trans_pcie->imr_status = IMR_D2S_IDLE; in iwl_trans_pcie_copy_imr()