31 #define RADIO_REG_MAX_READ 0x2ad
46 	for (i = 0; i < RADIO_REG_MAX_READ; i++) {  in iwl_read_radio_regs()
74 	/* No need to try to read the data if the length is 0 */  in iwl_fwrt_dump_rxf()
75 	if (fifo_len == 0)  in iwl_fwrt_dump_rxf()
100 	iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1);  in iwl_fwrt_dump_rxf()
102 	iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1);  in iwl_fwrt_dump_rxf()
105 			     RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0);  in iwl_fwrt_dump_rxf()
109 	for (i = 0; i < fifo_len; i++)  in iwl_fwrt_dump_rxf()
129 	/* No need to try to read the data if the length is 0 */  in iwl_fwrt_dump_txf()
130 	if (fifo_len == 0)  in iwl_fwrt_dump_txf()
162 	for (i = 0; i < fifo_len / sizeof(u32); i++)  in iwl_fwrt_dump_txf()
187 				  cfg->lmac[0].rxfifo1_size, 0, 0);  in iwl_fw_dump_rxf()
218 		for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) {  in iwl_fw_dump_txf()
222 					  cfg->lmac[0].txfifo_size[i], 0, i);  in iwl_fw_dump_txf()
227 			for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries;  in iwl_fw_dump_txf()
245 		for (i = 0;  in iwl_fw_dump_txf()
252 			/* No need to try to read the data if the length is 0 */  in iwl_fw_dump_txf()
253 			if (fifo_len == 0)  in iwl_fw_dump_txf()
295 			for (j = 0; j < fifo_len; j++)  in iwl_fw_dump_txf()
311 	{ .start = 0x00a00000, .end = 0x00a00000 },
312 	{ .start = 0x00a0000c, .end = 0x00a00024 },
313 	{ .start = 0x00a0002c, .end = 0x00a0003c },
314 	{ .start = 0x00a00410, .end = 0x00a00418 },
315 	{ .start = 0x00a00420, .end = 0x00a00420 },
316 	{ .start = 0x00a00428, .end = 0x00a00428 },
317 	{ .start = 0x00a00430, .end = 0x00a0043c },
318 	{ .start = 0x00a00444, .end = 0x00a00444 },
319 	{ .start = 0x00a004c0, .end = 0x00a004cc },
320 	{ .start = 0x00a004d8, .end = 0x00a004d8 },
321 	{ .start = 0x00a004e0, .end = 0x00a004f0 },
322 	{ .start = 0x00a00840, .end = 0x00a00840 },
323 	{ .start = 0x00a00850, .end = 0x00a00858 },
324 	{ .start = 0x00a01004, .end = 0x00a01008 },
325 	{ .start = 0x00a01010, .end = 0x00a01010 },
326 	{ .start = 0x00a01018, .end = 0x00a01018 },
327 	{ .start = 0x00a01024, .end = 0x00a01024 },
328 	{ .start = 0x00a0102c, .end = 0x00a01034 },
329 	{ .start = 0x00a0103c, .end = 0x00a01040 },
330 	{ .start = 0x00a01048, .end = 0x00a01094 },
331 	{ .start = 0x00a01c00, .end = 0x00a01c20 },
332 	{ .start = 0x00a01c58, .end = 0x00a01c58 },
333 	{ .start = 0x00a01c7c, .end = 0x00a01c7c },
334 	{ .start = 0x00a01c28, .end = 0x00a01c54 },
335 	{ .start = 0x00a01c5c, .end = 0x00a01c5c },
336 	{ .start = 0x00a01c60, .end = 0x00a01cdc },
337 	{ .start = 0x00a01ce0, .end = 0x00a01d0c },
338 	{ .start = 0x00a01d18, .end = 0x00a01d20 },
339 	{ .start = 0x00a01d2c, .end = 0x00a01d30 },
340 	{ .start = 0x00a01d40, .end = 0x00a01d5c },
341 	{ .start = 0x00a01d80, .end = 0x00a01d80 },
342 	{ .start = 0x00a01d98, .end = 0x00a01d9c },
343 	{ .start = 0x00a01da8, .end = 0x00a01da8 },
344 	{ .start = 0x00a01db8, .end = 0x00a01df4 },
345 	{ .start = 0x00a01dc0, .end = 0x00a01dfc },
346 	{ .start = 0x00a01e00, .end = 0x00a01e2c },
347 	{ .start = 0x00a01e40, .end = 0x00a01e60 },
348 	{ .start = 0x00a01e68, .end = 0x00a01e6c },
349 	{ .start = 0x00a01e74, .end = 0x00a01e74 },
350 	{ .start = 0x00a01e84, .end = 0x00a01e90 },
351 	{ .start = 0x00a01e9c, .end = 0x00a01ec4 },
352 	{ .start = 0x00a01ed0, .end = 0x00a01ee0 },
353 	{ .start = 0x00a01f00, .end = 0x00a01f1c },
354 	{ .start = 0x00a01f44, .end = 0x00a01ffc },
355 	{ .start = 0x00a02000, .end = 0x00a02048 },
356 	{ .start = 0x00a02068, .end = 0x00a020f0 },
357 	{ .start = 0x00a02100, .end = 0x00a02118 },
358 	{ .start = 0x00a02140, .end = 0x00a0214c },
359 	{ .start = 0x00a02168, .end = 0x00a0218c },
360 	{ .start = 0x00a021c0, .end = 0x00a021c0 },
361 	{ .start = 0x00a02400, .end = 0x00a02410 },
362 	{ .start = 0x00a02418, .end = 0x00a02420 },
363 	{ .start = 0x00a02428, .end = 0x00a0242c },
364 	{ .start = 0x00a02434, .end = 0x00a02434 },
365 	{ .start = 0x00a02440, .end = 0x00a02460 },
366 	{ .start = 0x00a02468, .end = 0x00a024b0 },
367 	{ .start = 0x00a024c8, .end = 0x00a024cc },
368 	{ .start = 0x00a02500, .end = 0x00a02504 },
369 	{ .start = 0x00a0250c, .end = 0x00a02510 },
370 	{ .start = 0x00a02540, .end = 0x00a02554 },
371 	{ .start = 0x00a02580, .end = 0x00a025f4 },
372 	{ .start = 0x00a02600, .end = 0x00a0260c },
373 	{ .start = 0x00a02648, .end = 0x00a02650 },
374 	{ .start = 0x00a02680, .end = 0x00a02680 },
375 	{ .start = 0x00a026c0, .end = 0x00a026d0 },
376 	{ .start = 0x00a02700, .end = 0x00a0270c },
377 	{ .start = 0x00a02804, .end = 0x00a02804 },
378 	{ .start = 0x00a02818, .end = 0x00a0281c },
379 	{ .start = 0x00a02c00, .end = 0x00a02db4 },
380 	{ .start = 0x00a02df4, .end = 0x00a02fb0 },
381 	{ .start = 0x00a03000, .end = 0x00a03014 },
382 	{ .start = 0x00a0301c, .end = 0x00a0302c },
383 	{ .start = 0x00a03034, .end = 0x00a03038 },
384 	{ .start = 0x00a03040, .end = 0x00a03048 },
385 	{ .start = 0x00a03060, .end = 0x00a03068 },
386 	{ .start = 0x00a03070, .end = 0x00a03074 },
387 	{ .start = 0x00a0307c, .end = 0x00a0307c },
388 	{ .start = 0x00a03080, .end = 0x00a03084 },
389 	{ .start = 0x00a0308c, .end = 0x00a03090 },
390 	{ .start = 0x00a03098, .end = 0x00a03098 },
391 	{ .start = 0x00a030a0, .end = 0x00a030a0 },
392 	{ .start = 0x00a030a8, .end = 0x00a030b4 },
393 	{ .start = 0x00a030bc, .end = 0x00a030bc },
394 	{ .start = 0x00a030c0, .end = 0x00a0312c },
395 	{ .start = 0x00a03c00, .end = 0x00a03c5c },
396 	{ .start = 0x00a04400, .end = 0x00a04454 },
397 	{ .start = 0x00a04460, .end = 0x00a04474 },
398 	{ .start = 0x00a044c0, .end = 0x00a044ec },
399 	{ .start = 0x00a04500, .end = 0x00a04504 },
400 	{ .start = 0x00a04510, .end = 0x00a04538 },
401 	{ .start = 0x00a04540, .end = 0x00a04548 },
402 	{ .start = 0x00a04560, .end = 0x00a0457c },
403 	{ .start = 0x00a04590, .end = 0x00a04598 },
404 	{ .start = 0x00a045c0, .end = 0x00a045f4 },
408 	{ .start = 0x00a05c00, .end = 0x00a05c18 },
409 	{ .start = 0x00a05400, .end = 0x00a056e8 },
410 	{ .start = 0x00a08000, .end = 0x00a098bc },
411 	{ .start = 0x00a02400, .end = 0x00a02758 },
412 	{ .start = 0x00a04764, .end = 0x00a0476c },
413 	{ .start = 0x00a04770, .end = 0x00a04774 },
414 	{ .start = 0x00a04620, .end = 0x00a04624 },
418 	{ .start = 0x00a00000, .end = 0x00a00000 },
419 	{ .start = 0x00a0000c, .end = 0x00a00024 },
420 	{ .start = 0x00a0002c, .end = 0x00a00034 },
421 	{ .start = 0x00a0003c, .end = 0x00a0003c },
422 	{ .start = 0x00a00410, .end = 0x00a00418 },
423 	{ .start = 0x00a00420, .end = 0x00a00420 },
424 	{ .start = 0x00a00428, .end = 0x00a00428 },
425 	{ .start = 0x00a00430, .end = 0x00a0043c },
426 	{ .start = 0x00a00444, .end = 0x00a00444 },
427 	{ .start = 0x00a00840, .end = 0x00a00840 },
428 	{ .start = 0x00a00850, .end = 0x00a00858 },
429 	{ .start = 0x00a01004, .end = 0x00a01008 },
430 	{ .start = 0x00a01010, .end = 0x00a01010 },
431 	{ .start = 0x00a01018, .end = 0x00a01018 },
432 	{ .start = 0x00a01024, .end = 0x00a01024 },
433 	{ .start = 0x00a0102c, .end = 0x00a01034 },
434 	{ .start = 0x00a0103c, .end = 0x00a01040 },
435 	{ .start = 0x00a01048, .end = 0x00a01050 },
436 	{ .start = 0x00a01058, .end = 0x00a01058 },
437 	{ .start = 0x00a01060, .end = 0x00a01070 },
438 	{ .start = 0x00a0108c, .end = 0x00a0108c },
439 	{ .start = 0x00a01c20, .end = 0x00a01c28 },
440 	{ .start = 0x00a01d10, .end = 0x00a01d10 },
441 	{ .start = 0x00a01e28, .end = 0x00a01e2c },
442 	{ .start = 0x00a01e60, .end = 0x00a01e60 },
443 	{ .start = 0x00a01e80, .end = 0x00a01e80 },
444 	{ .start = 0x00a01ea0, .end = 0x00a01ea0 },
445 	{ .start = 0x00a02000, .end = 0x00a0201c },
446 	{ .start = 0x00a02024, .end = 0x00a02024 },
447 	{ .start = 0x00a02040, .end = 0x00a02048 },
448 	{ .start = 0x00a020c0, .end = 0x00a020e0 },
449 	{ .start = 0x00a02400, .end = 0x00a02404 },
450 	{ .start = 0x00a0240c, .end = 0x00a02414 },
451 	{ .start = 0x00a0241c, .end = 0x00a0243c },
452 	{ .start = 0x00a02448, .end = 0x00a024bc },
453 	{ .start = 0x00a024c4, .end = 0x00a024cc },
454 	{ .start = 0x00a02508, .end = 0x00a02508 },
455 	{ .start = 0x00a02510, .end = 0x00a02514 },
456 	{ .start = 0x00a0251c, .end = 0x00a0251c },
457 	{ .start = 0x00a0252c, .end = 0x00a0255c },
458 	{ .start = 0x00a02564, .end = 0x00a025a0 },
459 	{ .start = 0x00a025a8, .end = 0x00a025b4 },
460 	{ .start = 0x00a025c0, .end = 0x00a025c0 },
461 	{ .start = 0x00a025e8, .end = 0x00a025f4 },
462 	{ .start = 0x00a02c08, .end = 0x00a02c18 },
463 	{ .start = 0x00a02c2c, .end = 0x00a02c38 },
464 	{ .start = 0x00a02c68, .end = 0x00a02c78 },
465 	{ .start = 0x00a03000, .end = 0x00a03000 },
466 	{ .start = 0x00a03010, .end = 0x00a03014 },
467 	{ .start = 0x00a0301c, .end = 0x00a0302c },
468 	{ .start = 0x00a03034, .end = 0x00a03038 },
469 	{ .start = 0x00a03040, .end = 0x00a03044 },
470 	{ .start = 0x00a03060, .end = 0x00a03068 },
471 	{ .start = 0x00a03070, .end = 0x00a03070 },
472 	{ .start = 0x00a0307c, .end = 0x00a03084 },
473 	{ .start = 0x00a0308c, .end = 0x00a03090 },
474 	{ .start = 0x00a03098, .end = 0x00a03098 },
475 	{ .start = 0x00a030a0, .end = 0x00a030a0 },
476 	{ .start = 0x00a030a8, .end = 0x00a030b4 },
477 	{ .start = 0x00a030bc, .end = 0x00a030c0 },
478 	{ .start = 0x00a030c8, .end = 0x00a030f4 },
479 	{ .start = 0x00a03100, .end = 0x00a0312c },
480 	{ .start = 0x00a03c00, .end = 0x00a03c5c },
481 	{ .start = 0x00a04400, .end = 0x00a04454 },
482 	{ .start = 0x00a04460, .end = 0x00a04474 },
483 	{ .start = 0x00a044c0, .end = 0x00a044ec },
484 	{ .start = 0x00a04500, .end = 0x00a04504 },
485 	{ .start = 0x00a04510, .end = 0x00a04538 },
486 	{ .start = 0x00a04540, .end = 0x00a04548 },
487 	{ .start = 0x00a04560, .end = 0x00a04560 },
488 	{ .start = 0x00a04570, .end = 0x00a0457c },
489 	{ .start = 0x00a04590, .end = 0x00a04590 },
490 	{ .start = 0x00a04598, .end = 0x00a04598 },
491 	{ .start = 0x00a045c0, .end = 0x00a045f4 },
492 	{ .start = 0x00a05c18, .end = 0x00a05c1c },
493 	{ .start = 0x00a0c000, .end = 0x00a0c018 },
494 	{ .start = 0x00a0c020, .end = 0x00a0c028 },
495 	{ .start = 0x00a0c038, .end = 0x00a0c094 },
496 	{ .start = 0x00a0c0c0, .end = 0x00a0c104 },
497 	{ .start = 0x00a0c10c, .end = 0x00a0c118 },
498 	{ .start = 0x00a0c150, .end = 0x00a0c174 },
499 	{ .start = 0x00a0c17c, .end = 0x00a0c188 },
500 	{ .start = 0x00a0c190, .end = 0x00a0c198 },
501 	{ .start = 0x00a0c1a0, .end = 0x00a0c1a8 },
502 	{ .start = 0x00a0c1b0, .end = 0x00a0c1b8 },
506 	{ .start = 0x00d03c00, .end = 0x00d03c64 },
507 	{ .start = 0x00d05c18, .end = 0x00d05c1c },
508 	{ .start = 0x00d0c000, .end = 0x00d0c174 },
516 	for (i = 0; i < len_bytes; i += 4)  in iwl_read_prph_block()
538 	for (i = 0; i < range_len; i++) {  in iwl_dump_prph()
594 		sg_set_page(iter, new_page, alloc_size, 0);  in alloc_sgtable()
609 	for (i = 0; i < range_len; i++) {  in iwl_fw_get_prph_len()
672 	while (0)
679 	u32 fifo_len = 0;  in iwl_fw_rxf_len()
683 		return 0;  in iwl_fw_rxf_len()
692 	for (i = 0; i < mem_cfg->num_lmacs; i++)  in iwl_fw_rxf_len()
703 	u32 fifo_len = 0;  in iwl_fw_txf_len()
713 	for (i = 0; i < mem_cfg->num_lmacs; i++) {  in iwl_fw_txf_len()
716 		for (j = 0; j < mem_cfg->num_txfifo_entries; j++)  in iwl_fw_txf_len()
727 	for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++)  in iwl_fw_txf_len()
782 	u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0;  in iwl_fw_error_dump_file()
783 	u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->cfg->smem_len;  in iwl_fw_error_dump_file()
785 				0 : fwrt->trans->cfg->dccm2_len;  in iwl_fw_error_dump_file()
837 		for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++)  in iwl_fw_error_dump_file()
888 		dump_info->lmac_err_id[0] =  in iwl_fw_error_dump_file()
889 			cpu_to_le32(fwrt->dump.lmac_err_id[0]);  in iwl_fw_error_dump_file()
906 		for (i = 0; i < MAX_NUM_LMAC; i++) {  in iwl_fw_error_dump_file()
910 			for (j = 0; j < TX_FIFO_MAX_NUM; j++)  in iwl_fw_error_dump_file()
920 		for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) {  in iwl_fw_error_dump_file()
961 		for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) {  in iwl_fw_error_dump_file()
1039 	for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) {  in iwl_dump_ini_prph_mac_iter()
1041 		if (prph_val == 0x5a5a5a5a)  in iwl_dump_ini_prph_mac_iter()
1081 	for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) {  in iwl_dump_ini_prph_phy_iter()
1113 	for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4)  in iwl_dump_ini_csr_iter()
1137 	for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) {  in iwl_dump_ini_config_iter()
1142 		if (ret < 0)  in iwl_dump_ini_config_iter()
1261 	u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid[0]);  in iwl_ini_txf_iter()
1265 			IWL_ERR(fwrt, "WRT: Invalid lmac offset 0x%x\n",  in iwl_ini_txf_iter()
1270 		iter->internal_txf = 0;  in iwl_ini_txf_iter()
1271 		iter->fifo_size = 0;  in iwl_ini_txf_iter()
1276 			iter->lmac = 0;  in iwl_ini_txf_iter()
1335 	for (i = 0; i < registers_num; i++) {  in iwl_dump_ini_txf_iter()
1360 	for (i = 0; i < iter->fifo_size; i += sizeof(*data))  in iwl_dump_ini_txf_iter()
1384 	u32 fid1 = le32_to_cpu(reg->fifos.fid[0]);  in iwl_ini_get_rxf_data()
1396 	memset(data, 0, sizeof(*data));  in iwl_ini_get_rxf_data()
1411 					    SHARED_MEM_CFG_CMD, 0) <= 3)  in iwl_ini_get_rxf_data()
1412 			max_idx = 0;  in iwl_ini_get_rxf_data()
1426 		case 0:  in iwl_ini_get_rxf_data()
1469 	for (i = 0; i < registers_num; i++) {  in iwl_dump_ini_rxf_iter()
1487 	iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1);  in iwl_dump_ini_rxf_iter()
1489 	iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1);  in iwl_dump_ini_rxf_iter()
1492 			       0x0);  in iwl_dump_ini_rxf_iter()
1497 	for (i = 0; i < rxf_data.size; i += sizeof(*data))  in iwl_dump_ini_rxf_iter()
1561 	for (i = 0; i < (le32_to_cpu(reg->dev_addr.size) / 4); i++) {  in iwl_dump_ini_dbgi_sram_iter()
1565 		if (prph_data == 0x5a5a5a5a) {  in iwl_dump_ini_dbgi_sram_iter()
1654 	 * DBGC1 address + (0x100 * i)  in iwl_get_mon_reg()
1656 	offs = (alloc_id - IWL_FW_INI_ALLOCATION_ID_DBGC1) * 0x100;  in iwl_get_mon_reg()
1659 		return 0;  in iwl_get_mon_reg()
1788 			return 0;  in iwl_dump_ini_paging_ranges()
1800 	u32 ranges = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id);  in iwl_dump_ini_mon_dram_ranges()
1805 	for (i = 0; i < fw_mon->num_frags; i++) {  in iwl_dump_ini_mon_dram_ranges()
1818 	u32 num_of_fifos = 0;  in iwl_dump_ini_txf_ranges()
1842 	if (imr_enable == 0 || imr_size == 0 || sram_size == 0) {  in iwl_dump_ini_imr_ranges()
1846 		return 0;  in iwl_dump_ini_imr_ranges()
1860 		return 0;  in iwl_dump_ini_mem_get_size()
1892 	u32 size = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id);  in iwl_dump_ini_mon_dram_get_size()
1897 	for (i = 0; i < fw_mon->num_frags; i++) {  in iwl_dump_ini_mon_dram_get_size()
1921 		return 0;  in iwl_dump_ini_mon_smem_get_size()
1937 		return 0;  in iwl_dump_ini_mon_dbgi_get_size()
1949 	u32 size = 0;  in iwl_dump_ini_txf_get_size()
1961 		return 0;  in iwl_dump_ini_txf_get_size()
2017 	u32 size = 0;  in iwl_dump_ini_fw_pkt_get_size()
2020 		return 0;  in iwl_dump_ini_fw_pkt_get_size()
2034 	u32 size = 0;  in iwl_dump_ini_imr_get_size()
2035 	u32 ranges = 0;  in iwl_dump_ini_imr_get_size()
2040 	if (imr_enable == 0 || imr_size == 0 || sram_size == 0) {  in iwl_dump_ini_imr_get_size()
2050 		return 0;  in iwl_dump_ini_imr_get_size()
2083  * Returns the size of the current dump tlv or 0 if failed
2118 			return 0;  in iwl_dump_ini_mem()
2124 			return 0;  in iwl_dump_ini_mem()
2130 			return 0;  in iwl_dump_ini_mem()
2137 		return 0;  in iwl_dump_ini_mem()
2144 		return 0;  in iwl_dump_ini_mem()
2149 		return 0;  in iwl_dump_ini_mem()
2189 	for (i = 0; i < num_of_ranges; i++) {  in iwl_dump_ini_mem()
2193 		if (range_size < 0) {  in iwl_dump_ini_mem()
2218 	return 0;  in iwl_dump_ini_mem()
2231 	u32 num_of_cfg_names = 0;  in iwl_dump_ini_info()
2241 		return 0;  in iwl_dump_ini_info()
2263 	 * Several HWs all have type == 0x42, so we'll override this value  in iwl_dump_ini_info()
2437 	u32 size = 0;  in iwl_dump_ini_trigger()
2445 	for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions); i++) {  in iwl_dump_ini_trigger()
2530 		return 0;  in iwl_dump_ini_file_gen()
2534 		return 0;  in iwl_dump_ini_file_gen()
2541 		return 0;  in iwl_dump_ini_file_gen()
2559 	fwrt->dump.lmac_err_id[0] = 0;  in iwl_fw_free_dump_desc()
2561 		fwrt->dump.lmac_err_id[1] = 0;  in iwl_fw_free_dump_desc()
2562 	fwrt->dump.umac_err_id = 0;  in iwl_fw_free_dump_desc()
2597 				     fw_error_dump.fwrt_len, 0);  in iwl_fw_error_dump()
2643 		u32 offs = 0;  in iwl_fw_error_ini_dump()
2673 		return 0;  in iwl_fw_dbg_collect_desc()
2679 	 * so check against ~0UL first.  in iwl_fw_dbg_collect_desc()
2681 	if (fwrt->dump.active_wks == ~0UL)  in iwl_fw_dbg_collect_desc()
2703 	return 0;  in iwl_fw_dbg_collect_desc()
2732 		iwl_dump_error_desc->len = 0;  in iwl_fw_dbg_error_collect()
2735 					      false, 0);  in iwl_fw_dbg_error_collect()
2744 	return 0;  in iwl_fw_dbg_error_collect()
2754 	unsigned int delay = 0;  in iwl_fw_dbg_collect()
2761 			return 0;  in iwl_fw_dbg_collect()
2767 			return 0;  in iwl_fw_dbg_collect()
2794 	int ret, len = 0;  in iwl_fw_dbg_collect_trig()
2798 		return 0;  in iwl_fw_dbg_collect_trig()
2803 		buf[sizeof(buf) - 1] = '\0';  in iwl_fw_dbg_collect_trig()
2811 			buf[sizeof(buf) - 1] = '\0';  in iwl_fw_dbg_collect_trig()
2822 	return 0;  in iwl_fw_dbg_collect_trig()
2840 		return 0;  in iwl_fw_start_dbg_conf()
2851 	for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) {  in iwl_fw_start_dbg_conf()
2869 	return 0;  in iwl_fw_start_dbg_conf()
2880 		.data[0] = &hcmd_data,  in iwl_send_dbg_dump_complete_cmd()
2881 		.len[0] = sizeof(hcmd_data),  in iwl_send_dbg_dump_complete_cmd()
2900 	struct iwl_fw_dbg_params params = {0};  in iwl_fw_dbg_collect_sync()
2940 		iwl_send_dbg_dump_complete_cmd(fwrt, time_point, 0);  in iwl_fw_dbg_collect_sync()
2974 		return 0;  in iwl_fw_dbg_ini_collect()
2980 	 * so check against ~0UL first.  in iwl_fw_dbg_ini_collect()
2982 	if (fwrt->dump.active_wks == ~0UL)  in iwl_fw_dbg_ini_collect()
2994 		delay = 0;  in iwl_fw_dbg_ini_collect()
3005 	return 0;  in iwl_fw_dbg_ini_collect()
3062 	for (i = 0; i < IWL_FW_RUNTIME_DUMP_WK_NUM; i++)  in iwl_fw_dbg_stop_sync()
3078 		.data[0] = &cmd,  in iwl_fw_dbg_suspend_resume_hcmd()
3079 		.len[0] = sizeof(cmd),  in iwl_fw_dbg_suspend_resume_hcmd()
3089 		iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);  in iwl_fw_dbg_stop_recording()
3098 	iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0);  in iwl_fw_dbg_stop_recording()
3103 	iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0);  in iwl_fw_dbg_stop_recording()
3113 		iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);  in iwl_fw_dbg_restart_recording()
3114 		iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);  in iwl_fw_dbg_restart_recording()
3115 		iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);  in iwl_fw_dbg_restart_recording()
3121 	return 0;  in iwl_fw_dbg_restart_recording()
3128 	int ret __maybe_unused = 0;  in iwl_fw_dbg_stop_restart_recording()