Lines Matching +full:gpio +full:- +full:in +full:- +full:accum
8 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
14 * This program is distributed in the hope that it will be useful, but
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
69 * whenever platform supplies power to device, even when device is in
70 * low power states due to driver-invoked device resets
71 * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
80 * NOTE: Device does need to be awake in order to read this memory
86 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
100 * 31-8: Reserved
101 * 7-4: Type of device: see CSR_HW_REV_TYPE_xxx definitions
102 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
103 * 1-0: "Dash" (-) value, as in A-1, etc.
106 * NOTE: See also CSR_HW_REV_WA_REG (work-around for bug in 4965).
114 * in order to read.
124 * UCODE-DRIVER GP (general purpose) mailbox registers.
138 /* Analog phase-lock-loop configuration */
146 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
147 * 1-0: "Dash" (-) value, as in C-1, etc.
176 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
199 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
225 /* GPIO */
242 * Indicates state of (platform's) hardware RF-Kill switch
243 * 26-24: POWER_SAVE_TYPE
244 * Indicates current power-saving mode:
245 * 000 -- No power saving
246 * 001 -- MAC power-down
247 * 010 -- PHY (radio) power-down
248 * 011 -- Error
249 * 9-6: SYS_CONFIG
253 * Indicates MAC is entering a power-saving sleep power-down.
254 * Not a good time to access device-internal resources.
257 * access to device-internal resources. Host must wait for
258 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
268 * init or post-power-down restore of internal SRAM memory.
270 * SRAM is restored and uCode is in normal operation mode.
271 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
310 * UCODE-DRIVER GP (general purpose) mailbox register 1
321 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
329 * uCode sets this when preparing a power-saving power-down.
330 * uCode resets this when power-up is complete and SRAM is sane.
334 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
362 * HBUS (Host-side Bus)
366 * may be powered-down.
384 * data registers auto-increment the address by one dword.
386 * 0-31: memory address within device
402 * 0-15: register address (offset) within device
403 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
411 * Per-Tx-queue write pointer (idx, really!)
414 * 0-7: queue write idx
415 * 11-8: queue selector