Lines Matching +full:0 +full:x10001
13 #define SDIOD_FBR_SIZE 0x100
16 #define SDIO_FUNC_ENABLE_1 0x02
17 #define SDIO_FUNC_ENABLE_2 0x04
20 #define SDIO_FUNC_READY_1 0x02
21 #define SDIO_FUNC_READY_2 0x04
24 #define INTR_STATUS_FUNC1 0x2
25 #define INTR_STATUS_FUNC2 0x4
28 #define REG_F0_REG_MASK 0x7FF
29 #define REG_F1_MISC_MASK 0x1FFFF
31 /* function 0 vendor specific CCCR registers */
33 #define SDIO_CCCR_BRCM_CARDCAP 0xf0
39 #define SDIO_CCCR_IEN_FUNC0 BIT(0)
43 #define SDIO_CCCR_BRCM_CARDCTRL 0xf1
46 #define SDIO_CCCR_BRCM_SEPINT 0xf2
47 #define SDIO_CCCR_BRCM_SEPINT_MASK BIT(0)
54 #define SBSDIO_SPROM_CS 0x10000
56 #define SBSDIO_SPROM_INFO 0x10001
57 /* sprom indirect access data byte 0 */
58 #define SBSDIO_SPROM_DATA_LOW 0x10002
60 #define SBSDIO_SPROM_DATA_HIGH 0x10003
61 /* sprom indirect access addr byte 0 */
62 #define SBSDIO_SPROM_ADDR_LOW 0x10004
64 #define SBSDIO_GPIO_SELECT 0x10005
66 #define SBSDIO_GPIO_OUT 0x10006
68 #define SBSDIO_GPIO_EN 0x10007
70 #define SBSDIO_WATERMARK 0x10008
72 #define SBSDIO_DEVICE_CTL 0x10009
75 #define SBSDIO_FUNC1_SBADDRLOW 0x1000A
77 #define SBSDIO_FUNC1_SBADDRMID 0x1000B
79 #define SBSDIO_FUNC1_SBADDRHIGH 0x1000C
81 #define SBSDIO_FUNC1_FRAMECTRL 0x1000D
83 #define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E
85 #define SBSDIO_FUNC1_SDIOPULLUP 0x1000F
87 #define SBSDIO_FUNC1_WFRAMEBCLO 0x10019
89 #define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A
91 #define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B
93 #define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C
95 #define SBSDIO_FUNC1_MESBUSYCTRL 0x1001D
97 #define SBSDIO_MESBUSY_RXFIFO_WM_MASK 0x7F
98 #define SBSDIO_MESBUSY_RXFIFO_WM_SHIFT 0
100 #define SBSDIO_MESBUSYCTRL_ENAB 0x80
104 #define SBSDIO_FUNC1_WAKEUPCTRL 0x1001E
105 #define SBSDIO_FUNC1_WCTRL_ALPWAIT_MASK 0x1
106 #define SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT 0
107 #define SBSDIO_FUNC1_WCTRL_HTWAIT_MASK 0x2
109 #define SBSDIO_FUNC1_SLEEPCSR 0x1001F
110 #define SBSDIO_FUNC1_SLEEPCSR_KSO_MASK 0x1
111 #define SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT 0
113 #define SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK 0x2
116 #define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */
117 #define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001F /* f1 misc register end */
122 #define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF
123 #define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000
125 #define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000
128 #define SBSDIO_SBWINDOW_MASK 0xffff8000
130 #define SDIOH_READ 0 /* Read request */
133 #define SDIOH_DATA_FIX 0 /* Fixed addressing */
137 #define SUCCESS 0
198 u32 corecontrol; /* 0x00, rev8 */
204 u16 pcmciamesportaladdr; /* 0x010, rev8 */
214 u32 intstatus; /* 0x020, rev8 */
221 u32 tosbmailbox; /* 0x040, rev8 */
227 u32 sdioaccess; /* 0x050, rev8 */
231 u8 pcmciaframectrl; /* 0x060, rev8 */
237 u32 intrcvlazy; /* 0x100, rev8 */
241 u32 cmd52rd; /* 0x110, rev8 */
260 char cis[512]; /* 0x400-0x5ff, rev6 */
263 char pcmciafcr[256]; /* 0x600-6ff, rev6 */
267 u16 backplanecsr; /* 0x76E, rev6 */
279 u16 spromstatus; /* 0x7BE, rev2 */
282 u16 PAD[0x80];
290 /* Accessors for SDIO Function 0 */
316 * Returns 0 or error code.
331 #define SDIO_REQ_4BYTE 0x1
333 #define SDIO_REQ_FIXED 0x2
336 * rw: read or write (0/1)
340 * Returns 0 or error code.