Lines Matching +full:0 +full:x3c00
46 #define B43legacy_TX4_MAC_KEYIDX 0x0FF00000 /* Security key index */
48 #define B43legacy_TX4_MAC_KEYALG 0x00070000 /* Security key algorithm */
50 #define B43legacy_TX4_MAC_LIFETIME 0x00001000
51 #define B43legacy_TX4_MAC_FRAMEBURST 0x00000800
52 #define B43legacy_TX4_MAC_SENDCTS 0x00000400
53 #define B43legacy_TX4_MAC_AMPDU 0x00000300
55 #define B43legacy_TX4_MAC_CTSFALLBACKOFDM 0x00000200
56 #define B43legacy_TX4_MAC_FALLBACKOFDM 0x00000100
57 #define B43legacy_TX4_MAC_5GHZ 0x00000080
58 #define B43legacy_TX4_MAC_IGNPMQ 0x00000020
59 #define B43legacy_TX4_MAC_HWSEQ 0x00000010 /* Use Hardware Seq No */
60 #define B43legacy_TX4_MAC_STMSDU 0x00000008 /* Start MSDU */
61 #define B43legacy_TX4_MAC_SENDRTS 0x00000004
62 #define B43legacy_TX4_MAC_LONGFRAME 0x00000002
63 #define B43legacy_TX4_MAC_ACK 0x00000001
66 #define B43legacy_TX4_EFT_FBOFDM 0x0001 /* Data frame fb rate type */
67 #define B43legacy_TX4_EFT_RTSOFDM 0x0004 /* RTS/CTS rate type */
68 #define B43legacy_TX4_EFT_RTSFBOFDM 0x0010 /* RTS/CTS fallback rate type */
71 #define B43legacy_TX4_PHY_ENC 0x0003 /* Data frame encoding */
72 #define B43legacy_TX4_PHY_ENC_CCK 0x0000 /* CCK */
73 #define B43legacy_TX4_PHY_ENC_OFDM 0x0001 /* Data frame rate type */
74 #define B43legacy_TX4_PHY_SHORTPRMBL 0x0010 /* Use short preamble */
75 #define B43legacy_TX4_PHY_ANT 0x03C0 /* Antenna selection */
76 #define B43legacy_TX4_PHY_ANT0 0x0000 /* Use antenna 0 */
77 #define B43legacy_TX4_PHY_ANT1 0x0100 /* Use antenna 1 */
78 #define B43legacy_TX4_PHY_ANTLAST 0x0300 /* Use last used antenna */
134 __le16 phy_status0; /* PHY RX Status 0 */
145 /* PHY RX Status 0 */
146 #define B43legacy_RX_PHYST0_GAINCTL 0x4000 /* Gain Control */
147 #define B43legacy_RX_PHYST0_PLCPHCF 0x0200
148 #define B43legacy_RX_PHYST0_PLCPFV 0x0100
149 #define B43legacy_RX_PHYST0_SHORTPRMBL 0x0080 /* Recvd with Short Preamble */
150 #define B43legacy_RX_PHYST0_LCRS 0x0040
151 #define B43legacy_RX_PHYST0_ANT 0x0020 /* Antenna */
152 #define B43legacy_RX_PHYST0_UNSRATE 0x0010
153 #define B43legacy_RX_PHYST0_CLIP 0x000C
155 #define B43legacy_RX_PHYST0_FTYPE 0x0003 /* Frame type */
156 #define B43legacy_RX_PHYST0_CCK 0x0000 /* Frame type: CCK */
157 #define B43legacy_RX_PHYST0_OFDM 0x0001 /* Frame type: OFDM */
158 #define B43legacy_RX_PHYST0_PRE_N 0x0002 /* Pre-standard N-PHY frame */
159 #define B43legacy_RX_PHYST0_STD_N 0x0003 /* Standard N-PHY frame */
162 #define B43legacy_RX_PHYST2_LNAG 0xC000 /* LNA Gain */
164 #define B43legacy_RX_PHYST2_PNAG 0x3C00 /* PNA Gain */
166 #define B43legacy_RX_PHYST2_FOFF 0x03FF /* F offset */
169 #define B43legacy_RX_PHYST3_DIGG 0x1800 /* DIG Gain */
171 #define B43legacy_RX_PHYST3_TRSTATE 0x0400 /* TR state */
174 #define B43legacy_RX_MAC_BEACONSENT 0x00008000 /* Beacon send flag */
175 #define B43legacy_RX_MAC_KEYIDX 0x000007E0 /* Key index */
177 #define B43legacy_RX_MAC_DECERR 0x00000010 /* Decrypt error */
178 #define B43legacy_RX_MAC_DEC 0x00000008 /* Decryption attempted */
179 #define B43legacy_RX_MAC_PADDING 0x00000004 /* Pad bytes present */
180 #define B43legacy_RX_MAC_RESP 0x00000002 /* Response frame xmitted */
181 #define B43legacy_RX_MAC_FCSERR 0x00000001 /* FCS error */
184 #define B43legacy_RX_CHAN_GAIN 0xFC00 /* Gain */
186 #define B43legacy_RX_CHAN_ID 0x03FC /* Channel ID */
188 #define B43legacy_RX_CHAN_PHYTYPE 0x0003 /* PHY type */
214 B43legacy_QOSPARM_TXOP = 0,