Lines Matching +full:c +full:- +full:phy
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 Common PHY routines
7 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
8 Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
9 Copyright (c) 2005-2008 Michael Buesch <m@bues.ch>
10 Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
11 Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
30 struct b43_phy *phy = &(dev->phy); in b43_phy_allocate() local
33 phy->ops = NULL; in b43_phy_allocate()
35 switch (phy->type) { in b43_phy_allocate()
38 phy->ops = &b43_phyops_g; in b43_phy_allocate()
43 phy->ops = &b43_phyops_n; in b43_phy_allocate()
48 phy->ops = &b43_phyops_lp; in b43_phy_allocate()
53 phy->ops = &b43_phyops_ht; in b43_phy_allocate()
58 phy->ops = &b43_phyops_lcn; in b43_phy_allocate()
63 phy->ops = &b43_phyops_ac; in b43_phy_allocate()
67 if (B43_WARN_ON(!phy->ops)) in b43_phy_allocate()
68 return -ENODEV; in b43_phy_allocate()
70 err = phy->ops->allocate(dev); in b43_phy_allocate()
72 phy->ops = NULL; in b43_phy_allocate()
79 dev->phy.ops->free(dev); in b43_phy_free()
80 dev->phy.ops = NULL; in b43_phy_free()
85 struct b43_phy *phy = &dev->phy; in b43_phy_init() local
86 const struct b43_phy_operations *ops = phy->ops; in b43_phy_init()
89 /* During PHY init we need to use some channel. On the first init this in b43_phy_init()
92 if (!phy->chandef) { in b43_phy_init()
93 phy->chandef = &dev->wl->hw->conf.chandef; in b43_phy_init()
94 phy->channel = phy->chandef->chan->hw_value; in b43_phy_init()
97 phy->ops->switch_analog(dev, true); in b43_phy_init()
100 err = ops->init(dev); in b43_phy_init()
102 b43err(dev->wl, "PHY init failed\n"); in b43_phy_init()
105 phy->do_full_init = false; in b43_phy_init()
107 err = b43_switch_channel(dev, phy->channel); in b43_phy_init()
109 b43err(dev->wl, "PHY init: Channel switch to default failed\n"); in b43_phy_init()
116 phy->do_full_init = true; in b43_phy_init()
117 if (ops->exit) in b43_phy_init()
118 ops->exit(dev); in b43_phy_init()
127 const struct b43_phy_operations *ops = dev->phy.ops; in b43_phy_exit()
130 dev->phy.do_full_init = true; in b43_phy_exit()
131 if (ops->exit) in b43_phy_exit()
132 ops->exit(dev); in b43_phy_exit()
137 if (!dev->phy.hardware_power_control) in b43_has_hardware_pctl()
139 if (!dev->phy.ops->supports_hwpctl) in b43_has_hardware_pctl()
141 return dev->phy.ops->supports_hwpctl(dev); in b43_has_hardware_pctl()
149 B43_WARN_ON(dev->phy.radio_locked); in b43_radio_lock()
150 dev->phy.radio_locked = true; in b43_radio_lock()
167 B43_WARN_ON(!dev->phy.radio_locked); in b43_radio_unlock()
168 dev->phy.radio_locked = false; in b43_radio_unlock()
182 B43_WARN_ON(dev->phy.phy_locked); in b43_phy_lock()
183 dev->phy.phy_locked = true; in b43_phy_lock()
185 B43_WARN_ON(dev->dev->core_rev < 3); in b43_phy_lock()
187 if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) in b43_phy_lock()
194 B43_WARN_ON(!dev->phy.phy_locked); in b43_phy_unlock()
195 dev->phy.phy_locked = false; in b43_phy_unlock()
197 B43_WARN_ON(dev->dev->core_rev < 3); in b43_phy_unlock()
199 if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) in b43_phy_unlock()
208 (dev->mac_suspended <= 0)) { in assert_mac_suspended()
209 b43dbg(dev->wl, "PHY/RADIO register access with " in assert_mac_suspended()
218 dev->phy.writes_counter = 0; in b43_radio_read()
219 return dev->phy.ops->radio_read(dev, reg); in b43_radio_read()
225 if (b43_bus_host_is_pci(dev->dev) && in b43_radio_write()
226 ++dev->phy.writes_counter > B43_MAX_WRITES_IN_ROW) { in b43_radio_write()
228 dev->phy.writes_counter = 1; in b43_radio_write()
230 dev->phy.ops->radio_write(dev, reg, value); in b43_radio_write()
269 dev->phy.writes_counter = 0; in b43_phy_read()
271 if (dev->phy.ops->phy_read) in b43_phy_read()
272 return dev->phy.ops->phy_read(dev, reg); in b43_phy_read()
281 if (b43_bus_host_is_pci(dev->dev) && in b43_phy_write()
282 ++dev->phy.writes_counter > B43_MAX_WRITES_IN_ROW) { in b43_phy_write()
284 dev->phy.writes_counter = 1; in b43_phy_write()
287 if (dev->phy.ops->phy_write) in b43_phy_write()
288 return dev->phy.ops->phy_write(dev, reg, value); in b43_phy_write()
301 if (dev->phy.ops->phy_maskset) { in b43_phy_mask()
303 dev->phy.ops->phy_maskset(dev, offset, mask, 0); in b43_phy_mask()
312 if (dev->phy.ops->phy_maskset) { in b43_phy_set()
314 dev->phy.ops->phy_maskset(dev, offset, 0xFFFF, set); in b43_phy_set()
323 if (dev->phy.ops->phy_maskset) { in b43_phy_maskset()
325 dev->phy.ops->phy_maskset(dev, offset, mask, set); in b43_phy_maskset()
336 switch (dev->dev->bus_type) { in b43_phy_put_into_reset()
339 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); in b43_phy_put_into_reset()
343 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); in b43_phy_put_into_reset()
346 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); in b43_phy_put_into_reset()
348 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); in b43_phy_put_into_reset()
354 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); in b43_phy_put_into_reset()
358 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); in b43_phy_put_into_reset()
361 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); in b43_phy_put_into_reset()
363 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); in b43_phy_put_into_reset()
375 switch (dev->dev->bus_type) { in b43_phy_take_out_of_reset()
379 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); in b43_phy_take_out_of_reset()
383 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); in b43_phy_take_out_of_reset()
387 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); in b43_phy_take_out_of_reset()
390 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); in b43_phy_take_out_of_reset()
397 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); in b43_phy_take_out_of_reset()
401 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); in b43_phy_take_out_of_reset()
402 ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */ in b43_phy_take_out_of_reset()
405 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); in b43_phy_take_out_of_reset()
408 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); in b43_phy_take_out_of_reset()
409 ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */ in b43_phy_take_out_of_reset()
418 struct b43_phy *phy = &(dev->phy); in b43_switch_channel() local
426 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) in b43_switch_channel()
434 /* Now try to switch the PHY hardware channel. */ in b43_switch_channel()
435 err = phy->ops->switch_channel(dev, new_channel); in b43_switch_channel()
453 struct b43_phy *phy = &dev->phy; in b43_software_rfkill() local
456 phy->ops->software_rfkill(dev, blocked); in b43_software_rfkill()
457 phy->radio_on = !blocked; in b43_software_rfkill()
462 * b43_phy_txpower_adjust_work - TX power workqueue.
472 mutex_lock(&wl->mutex); in b43_phy_txpower_adjust_work()
473 dev = wl->current_dev; in b43_phy_txpower_adjust_work()
476 dev->phy.ops->adjust_txpower(dev); in b43_phy_txpower_adjust_work()
478 mutex_unlock(&wl->mutex); in b43_phy_txpower_adjust_work()
483 struct b43_phy *phy = &dev->phy; in b43_phy_txpower_check() local
489 if (time_before(now, phy->next_txpwr_check_time)) in b43_phy_txpower_check()
493 phy->next_txpwr_check_time = round_jiffies(now + (HZ * 2)); in b43_phy_txpower_check()
495 if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) && in b43_phy_txpower_check()
496 (dev->dev->board_type == SSB_BOARD_BU4306)) in b43_phy_txpower_check()
499 result = phy->ops->recalc_txpower(dev, !!(flags & B43_TXPWR_IGNORE_TSSI)); in b43_phy_txpower_check()
503 B43_WARN_ON(phy->ops->adjust_txpower == NULL); in b43_phy_txpower_check()
507 ieee80211_queue_work(dev->wl->hw, &dev->wl->txpower_adjust_work); in b43_phy_txpower_check()
513 unsigned int a, b, c, d; in b43_phy_shm_tssi_read() local
520 c = (tmp >> 16) & 0xFF; in b43_phy_shm_tssi_read()
524 c == 0 || c == B43_TSSI_MAX || in b43_phy_shm_tssi_read()
526 return -ENOENT; in b43_phy_shm_tssi_read()
535 c = (c + 32) & 0x3F; in b43_phy_shm_tssi_read()
540 average = (a + b + c + d + 2) / 4; in b43_phy_shm_tssi_read()
542 /* Adjust for CCK-boost */ in b43_phy_shm_tssi_read()
545 average = (average >= 13) ? (average - 13) : 0; in b43_phy_shm_tssi_read()
559 return dev->phy.chandef->width == NL80211_CHAN_WIDTH_40; in b43_is_40mhz()
562 /* https://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
567 WARN_ON(dev->phy.type != B43_PHYTYPE_N && in b43_phy_force_clock()
568 dev->phy.type != B43_PHYTYPE_HT && in b43_phy_force_clock()
569 dev->phy.type != B43_PHYTYPE_AC); in b43_phy_force_clock()
571 switch (dev->dev->bus_type) { in b43_phy_force_clock()
574 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); in b43_phy_force_clock()
579 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); in b43_phy_force_clock()
584 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); in b43_phy_force_clock()
589 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); in b43_phy_force_clock()