Lines Matching +full:txpower +full:-
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
39 (i->qcu << AR_TxQcuNum_S) | desc_len; in ar9003_set_txdesc()
42 WRITE_ONCE(ads->info, val); in ar9003_set_txdesc()
44 checksum += i->link; in ar9003_set_txdesc()
45 WRITE_ONCE(ads->link, i->link); in ar9003_set_txdesc()
47 checksum += i->buf_addr[0]; in ar9003_set_txdesc()
48 WRITE_ONCE(ads->data0, i->buf_addr[0]); in ar9003_set_txdesc()
49 checksum += i->buf_addr[1]; in ar9003_set_txdesc()
50 WRITE_ONCE(ads->data1, i->buf_addr[1]); in ar9003_set_txdesc()
51 checksum += i->buf_addr[2]; in ar9003_set_txdesc()
52 WRITE_ONCE(ads->data2, i->buf_addr[2]); in ar9003_set_txdesc()
53 checksum += i->buf_addr[3]; in ar9003_set_txdesc()
54 WRITE_ONCE(ads->data3, i->buf_addr[3]); in ar9003_set_txdesc()
56 checksum += (val = (i->buf_len[0] << AR_BufLen_S) & AR_BufLen); in ar9003_set_txdesc()
57 WRITE_ONCE(ads->ctl3, val); in ar9003_set_txdesc()
58 checksum += (val = (i->buf_len[1] << AR_BufLen_S) & AR_BufLen); in ar9003_set_txdesc()
59 WRITE_ONCE(ads->ctl5, val); in ar9003_set_txdesc()
60 checksum += (val = (i->buf_len[2] << AR_BufLen_S) & AR_BufLen); in ar9003_set_txdesc()
61 WRITE_ONCE(ads->ctl7, val); in ar9003_set_txdesc()
62 checksum += (val = (i->buf_len[3] << AR_BufLen_S) & AR_BufLen); in ar9003_set_txdesc()
63 WRITE_ONCE(ads->ctl9, val); in ar9003_set_txdesc()
66 WRITE_ONCE(ads->ctl10, checksum); in ar9003_set_txdesc()
68 if (i->is_first || i->is_last) { in ar9003_set_txdesc()
69 WRITE_ONCE(ads->ctl13, set11nTries(i->rates, 0) in ar9003_set_txdesc()
70 | set11nTries(i->rates, 1) in ar9003_set_txdesc()
71 | set11nTries(i->rates, 2) in ar9003_set_txdesc()
72 | set11nTries(i->rates, 3) in ar9003_set_txdesc()
73 | (i->dur_update ? AR_DurUpdateEna : 0) in ar9003_set_txdesc()
76 WRITE_ONCE(ads->ctl14, set11nRate(i->rates, 0) in ar9003_set_txdesc()
77 | set11nRate(i->rates, 1) in ar9003_set_txdesc()
78 | set11nRate(i->rates, 2) in ar9003_set_txdesc()
79 | set11nRate(i->rates, 3)); in ar9003_set_txdesc()
81 WRITE_ONCE(ads->ctl13, 0); in ar9003_set_txdesc()
82 WRITE_ONCE(ads->ctl14, 0); in ar9003_set_txdesc()
85 ads->ctl20 = 0; in ar9003_set_txdesc()
86 ads->ctl21 = 0; in ar9003_set_txdesc()
87 ads->ctl22 = 0; in ar9003_set_txdesc()
88 ads->ctl23 = 0; in ar9003_set_txdesc()
90 ctl17 = SM(i->keytype, AR_EncrType); in ar9003_set_txdesc()
91 if (!i->is_first) { in ar9003_set_txdesc()
92 WRITE_ONCE(ads->ctl11, 0); in ar9003_set_txdesc()
93 WRITE_ONCE(ads->ctl12, i->is_last ? 0 : AR_TxMore); in ar9003_set_txdesc()
94 WRITE_ONCE(ads->ctl15, 0); in ar9003_set_txdesc()
95 WRITE_ONCE(ads->ctl16, 0); in ar9003_set_txdesc()
96 WRITE_ONCE(ads->ctl17, ctl17); in ar9003_set_txdesc()
97 WRITE_ONCE(ads->ctl18, 0); in ar9003_set_txdesc()
98 WRITE_ONCE(ads->ctl19, 0); in ar9003_set_txdesc()
102 WRITE_ONCE(ads->ctl11, (i->pkt_len & AR_FrameLen) in ar9003_set_txdesc()
103 | (i->flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0) in ar9003_set_txdesc()
104 | SM(i->txpower[0], AR_XmitPower0) in ar9003_set_txdesc()
105 | (i->flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0) in ar9003_set_txdesc()
106 | (i->keyix != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0) in ar9003_set_txdesc()
107 | (i->flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0) in ar9003_set_txdesc()
108 | (i->flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0) in ar9003_set_txdesc()
109 | (i->flags & ATH9K_TXDESC_RTSENA ? AR_RTSEnable : in ar9003_set_txdesc()
110 (i->flags & ATH9K_TXDESC_CTSENA ? AR_CTSEnable : 0))); in ar9003_set_txdesc()
112 ctl12 = (i->keyix != ATH9K_TXKEYIX_INVALID ? in ar9003_set_txdesc()
113 SM(i->keyix, AR_DestIdx) : 0) in ar9003_set_txdesc()
114 | SM(i->type, AR_FrameType) in ar9003_set_txdesc()
115 | (i->flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0) in ar9003_set_txdesc()
116 | (i->flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0) in ar9003_set_txdesc()
117 | (i->flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0); in ar9003_set_txdesc()
119 ctl17 |= (i->flags & ATH9K_TXDESC_LDPC ? AR_LDPC : 0); in ar9003_set_txdesc()
120 switch (i->aggr) { in ar9003_set_txdesc()
122 ctl17 |= SM(i->aggr_len, AR_AggrLen); in ar9003_set_txdesc()
126 ctl17 |= SM(i->ndelim, AR_PadDelim); in ar9003_set_txdesc()
135 val = (i->flags & ATH9K_TXDESC_PAPRD) >> ATH9K_TXDESC_PAPRD_S; in ar9003_set_txdesc()
138 WRITE_ONCE(ads->ctl12, ctl12); in ar9003_set_txdesc()
139 WRITE_ONCE(ads->ctl17, ctl17); in ar9003_set_txdesc()
141 WRITE_ONCE(ads->ctl15, set11nPktDurRTSCTS(i->rates, 0) in ar9003_set_txdesc()
142 | set11nPktDurRTSCTS(i->rates, 1)); in ar9003_set_txdesc()
144 WRITE_ONCE(ads->ctl16, set11nPktDurRTSCTS(i->rates, 2) in ar9003_set_txdesc()
145 | set11nPktDurRTSCTS(i->rates, 3)); in ar9003_set_txdesc()
147 WRITE_ONCE(ads->ctl18, in ar9003_set_txdesc()
148 set11nRateFlags(i->rates, 0) | set11nChainSel(i->rates, 0) in ar9003_set_txdesc()
149 | set11nRateFlags(i->rates, 1) | set11nChainSel(i->rates, 1) in ar9003_set_txdesc()
150 | set11nRateFlags(i->rates, 2) | set11nChainSel(i->rates, 2) in ar9003_set_txdesc()
151 | set11nRateFlags(i->rates, 3) | set11nChainSel(i->rates, 3) in ar9003_set_txdesc()
152 | SM(i->rtscts_rate, AR_RTSCTSRate)); in ar9003_set_txdesc()
154 WRITE_ONCE(ads->ctl19, AR_Not_Sounding); in ar9003_set_txdesc()
156 WRITE_ONCE(ads->ctl20, SM(i->txpower[1], AR_XmitPower1)); in ar9003_set_txdesc()
157 WRITE_ONCE(ads->ctl21, SM(i->txpower[2], AR_XmitPower2)); in ar9003_set_txdesc()
158 WRITE_ONCE(ads->ctl22, SM(i->txpower[3], AR_XmitPower3)); in ar9003_set_txdesc()
165 checksum = ads->info + ads->link in ar9003_calc_ptr_chksum()
166 + ads->data0 + ads->ctl3 in ar9003_calc_ptr_chksum()
167 + ads->data1 + ads->ctl5 in ar9003_calc_ptr_chksum()
168 + ads->data2 + ads->ctl7 in ar9003_calc_ptr_chksum()
169 + ads->data3 + ads->ctl9; in ar9003_calc_ptr_chksum()
178 ads->link = ds_link; in ar9003_hw_set_desc_link()
179 ads->ctl10 &= ~AR_TxPtrChkSum; in ar9003_hw_set_desc_link()
180 ads->ctl10 |= ar9003_calc_ptr_chksum(ads); in ar9003_hw_set_desc_link()
188 struct ath9k_hw_capabilities *pCap = &ah->caps; in ar9003_hw_get_isr()
234 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { in ar9003_hw_get_isr()
240 if ((pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) in ar9003_hw_get_isr()
250 if (ah->config.rx_intr_mitigation) in ar9003_hw_get_isr()
254 if (ah->config.tx_intr_mitigation) in ar9003_hw_get_isr()
267 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { in ar9003_hw_get_isr()
282 if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) in ar9003_hw_get_isr()
287 ah->intr_gen_timer_trigger = in ar9003_hw_get_isr()
290 ah->intr_gen_timer_thresh = in ar9003_hw_get_isr()
293 if (ah->intr_gen_timer_trigger) in ar9003_hw_get_isr()
296 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { in ar9003_hw_get_isr()
305 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { in ar9003_hw_get_isr()
361 ads = &ah->ts_ring[ah->ts_tail]; in ar9003_hw_proc_txdesc()
363 status = READ_ONCE(ads->status8); in ar9003_hw_proc_txdesc()
365 return -EINPROGRESS; in ar9003_hw_proc_txdesc()
367 ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size; in ar9003_hw_proc_txdesc()
369 if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) || in ar9003_hw_proc_txdesc()
370 (MS(ads->ds_info, AR_TxRxDesc) != 1)) { in ar9003_hw_proc_txdesc()
372 "Tx Descriptor error %x\n", ads->ds_info); in ar9003_hw_proc_txdesc()
374 return -EIO; in ar9003_hw_proc_txdesc()
377 ts->ts_rateindex = MS(status, AR_FinalTxIdx); in ar9003_hw_proc_txdesc()
378 ts->ts_seqnum = MS(status, AR_SeqNum); in ar9003_hw_proc_txdesc()
379 ts->tid = MS(status, AR_TxTid); in ar9003_hw_proc_txdesc()
381 ts->qid = MS(ads->ds_info, AR_TxQcuNum); in ar9003_hw_proc_txdesc()
382 ts->desc_id = MS(ads->status1, AR_TxDescId); in ar9003_hw_proc_txdesc()
383 ts->ts_tstamp = ads->status4; in ar9003_hw_proc_txdesc()
384 ts->ts_status = 0; in ar9003_hw_proc_txdesc()
385 ts->ts_flags = 0; in ar9003_hw_proc_txdesc()
388 ts->ts_status |= ATH9K_TXERR_XTXOP; in ar9003_hw_proc_txdesc()
389 status = READ_ONCE(ads->status2); in ar9003_hw_proc_txdesc()
390 ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00); in ar9003_hw_proc_txdesc()
391 ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01); in ar9003_hw_proc_txdesc()
392 ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02); in ar9003_hw_proc_txdesc()
394 ts->ts_flags |= ATH9K_TX_BA; in ar9003_hw_proc_txdesc()
395 ts->ba_low = ads->status5; in ar9003_hw_proc_txdesc()
396 ts->ba_high = ads->status6; in ar9003_hw_proc_txdesc()
399 status = READ_ONCE(ads->status3); in ar9003_hw_proc_txdesc()
401 ts->ts_status |= ATH9K_TXERR_XRETRY; in ar9003_hw_proc_txdesc()
403 ts->ts_status |= ATH9K_TXERR_FILT; in ar9003_hw_proc_txdesc()
405 ts->ts_status |= ATH9K_TXERR_FIFO; in ar9003_hw_proc_txdesc()
409 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED; in ar9003_hw_proc_txdesc()
411 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR; in ar9003_hw_proc_txdesc()
413 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN; in ar9003_hw_proc_txdesc()
417 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN; in ar9003_hw_proc_txdesc()
420 ts->ts_shortretry = MS(status, AR_RTSFailCnt); in ar9003_hw_proc_txdesc()
421 ts->ts_longretry = MS(status, AR_DataFailCnt); in ar9003_hw_proc_txdesc()
422 ts->ts_virtcol = MS(status, AR_VirtRetryCnt); in ar9003_hw_proc_txdesc()
424 status = READ_ONCE(ads->status7); in ar9003_hw_proc_txdesc()
425 ts->ts_rssi = MS(status, AR_TxRSSICombined); in ar9003_hw_proc_txdesc()
426 ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10); in ar9003_hw_proc_txdesc()
427 ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11); in ar9003_hw_proc_txdesc()
428 ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12); in ar9003_hw_proc_txdesc()
441 return MS(READ_ONCE(adc->ctl15), AR_PacketDur0); in ar9003_hw_get_duration()
443 return MS(READ_ONCE(adc->ctl15), AR_PacketDur1); in ar9003_hw_get_duration()
445 return MS(READ_ONCE(adc->ctl16), AR_PacketDur2); in ar9003_hw_get_duration()
447 return MS(READ_ONCE(adc->ctl16), AR_PacketDur3); in ar9003_hw_get_duration()
457 ops->rx_enable = ar9003_hw_rx_enable; in ar9003_hw_attach_mac_ops()
458 ops->set_desc_link = ar9003_hw_set_desc_link; in ar9003_hw_attach_mac_ops()
459 ops->get_isr = ar9003_hw_get_isr; in ar9003_hw_attach_mac_ops()
460 ops->set_txdesc = ar9003_set_txdesc; in ar9003_hw_attach_mac_ops()
461 ops->proc_txdesc = ar9003_hw_proc_txdesc; in ar9003_hw_attach_mac_ops()
462 ops->get_duration = ar9003_hw_get_duration; in ar9003_hw_attach_mac_ops()
487 if ((rxsp->status11 & AR_RxDone) == 0) in ath9k_hw_process_rxdesc_edma()
488 return -EINPROGRESS; in ath9k_hw_process_rxdesc_edma()
490 if (MS(rxsp->ds_info, AR_DescId) != 0x168c) in ath9k_hw_process_rxdesc_edma()
491 return -EINVAL; in ath9k_hw_process_rxdesc_edma()
493 if ((rxsp->ds_info & (AR_TxRxDesc | AR_CtrlStat)) != 0) in ath9k_hw_process_rxdesc_edma()
494 return -EINPROGRESS; in ath9k_hw_process_rxdesc_edma()
496 rxs->rs_status = 0; in ath9k_hw_process_rxdesc_edma()
497 rxs->rs_flags = 0; in ath9k_hw_process_rxdesc_edma()
498 rxs->enc_flags = 0; in ath9k_hw_process_rxdesc_edma()
499 rxs->bw = RATE_INFO_BW_20; in ath9k_hw_process_rxdesc_edma()
501 rxs->rs_datalen = rxsp->status2 & AR_DataLen; in ath9k_hw_process_rxdesc_edma()
502 rxs->rs_tstamp = rxsp->status3; in ath9k_hw_process_rxdesc_edma()
505 rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined); in ath9k_hw_process_rxdesc_edma()
506 rxs->rs_rssi_ctl[0] = MS(rxsp->status1, AR_RxRSSIAnt00); in ath9k_hw_process_rxdesc_edma()
507 rxs->rs_rssi_ctl[1] = MS(rxsp->status1, AR_RxRSSIAnt01); in ath9k_hw_process_rxdesc_edma()
508 rxs->rs_rssi_ctl[2] = MS(rxsp->status1, AR_RxRSSIAnt02); in ath9k_hw_process_rxdesc_edma()
509 rxs->rs_rssi_ext[0] = MS(rxsp->status5, AR_RxRSSIAnt10); in ath9k_hw_process_rxdesc_edma()
510 rxs->rs_rssi_ext[1] = MS(rxsp->status5, AR_RxRSSIAnt11); in ath9k_hw_process_rxdesc_edma()
511 rxs->rs_rssi_ext[2] = MS(rxsp->status5, AR_RxRSSIAnt12); in ath9k_hw_process_rxdesc_edma()
513 if (rxsp->status11 & AR_RxKeyIdxValid) in ath9k_hw_process_rxdesc_edma()
514 rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx); in ath9k_hw_process_rxdesc_edma()
516 rxs->rs_keyix = ATH9K_RXKEYIX_INVALID; in ath9k_hw_process_rxdesc_edma()
518 rxs->rs_rate = MS(rxsp->status1, AR_RxRate); in ath9k_hw_process_rxdesc_edma()
519 rxs->rs_more = (rxsp->status2 & AR_RxMore) ? 1 : 0; in ath9k_hw_process_rxdesc_edma()
521 rxs->rs_firstaggr = (rxsp->status11 & AR_RxFirstAggr) ? 1 : 0; in ath9k_hw_process_rxdesc_edma()
522 rxs->rs_isaggr = (rxsp->status11 & AR_RxAggr) ? 1 : 0; in ath9k_hw_process_rxdesc_edma()
523 rxs->rs_moreaggr = (rxsp->status11 & AR_RxMoreAggr) ? 1 : 0; in ath9k_hw_process_rxdesc_edma()
524 rxs->rs_antenna = (MS(rxsp->status4, AR_RxAntenna) & 0x7); in ath9k_hw_process_rxdesc_edma()
525 rxs->enc_flags |= (rxsp->status4 & AR_GI) ? RX_ENC_FLAG_SHORT_GI : 0; in ath9k_hw_process_rxdesc_edma()
526 rxs->enc_flags |= in ath9k_hw_process_rxdesc_edma()
527 (rxsp->status4 & AR_STBC) ? (1 << RX_ENC_FLAG_STBC_SHIFT) : 0; in ath9k_hw_process_rxdesc_edma()
528 rxs->bw = (rxsp->status4 & AR_2040) ? RATE_INFO_BW_40 : RATE_INFO_BW_20; in ath9k_hw_process_rxdesc_edma()
530 rxs->evm0 = rxsp->status6; in ath9k_hw_process_rxdesc_edma()
531 rxs->evm1 = rxsp->status7; in ath9k_hw_process_rxdesc_edma()
532 rxs->evm2 = rxsp->status8; in ath9k_hw_process_rxdesc_edma()
533 rxs->evm3 = rxsp->status9; in ath9k_hw_process_rxdesc_edma()
534 rxs->evm4 = (rxsp->status10 & 0xffff); in ath9k_hw_process_rxdesc_edma()
536 if (rxsp->status11 & AR_PreDelimCRCErr) in ath9k_hw_process_rxdesc_edma()
537 rxs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE; in ath9k_hw_process_rxdesc_edma()
539 if (rxsp->status11 & AR_PostDelimCRCErr) in ath9k_hw_process_rxdesc_edma()
540 rxs->rs_flags |= ATH9K_RX_DELIM_CRC_POST; in ath9k_hw_process_rxdesc_edma()
542 if (rxsp->status11 & AR_DecryptBusyErr) in ath9k_hw_process_rxdesc_edma()
543 rxs->rs_flags |= ATH9K_RX_DECRYPT_BUSY; in ath9k_hw_process_rxdesc_edma()
545 if ((rxsp->status11 & AR_RxFrameOK) == 0) { in ath9k_hw_process_rxdesc_edma()
554 if (rxsp->status11 & AR_CRCErr) in ath9k_hw_process_rxdesc_edma()
555 rxs->rs_status |= ATH9K_RXERR_CRC; in ath9k_hw_process_rxdesc_edma()
556 else if (rxsp->status11 & AR_DecryptCRCErr) in ath9k_hw_process_rxdesc_edma()
557 rxs->rs_status |= ATH9K_RXERR_DECRYPT; in ath9k_hw_process_rxdesc_edma()
558 else if (rxsp->status11 & AR_MichaelErr) in ath9k_hw_process_rxdesc_edma()
559 rxs->rs_status |= ATH9K_RXERR_MIC; in ath9k_hw_process_rxdesc_edma()
560 if (rxsp->status11 & AR_PHYErr) { in ath9k_hw_process_rxdesc_edma()
561 phyerr = MS(rxsp->status11, AR_PHYErrCode); in ath9k_hw_process_rxdesc_edma()
573 * delimiter for an A-MPDU subframe (0x4E = 'N' ASCII). in ath9k_hw_process_rxdesc_edma()
576 (rxsp->status11 & AR_PostDelimCRCErr)) { in ath9k_hw_process_rxdesc_edma()
577 rxs->rs_phyerr = 0; in ath9k_hw_process_rxdesc_edma()
579 rxs->rs_status |= ATH9K_RXERR_PHY; in ath9k_hw_process_rxdesc_edma()
580 rxs->rs_phyerr = phyerr; in ath9k_hw_process_rxdesc_edma()
585 if (rxsp->status11 & AR_KeyMiss) in ath9k_hw_process_rxdesc_edma()
586 rxs->rs_status |= ATH9K_RXERR_KEYMISS; in ath9k_hw_process_rxdesc_edma()
594 ah->ts_tail = 0; in ath9k_hw_reset_txstatus_ring()
596 memset((void *) ah->ts_ring, 0, in ath9k_hw_reset_txstatus_ring()
597 ah->ts_size * sizeof(struct ar9003_txs)); in ath9k_hw_reset_txstatus_ring()
601 ah->ts_paddr_start, ah->ts_paddr_end, in ath9k_hw_reset_txstatus_ring()
602 ah->ts_ring, ah->ts_size); in ath9k_hw_reset_txstatus_ring()
604 REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start); in ath9k_hw_reset_txstatus_ring()
605 REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end); in ath9k_hw_reset_txstatus_ring()
613 ah->ts_paddr_start = ts_paddr_start; in ath9k_hw_setup_statusring()
614 ah->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9003_txs)); in ath9k_hw_setup_statusring()
615 ah->ts_size = size; in ath9k_hw_setup_statusring()
616 ah->ts_ring = ts_start; in ath9k_hw_setup_statusring()