Lines Matching +full:txpower +full:-
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
29 ((struct ath_desc*) ds)->ds_link = ds_link; in ar9002_hw_set_desc_link()
37 struct ath9k_hw_capabilities *pCap = &ah->caps; in ar9002_hw_get_isr()
81 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { in ar9002_hw_get_isr()
87 if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) in ar9002_hw_get_isr()
108 if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) { in ar9002_hw_get_isr()
123 ah->intr_txqs = MS(s0_s, AR_ISR_S0_QCU_TXOK); in ar9002_hw_get_isr()
124 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); in ar9002_hw_get_isr()
125 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); in ar9002_hw_get_isr()
126 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); in ar9002_hw_get_isr()
140 if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) { in ar9002_hw_get_isr()
146 ah->intr_gen_timer_trigger = in ar9002_hw_get_isr()
149 ah->intr_gen_timer_thresh = in ar9002_hw_get_isr()
152 if (ah->intr_gen_timer_trigger) in ar9002_hw_get_isr()
156 !(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) in ar9002_hw_get_isr()
159 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { in ar9002_hw_get_isr()
165 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { in ar9002_hw_get_isr()
217 ads->ds_txstatus0 = ads->ds_txstatus1 = 0; in ar9002_set_txdesc()
218 ads->ds_txstatus2 = ads->ds_txstatus3 = 0; in ar9002_set_txdesc()
219 ads->ds_txstatus4 = ads->ds_txstatus5 = 0; in ar9002_set_txdesc()
220 ads->ds_txstatus6 = ads->ds_txstatus7 = 0; in ar9002_set_txdesc()
221 ads->ds_txstatus8 = ads->ds_txstatus9 = 0; in ar9002_set_txdesc()
223 WRITE_ONCE(ads->ds_link, i->link); in ar9002_set_txdesc()
224 WRITE_ONCE(ads->ds_data, i->buf_addr[0]); in ar9002_set_txdesc()
226 ctl1 = i->buf_len[0] | (i->is_last ? 0 : AR_TxMore); in ar9002_set_txdesc()
227 ctl6 = SM(i->keytype, AR_EncrType); in ar9002_set_txdesc()
230 ads->ds_ctl8 = 0; in ar9002_set_txdesc()
231 ads->ds_ctl9 = 0; in ar9002_set_txdesc()
232 ads->ds_ctl10 = 0; in ar9002_set_txdesc()
233 ads->ds_ctl11 = 0; in ar9002_set_txdesc()
236 if ((i->is_first || i->is_last) && in ar9002_set_txdesc()
237 i->aggr != AGGR_BUF_MIDDLE && i->aggr != AGGR_BUF_LAST) { in ar9002_set_txdesc()
238 WRITE_ONCE(ads->ds_ctl2, set11nTries(i->rates, 0) in ar9002_set_txdesc()
239 | set11nTries(i->rates, 1) in ar9002_set_txdesc()
240 | set11nTries(i->rates, 2) in ar9002_set_txdesc()
241 | set11nTries(i->rates, 3) in ar9002_set_txdesc()
242 | (i->dur_update ? AR_DurUpdateEna : 0) in ar9002_set_txdesc()
245 WRITE_ONCE(ads->ds_ctl3, set11nRate(i->rates, 0) in ar9002_set_txdesc()
246 | set11nRate(i->rates, 1) in ar9002_set_txdesc()
247 | set11nRate(i->rates, 2) in ar9002_set_txdesc()
248 | set11nRate(i->rates, 3)); in ar9002_set_txdesc()
250 WRITE_ONCE(ads->ds_ctl2, 0); in ar9002_set_txdesc()
251 WRITE_ONCE(ads->ds_ctl3, 0); in ar9002_set_txdesc()
254 if (!i->is_first) { in ar9002_set_txdesc()
255 WRITE_ONCE(ads->ds_ctl0, 0); in ar9002_set_txdesc()
256 WRITE_ONCE(ads->ds_ctl1, ctl1); in ar9002_set_txdesc()
257 WRITE_ONCE(ads->ds_ctl6, ctl6); in ar9002_set_txdesc()
261 ctl1 |= (i->keyix != ATH9K_TXKEYIX_INVALID ? SM(i->keyix, AR_DestIdx) : 0) in ar9002_set_txdesc()
262 | SM(i->type, AR_FrameType) in ar9002_set_txdesc()
263 | (i->flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0) in ar9002_set_txdesc()
264 | (i->flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0) in ar9002_set_txdesc()
265 | (i->flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0); in ar9002_set_txdesc()
267 switch (i->aggr) { in ar9002_set_txdesc()
269 ctl6 |= SM(i->aggr_len, AR_AggrLen); in ar9002_set_txdesc()
273 ctl6 |= SM(i->ndelim, AR_PadDelim); in ar9002_set_txdesc()
282 WRITE_ONCE(ads->ds_ctl0, (i->pkt_len & AR_FrameLen) in ar9002_set_txdesc()
283 | (i->flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0) in ar9002_set_txdesc()
284 | SM(i->txpower[0], AR_XmitPower0) in ar9002_set_txdesc()
285 | (i->flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0) in ar9002_set_txdesc()
286 | (i->flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0) in ar9002_set_txdesc()
287 | (i->keyix != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0) in ar9002_set_txdesc()
288 | (i->flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0) in ar9002_set_txdesc()
289 | (i->flags & ATH9K_TXDESC_RTSENA ? AR_RTSEnable : in ar9002_set_txdesc()
290 (i->flags & ATH9K_TXDESC_CTSENA ? AR_CTSEnable : 0))); in ar9002_set_txdesc()
292 WRITE_ONCE(ads->ds_ctl1, ctl1); in ar9002_set_txdesc()
293 WRITE_ONCE(ads->ds_ctl6, ctl6); in ar9002_set_txdesc()
295 if (i->aggr == AGGR_BUF_MIDDLE || i->aggr == AGGR_BUF_LAST) in ar9002_set_txdesc()
298 WRITE_ONCE(ads->ds_ctl4, set11nPktDurRTSCTS(i->rates, 0) in ar9002_set_txdesc()
299 | set11nPktDurRTSCTS(i->rates, 1)); in ar9002_set_txdesc()
301 WRITE_ONCE(ads->ds_ctl5, set11nPktDurRTSCTS(i->rates, 2) in ar9002_set_txdesc()
302 | set11nPktDurRTSCTS(i->rates, 3)); in ar9002_set_txdesc()
304 WRITE_ONCE(ads->ds_ctl7, in ar9002_set_txdesc()
305 set11nRateFlags(i->rates, 0) | set11nChainSel(i->rates, 0) in ar9002_set_txdesc()
306 | set11nRateFlags(i->rates, 1) | set11nChainSel(i->rates, 1) in ar9002_set_txdesc()
307 | set11nRateFlags(i->rates, 2) | set11nChainSel(i->rates, 2) in ar9002_set_txdesc()
308 | set11nRateFlags(i->rates, 3) | set11nChainSel(i->rates, 3) in ar9002_set_txdesc()
309 | SM(i->rtscts_rate, AR_RTSCTSRate)); in ar9002_set_txdesc()
311 WRITE_ONCE(ads->ds_ctl9, SM(i->txpower[1], AR_XmitPower1)); in ar9002_set_txdesc()
312 WRITE_ONCE(ads->ds_ctl10, SM(i->txpower[2], AR_XmitPower2)); in ar9002_set_txdesc()
313 WRITE_ONCE(ads->ds_ctl11, SM(i->txpower[3], AR_XmitPower3)); in ar9002_set_txdesc()
322 status = READ_ONCE(ads->ds_txstatus9); in ar9002_hw_proc_txdesc()
324 return -EINPROGRESS; in ar9002_hw_proc_txdesc()
326 ts->ts_tstamp = ads->AR_SendTimestamp; in ar9002_hw_proc_txdesc()
327 ts->ts_status = 0; in ar9002_hw_proc_txdesc()
328 ts->ts_flags = 0; in ar9002_hw_proc_txdesc()
331 ts->ts_status |= ATH9K_TXERR_XTXOP; in ar9002_hw_proc_txdesc()
332 ts->tid = MS(status, AR_TxTid); in ar9002_hw_proc_txdesc()
333 ts->ts_rateindex = MS(status, AR_FinalTxIdx); in ar9002_hw_proc_txdesc()
334 ts->ts_seqnum = MS(status, AR_SeqNum); in ar9002_hw_proc_txdesc()
336 status = READ_ONCE(ads->ds_txstatus0); in ar9002_hw_proc_txdesc()
337 ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00); in ar9002_hw_proc_txdesc()
338 ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01); in ar9002_hw_proc_txdesc()
339 ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02); in ar9002_hw_proc_txdesc()
341 ts->ts_flags |= ATH9K_TX_BA; in ar9002_hw_proc_txdesc()
342 ts->ba_low = ads->AR_BaBitmapLow; in ar9002_hw_proc_txdesc()
343 ts->ba_high = ads->AR_BaBitmapHigh; in ar9002_hw_proc_txdesc()
346 status = READ_ONCE(ads->ds_txstatus1); in ar9002_hw_proc_txdesc()
348 ts->ts_status |= ATH9K_TX_ACKED; in ar9002_hw_proc_txdesc()
351 ts->ts_status |= ATH9K_TXERR_XRETRY; in ar9002_hw_proc_txdesc()
353 ts->ts_status |= ATH9K_TXERR_FILT; in ar9002_hw_proc_txdesc()
355 ts->ts_status |= ATH9K_TXERR_FIFO; in ar9002_hw_proc_txdesc()
360 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED; in ar9002_hw_proc_txdesc()
362 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR; in ar9002_hw_proc_txdesc()
364 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN; in ar9002_hw_proc_txdesc()
368 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN; in ar9002_hw_proc_txdesc()
371 ts->ts_shortretry = MS(status, AR_RTSFailCnt); in ar9002_hw_proc_txdesc()
372 ts->ts_longretry = MS(status, AR_DataFailCnt); in ar9002_hw_proc_txdesc()
373 ts->ts_virtcol = MS(status, AR_VirtRetryCnt); in ar9002_hw_proc_txdesc()
375 status = READ_ONCE(ads->ds_txstatus5); in ar9002_hw_proc_txdesc()
376 ts->ts_rssi = MS(status, AR_TxRSSICombined); in ar9002_hw_proc_txdesc()
377 ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10); in ar9002_hw_proc_txdesc()
378 ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11); in ar9002_hw_proc_txdesc()
379 ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12); in ar9002_hw_proc_txdesc()
381 ts->evm0 = ads->AR_TxEVM0; in ar9002_hw_proc_txdesc()
382 ts->evm1 = ads->AR_TxEVM1; in ar9002_hw_proc_txdesc()
383 ts->evm2 = ads->AR_TxEVM2; in ar9002_hw_proc_txdesc()
394 return MS(READ_ONCE(ads->ds_ctl4), AR_PacketDur0); in ar9002_hw_get_duration()
396 return MS(READ_ONCE(ads->ds_ctl4), AR_PacketDur1); in ar9002_hw_get_duration()
398 return MS(READ_ONCE(ads->ds_ctl5), AR_PacketDur2); in ar9002_hw_get_duration()
400 return MS(READ_ONCE(ads->ds_ctl5), AR_PacketDur3); in ar9002_hw_get_duration()
402 return -1; in ar9002_hw_get_duration()
411 ads->ds_ctl1 = size & AR_BufLen; in ath9k_hw_setuprxdesc()
413 ads->ds_ctl1 |= AR_RxIntrReq; in ath9k_hw_setuprxdesc()
415 memset(&ads->u.rx, 0, sizeof(ads->u.rx)); in ath9k_hw_setuprxdesc()
423 ops->rx_enable = ar9002_hw_rx_enable; in ar9002_hw_attach_mac_ops()
424 ops->set_desc_link = ar9002_hw_set_desc_link; in ar9002_hw_attach_mac_ops()
425 ops->get_isr = ar9002_hw_get_isr; in ar9002_hw_attach_mac_ops()
426 ops->set_txdesc = ar9002_set_txdesc; in ar9002_hw_attach_mac_ops()
427 ops->proc_txdesc = ar9002_hw_proc_txdesc; in ar9002_hw_attach_mac_ops()
428 ops->get_duration = ar9002_hw_get_duration; in ar9002_hw_attach_mac_ops()