Lines Matching defs:ath11k_hw_regs
334 struct ath11k_hw_regs { struct
335 u32 hal_tcl1_ring_base_lsb;
336 u32 hal_tcl1_ring_base_msb;
337 u32 hal_tcl1_ring_id;
338 u32 hal_tcl1_ring_misc;
339 u32 hal_tcl1_ring_tp_addr_lsb;
340 u32 hal_tcl1_ring_tp_addr_msb;
341 u32 hal_tcl1_ring_consumer_int_setup_ix0;
342 u32 hal_tcl1_ring_consumer_int_setup_ix1;
343 u32 hal_tcl1_ring_msi1_base_lsb;
344 u32 hal_tcl1_ring_msi1_base_msb;
345 u32 hal_tcl1_ring_msi1_data;
346 u32 hal_tcl2_ring_base_lsb;
347 u32 hal_tcl_ring_base_lsb;
349 u32 hal_tcl_status_ring_base_lsb;
351 u32 hal_reo1_ring_base_lsb;
352 u32 hal_reo1_ring_base_msb;
353 u32 hal_reo1_ring_id;
354 u32 hal_reo1_ring_misc;
355 u32 hal_reo1_ring_hp_addr_lsb;
356 u32 hal_reo1_ring_hp_addr_msb;
357 u32 hal_reo1_ring_producer_int_setup;
358 u32 hal_reo1_ring_msi1_base_lsb;
359 u32 hal_reo1_ring_msi1_base_msb;
360 u32 hal_reo1_ring_msi1_data;
361 u32 hal_reo2_ring_base_lsb;
362 u32 hal_reo1_aging_thresh_ix_0;
363 u32 hal_reo1_aging_thresh_ix_1;
364 u32 hal_reo1_aging_thresh_ix_2;
365 u32 hal_reo1_aging_thresh_ix_3;
367 u32 hal_reo1_ring_hp;
368 u32 hal_reo1_ring_tp;
369 u32 hal_reo2_ring_hp;
371 u32 hal_reo_tcl_ring_base_lsb;
372 u32 hal_reo_tcl_ring_hp;
374 u32 hal_reo_status_ring_base_lsb;
375 u32 hal_reo_status_hp;
377 u32 hal_reo_cmd_ring_base_lsb;
378 u32 hal_reo_cmd_ring_hp;
403 extern const struct ath11k_hw_regs ipq8074_regs; argument