3588 	lockdep_assert_held(&ar->htt.tx_lock);  in ath10k_mac_tx_lock()
3609 	lockdep_assert_held(&ar->htt.tx_lock);  in ath10k_mac_tx_unlock()
3629 	lockdep_assert_held(&ar->htt.tx_lock);  in ath10k_mac_vif_tx_lock()
3640 	lockdep_assert_held(&ar->htt.tx_lock);  in ath10k_mac_vif_tx_unlock()
3660 	lockdep_assert_held(&ar->htt.tx_lock);  in ath10k_mac_vif_handle_tx_pause()
3705 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_handle_tx_pause_vdev()
3710 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_handle_tx_pause_vdev()
3748 	if (ar->htt.target_version_major < 3 &&  in ath10k_mac_tx_h_get_txmode()
3950 	return (ar->htt.target_version_major >= 3 &&  in ath10k_mac_tx_frm_has_freq()
3951 		ar->htt.target_version_minor >= 4 &&  in ath10k_mac_tx_frm_has_freq()
3986 		else if (ar->htt.target_version_major >= 3)  in ath10k_mac_tx_h_get_txpath()
4000 	struct ath10k_htt *htt = &ar->htt;  in ath10k_mac_tx_submit()  local
4005 		ret = ath10k_htt_tx(htt, txmode, skb);  in ath10k_mac_tx_submit()
4008 		ret = ath10k_htt_mgmt_tx(htt, skb);  in ath10k_mac_tx_submit()
4278 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_txq_unref()
4279 	idr_for_each_entry(&ar->htt.pending_tx, msdu, msdu_id) {  in ath10k_mac_txq_unref()
4284 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_txq_unref()
4317 	if (ar->htt.tx_q_state.mode == HTT_TX_MODE_SWITCH_PUSH)  in ath10k_mac_tx_can_push()
4320 	if (ar->htt.num_pending_tx < ar->htt.tx_q_state.num_push_allowed)  in ath10k_mac_tx_can_push()
4379 	struct ath10k_htt *htt = &ar->htt;  in ath10k_mac_tx_push_txq()  local
4392 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4393 	ret = ath10k_htt_tx_inc_pending(htt);  in ath10k_mac_tx_push_txq()
4394 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4401 		spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4402 		ath10k_htt_tx_dec_pending(htt);  in ath10k_mac_tx_push_txq()
4403 		spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4420 		spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4421 		ret = ath10k_htt_tx_mgmt_inc_pending(htt, is_mgmt, is_presp);  in ath10k_mac_tx_push_txq()
4424 			ath10k_htt_tx_dec_pending(htt);  in ath10k_mac_tx_push_txq()
4425 			spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4428 		spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4435 		spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4436 		ath10k_htt_tx_dec_pending(htt);  in ath10k_mac_tx_push_txq()
4438 			ath10k_htt_tx_mgmt_dec_pending(htt);  in ath10k_mac_tx_push_txq()
4439 		spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4444 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4446 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4478 	if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH)  in ath10k_mac_tx_push_pending()
4481 	if (ar->htt.num_pending_tx >= (ar->htt.max_num_pending_tx / 2))  in ath10k_mac_tx_push_pending()
4664 	struct ath10k_htt *htt = &ar->htt;  in ath10k_mac_op_tx()  local
4688 		spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4695 		ret = ath10k_htt_tx_inc_pending(htt);  in ath10k_mac_op_tx()
4699 			spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4704 		ret = ath10k_htt_tx_mgmt_inc_pending(htt, is_mgmt, is_presp);  in ath10k_mac_op_tx()
4708 			ath10k_htt_tx_dec_pending(htt);  in ath10k_mac_op_tx()
4709 			spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4713 		spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4720 			spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4721 			ath10k_htt_tx_dec_pending(htt);  in ath10k_mac_op_tx()
4723 				ath10k_htt_tx_mgmt_dec_pending(htt);  in ath10k_mac_op_tx()
4724 			spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4738 	if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH)  in ath10k_mac_op_wake_tx_queue()
5850 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_add_interface()
5853 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_add_interface()
6001 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_remove_interface()
6003 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_remove_interface()
8054 	time_left = wait_event_timeout(ar->htt.empty_tx_wq, ({  in ath10k_mac_wait_tx_complete()
8057 			spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_wait_tx_complete()
8058 			empty = (ar->htt.num_pending_tx == 0);  in ath10k_mac_wait_tx_complete()
8059 			spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_wait_tx_complete()
8088 			ath10k_htt_flush_tx(&ar->htt);  in ath10k_flush()
9331 	if (ar->htt.disable_tx_comp) {  in ath10k_sta_statistics()