Lines Matching +full:0 +full:x1234
23 #define QCA988X_2_0_DEVICE_ID_UBNT (0x11ac)
24 #define QCA988X_2_0_DEVICE_ID (0x003c)
25 #define QCA6164_2_1_DEVICE_ID (0x0041)
26 #define QCA6174_2_1_DEVICE_ID (0x003e)
27 #define QCA6174_3_2_DEVICE_ID (0x0042)
28 #define QCA99X0_2_0_DEVICE_ID (0x0040)
29 #define QCA9888_2_0_DEVICE_ID (0x0056)
30 #define QCA9984_1_0_DEVICE_ID (0x0046)
31 #define QCA9377_1_0_DEVICE_ID (0x0042)
32 #define QCA9887_1_0_DEVICE_ID (0x0050)
35 #define QCA988X_HW_1_0_CHIP_ID_REV 0x0
38 #define QCA988X_HW_2_0_VERSION 0x4100016c
39 #define QCA988X_HW_2_0_CHIP_ID_REV 0x2
40 #define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0"
42 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234
45 #define QCA9887_HW_1_0_VERSION 0x4100016d
46 #define QCA9887_HW_1_0_CHIP_ID_REV 0
47 #define QCA9887_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9887/hw1.0"
49 #define QCA9887_HW_1_0_PATCH_LOAD_ADDR 0x1234
52 #define QCA6174_HW_1_0_VERSION 0x05000000
53 #define QCA6174_HW_1_1_VERSION 0x05000001
54 #define QCA6174_HW_1_3_VERSION 0x05000003
55 #define QCA6174_HW_2_1_VERSION 0x05010000
56 #define QCA6174_HW_3_0_VERSION 0x05020000
57 #define QCA6174_HW_3_2_VERSION 0x05030000
60 #define QCA9377_HW_1_0_DEV_VERSION 0x05020000
61 #define QCA9377_HW_1_1_DEV_VERSION 0x05020001
64 QCA6174_PCI_REV_1_1 = 0x11,
65 QCA6174_PCI_REV_1_3 = 0x13,
66 QCA6174_PCI_REV_2_0 = 0x20,
67 QCA6174_PCI_REV_3_0 = 0x30,
71 QCA6174_HW_1_0_CHIP_ID_REV = 0,
82 QCA9377_HW_1_0_CHIP_ID_REV = 0x0,
83 QCA9377_HW_1_1_CHIP_ID_REV = 0x1,
88 #define QCA6174_HW_2_1_PATCH_LOAD_ADDR 0x1234
90 #define QCA6174_HW_3_0_FW_DIR ATH10K_FW_DIR "/QCA6174/hw3.0"
92 #define QCA6174_HW_3_0_PATCH_LOAD_ADDR 0x1234
95 #define QCA99X0_HW_1_0_CHIP_ID_REV 0x0
98 #define QCA99X0_HW_2_0_DEV_VERSION 0x01000000
99 #define QCA99X0_HW_2_0_CHIP_ID_REV 0x1
100 #define QCA99X0_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA99X0/hw2.0"
102 #define QCA99X0_HW_2_0_PATCH_LOAD_ADDR 0x1234
105 #define QCA9984_HW_1_0_DEV_VERSION 0x1000000
106 #define QCA9984_HW_DEV_TYPE 0xa
107 #define QCA9984_HW_1_0_CHIP_ID_REV 0x0
108 #define QCA9984_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9984/hw1.0"
111 #define QCA9984_HW_1_0_PATCH_LOAD_ADDR 0x1234
114 #define QCA9888_HW_2_0_DEV_VERSION 0x1000000
115 #define QCA9888_HW_DEV_TYPE 0xc
116 #define QCA9888_HW_2_0_CHIP_ID_REV 0x0
117 #define QCA9888_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA9888/hw2.0"
119 #define QCA9888_HW_2_0_PATCH_LOAD_ADDR 0x1234
122 #define QCA9377_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9377/hw1.0"
124 #define QCA9377_HW_1_0_PATCH_LOAD_ADDR 0x1234
127 #define QCA4019_HW_1_0_DEV_VERSION 0x01000000
128 #define QCA4019_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA4019/hw1.0"
130 #define QCA4019_HW_1_0_PATCH_LOAD_ADDR 0x1234
134 #define WCN3990_HW_1_0_FW_DIR ATH10K_FW_DIR "/WCN3990/hw1.0"
172 ATH10K_FW_IE_FW_VERSION = 0,
193 ATH10K_FW_WMI_OP_VERSION_UNSET = 0,
207 ATH10K_FW_HTT_OP_VERSION_UNSET = 0,
224 ATH10K_BD_IE_BOARD = 0,
229 ATH10K_BD_IE_BOARD_NAME = 0,
421 ATH10K_HW_TXRX_RAW = 0,
434 ATH10K_MCAST2UCAST_DISABLED = 0,
439 ATH10K_HW_RATE_OFDM_48M = 0,
450 ATH10K_HW_RATE_CCK_LP_11M = 0,
470 ATH10K_HW_CC_WRAP_DISABLED = 0,
473 * wraparound which resets to 0x7fffffff instead of 0. All
481 * by 1, i.e reset to 0x7fffffff, and other counters will be
491 ATH10K_HW_REFCLK_48_MHZ = 0,
668 return 0; in ath10k_tx_data_rssi_get_pad_bytes()
677 return 0; in ath10k_is_rssi_enable()
684 #define TARGET_DMA_BURST_SIZE 0
685 #define TARGET_MAC_AGGR_DELIM 0
690 #define TARGET_NUM_OFFLOAD_PEERS 0
691 #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0
694 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
695 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
704 #define TARGET_NUM_MCAST_GROUPS 0
705 #define TARGET_NUM_MCAST_TABLE_ELEMS 0
708 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0
709 #define TARGET_VOW_CONFIG 0
711 #define TARGET_MAX_FRAG_ENTRIES 0
717 #define TARGET_10X_DMA_BURST_SIZE 0
718 #define TARGET_10X_MAC_AGGR_DELIM 0
726 #define TARGET_10X_NUM_OFFLOAD_PEERS 0
727 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0
734 #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
735 #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
743 #define TARGET_10X_NUM_MCAST_GROUPS 0
744 #define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0
748 #define TARGET_10X_VOW_CONFIG 0
750 #define TARGET_10X_MAX_FRAG_ENTRIES 0
753 #define TARGET_10_2_DMA_BURST_SIZE 0
784 #define TARGET_10_4_ACTIVE_PEERS 0
789 #define TARGET_10_4_NUM_OFFLOAD_PEERS 0
790 #define TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS 0
810 #define TARGET_10_4_NUM_MCAST_GROUPS 0
811 #define TARGET_10_4_NUM_MCAST_TABLE_ELEMS 0
812 #define TARGET_10_4_MCAST2UCAST_MODE 0
817 #define TARGET_10_4_MAC_AGGR_DELIM 0
819 #define TARGET_10_4_VOW_CONFIG 0
823 #define TARGET_10_4_SMART_ANT_CAP 0
824 #define TARGET_10_4_BK_MIN_FREE 0
825 #define TARGET_10_4_BE_MIN_FREE 0
826 #define TARGET_10_4_VI_MIN_FREE 0
827 #define TARGET_10_4_VO_MIN_FREE 0
829 #define TARGET_10_4_THERMAL_THROTTLING_CONFIG 0
830 #define TARGET_10_4_ATF_CONFIG 0
832 #define TARGET_10_4_QWRAP_CONFIG 0
853 #define MSI_ASSIGN_FW 0
862 #define RTC_STATE_V_LSB 0
863 #define RTC_STATE_V_MASK 0x00000007
864 #define RTC_STATE_ADDRESS 0x0000
865 #define PCIE_SOC_WAKE_V_MASK 0x00000001
866 #define PCIE_SOC_WAKE_ADDRESS 0x0004
867 #define PCIE_SOC_WAKE_RESET 0x00000000
868 #define SOC_GLOBAL_RESET_ADDRESS 0x0008
872 #define MAC_COEX_BASE_ADDRESS 0x00006000
873 #define BT_COEX_BASE_ADDRESS 0x00007000
874 #define SOC_PCIE_BASE_ADDRESS 0x00008000
876 #define WLAN_UART_BASE_ADDRESS 0x0000c000
877 #define WLAN_SI_BASE_ADDRESS 0x00010000
878 #define WLAN_GPIO_BASE_ADDRESS 0x00014000
879 #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000
881 #define EFUSE_BASE_ADDRESS 0x00030000
882 #define FPGA_REG_BASE_ADDRESS 0x00039000
883 #define WLAN_UART2_BASE_ADDRESS 0x00054c00
893 #define DBI_BASE_ADDRESS 0x00060000
894 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000
897 #define SOC_RESET_CONTROL_ADDRESS 0x00000000
898 #define SOC_RESET_CONTROL_OFFSET 0x00000000
901 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040
902 #define SOC_CPU_CLOCK_OFFSET 0x00000020
903 #define SOC_CPU_CLOCK_STANDARD_LSB 0
904 #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003
905 #define SOC_CLOCK_CONTROL_OFFSET 0x00000028
906 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001
907 #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4
908 #define SOC_LPO_CAL_OFFSET 0x000000e0
910 #define SOC_LPO_CAL_ENABLE_MASK 0x00100000
911 #define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050
912 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004
916 #define SOC_CHIP_ID_REV_MASK 0x00000f00
918 #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008
919 #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004
920 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0
921 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001
923 #define WLAN_GPIO_PIN0_ADDRESS 0x00000028
925 #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800
927 #define WLAN_GPIO_PIN0_PAD_PULL_MASK 0x00000060
928 #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c
929 #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800
930 #define WLAN_GPIO_PIN10_ADDRESS 0x00000050
931 #define WLAN_GPIO_PIN11_ADDRESS 0x00000054
932 #define WLAN_GPIO_PIN12_ADDRESS 0x00000058
933 #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c
935 #define CLOCK_GPIO_OFFSET 0xffffffff
936 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0
937 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0
939 #define SI_CONFIG_OFFSET 0x00000000
941 #define SI_CONFIG_ERR_INT_MASK 0x00080000
943 #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000
945 #define SI_CONFIG_I2C_MASK 0x00010000
947 #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080
949 #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020
951 #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010
952 #define SI_CONFIG_DIVIDER_LSB 0
953 #define SI_CONFIG_DIVIDER_MASK 0x0000000f
954 #define SI_CS_OFFSET 0x00000004
956 #define SI_CS_DONE_ERR_MASK 0x00000400
958 #define SI_CS_DONE_INT_MASK 0x00000200
960 #define SI_CS_START_MASK 0x00000100
962 #define SI_CS_RX_CNT_MASK 0x000000f0
963 #define SI_CS_TX_CNT_LSB 0
964 #define SI_CS_TX_CNT_MASK 0x0000000f
966 #define SI_TX_DATA0_OFFSET 0x00000008
967 #define SI_TX_DATA1_OFFSET 0x0000000c
968 #define SI_RX_DATA0_OFFSET 0x00000010
969 #define SI_RX_DATA1_OFFSET 0x00000014
971 #define CORE_CTRL_CPU_INTR_MASK 0x00002000
972 #define CORE_CTRL_PCIE_REG_31_MASK 0x00000800
973 #define CORE_CTRL_ADDRESS 0x0000
974 #define PCIE_INTR_ENABLE_ADDRESS 0x0008
975 #define PCIE_INTR_CAUSE_ADDRESS 0x000c
978 #define CPU_INTR_ADDRESS 0x0010
979 #define FW_RAM_CONFIG_ADDRESS 0x0018
987 #define FW_IND_HOST_READY 0x80000000
993 #define DRAM_BASE_ADDRESS 0x00400000
995 #define PCIE_BAR_REG_ADDRESS 0x40030
997 #define MISSING 0
1016 #define LOCAL_SCRATCH_OFFSET 0x18
1071 #define QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS 0x00000010
1073 #define QCA9887_EEPROM_SELECT_READ 0xa10000a0
1074 #define QCA9887_EEPROM_ADDR_HI_MASK 0x0000ff00
1076 #define QCA9887_EEPROM_ADDR_LO_MASK 0x00ff0000
1079 #define MBOX_RESET_CONTROL_ADDRESS 0x00000000
1080 #define MBOX_HOST_INT_STATUS_ADDRESS 0x00000800
1082 #define MBOX_HOST_INT_STATUS_ERROR_MASK 0x00000080
1084 #define MBOX_HOST_INT_STATUS_CPU_MASK 0x00000040
1086 #define MBOX_HOST_INT_STATUS_COUNTER_MASK 0x00000010
1087 #define MBOX_CPU_INT_STATUS_ADDRESS 0x00000801
1088 #define MBOX_ERROR_INT_STATUS_ADDRESS 0x00000802
1090 #define MBOX_ERROR_INT_STATUS_WAKEUP_MASK 0x00000004
1092 #define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002
1093 #define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_LSB 0
1094 #define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001
1095 #define MBOX_COUNTER_INT_STATUS_ADDRESS 0x00000803
1096 #define MBOX_COUNTER_INT_STATUS_COUNTER_LSB 0
1097 #define MBOX_COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff
1098 #define MBOX_RX_LOOKAHEAD_VALID_ADDRESS 0x00000805
1099 #define MBOX_INT_STATUS_ENABLE_ADDRESS 0x00000828
1101 #define MBOX_INT_STATUS_ENABLE_ERROR_MASK 0x00000080
1103 #define MBOX_INT_STATUS_ENABLE_CPU_MASK 0x00000040
1105 #define MBOX_INT_STATUS_ENABLE_INT_MASK 0x00000020
1107 #define MBOX_INT_STATUS_ENABLE_COUNTER_MASK 0x00000010
1108 #define MBOX_INT_STATUS_ENABLE_MBOX_DATA_LSB 0
1109 #define MBOX_INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f
1110 #define MBOX_CPU_INT_STATUS_ENABLE_ADDRESS 0x00000819
1111 #define MBOX_CPU_INT_STATUS_ENABLE_BIT_LSB 0
1112 #define MBOX_CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
1113 #define MBOX_CPU_STATUS_ENABLE_ASSERT_MASK 0x00000001
1114 #define MBOX_ERROR_STATUS_ENABLE_ADDRESS 0x0000081a
1116 #define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002
1117 #define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0
1118 #define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001
1119 #define MBOX_COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000081b
1120 #define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_LSB 0
1121 #define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
1122 #define MBOX_COUNT_ADDRESS 0x00000820
1123 #define MBOX_COUNT_DEC_ADDRESS 0x00000840
1124 #define MBOX_WINDOW_DATA_ADDRESS 0x00000874
1125 #define MBOX_WINDOW_WRITE_ADDR_ADDRESS 0x00000878
1126 #define MBOX_WINDOW_READ_ADDR_ADDRESS 0x0000087c
1127 #define MBOX_CPU_DBG_SEL_ADDRESS 0x00000883
1128 #define MBOX_CPU_DBG_ADDRESS 0x00000884
1129 #define MBOX_RTC_BASE_ADDRESS 0x00000000
1130 #define MBOX_GPIO_BASE_ADDRESS 0x00005000
1131 #define MBOX_MBOX_BASE_ADDRESS 0x00008000
1142 #define WAVE1_PCU_ACK_CTS_TIMEOUT 0x8014
1143 #define WAVE1_PCU_ACK_CTS_TIMEOUT_MAX 0x00003FFF
1144 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_MASK 0x00003FFF
1145 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_LSB 0
1146 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_MASK 0x3FFF0000
1149 #define WAVE1_PCU_GBL_IFS_SLOT 0x1070
1150 #define WAVE1_PCU_GBL_IFS_SLOT_MASK 0x0000FFFF
1151 #define WAVE1_PCU_GBL_IFS_SLOT_MAX 0x0000FFFF
1152 #define WAVE1_PCU_GBL_IFS_SLOT_LSB 0
1153 #define WAVE1_PCU_GBL_IFS_SLOT_RESV0 0xFFFF0000
1155 #define WAVE1_PHYCLK 0x801C
1156 #define WAVE1_PHYCLK_USEC_MASK 0x0000007F
1157 #define WAVE1_PHYCLK_USEC_LSB 0
1160 #define SOC_CORE_CLK_CTRL_OFFSET 0x00000114
1161 #define SOC_CORE_CLK_CTRL_DIV_LSB 0
1162 #define SOC_CORE_CLK_CTRL_DIV_MASK 0x00000007
1164 #define EFUSE_OFFSET 0x0000032c
1166 #define EFUSE_XTAL_SEL_MASK 0x00000700
1168 #define BB_PLL_CONFIG_OFFSET 0x000002f4
1169 #define BB_PLL_CONFIG_FRAC_LSB 0
1170 #define BB_PLL_CONFIG_FRAC_MASK 0x0003ffff
1172 #define BB_PLL_CONFIG_OUTDIV_MASK 0x001c0000
1174 #define WLAN_PLL_SETTLE_OFFSET 0x0018
1175 #define WLAN_PLL_SETTLE_TIME_LSB 0
1176 #define WLAN_PLL_SETTLE_TIME_MASK 0x000007ff
1178 #define WLAN_PLL_CONTROL_OFFSET 0x0014
1179 #define WLAN_PLL_CONTROL_DIV_LSB 0
1180 #define WLAN_PLL_CONTROL_DIV_MASK 0x000003ff
1182 #define WLAN_PLL_CONTROL_REFDIV_MASK 0x00003c00
1184 #define WLAN_PLL_CONTROL_BYPASS_MASK 0x00010000
1186 #define WLAN_PLL_CONTROL_NOPWD_MASK 0x00040000
1188 #define RTC_SYNC_STATUS_OFFSET 0x0244
1190 #define RTC_SYNC_STATUS_PLL_CHANGING_MASK 0x00000020
1193 /* CPU_ADDR_MSB is a register, bit[3:0] is to specify which memory
1195 * If host wants to access 0xX12345 at target, then CPU_ADDR_MSB[3:0]
1196 * is 0xX.
1197 * The following MACROs are defined to get the 0xX and the size limit.
1201 #define REGION_ACCESS_SIZE_LIMIT 0x100000