Lines Matching full:d2
319 movel #TX_BUFFERS - 2, %d2 // D2 = TX_BUFFERS - 1 counter
328 dbfw %d2, open_port_tx_loop
335 movel #RX_BUFFERS - 2, %d2 // D2 = RX_BUFFERS - 1 counter
340 dbfw %d2, open_port_rx_loop
452 movel %d1, %d2 // D1 = D2 = tx_out BD# = desc#
453 mulul #DESC_LENGTH, %d2 // D2 = TX desc offset
454 addl ch_status_addr(%d0), %d2
455 addl #STATUS_TX_DESCS, %d2 // D2 = TX desc address
456 cmpl #PACKET_FULL, (%d2) // desc status
460 movel 4(%d2), %a0 // PCI address
465 movel 8(%d2), %d2 // D2 = length
466 movew %d2, 2(%d1) // length into BD
467 memcpy_from_pci %a0, %a1, %d2
490 movew (%d1), %d2 // D2 = RX BD flags
491 btstl #15, %d2
494 btstl #1, %d2
499 bclrl #2, %d2 // do not test for CRC errors
501 andw #0x0CBC, %d2 // mask status bits
502 cmpw #0x0C00, %d2 // correct frame
511 movel rx_out, %d2
512 mulul #DESC_LENGTH, %d2
513 addl rx_descs_addr, %d2 // D2 = RX desc address
514 cmpl #PACKET_EMPTY, (%d2) // desc stat
517 movel %d3, 8(%d2)
519 movel 4(%d2), %a1
524 movel packet_full(%d0), (%d2) // update desc stat
528 movel rx_out, %d2
529 addl #1, %d2
530 cmpl #RX_QUEUE_LENGTH, %d2
532 clrl %d2
533 rx_1: movel %d2, rx_out
548 movel ch_status_addr(%d0), %d2
549 addl #1, STATUS_RX_OVERRUNS(%d2)
553 movel ch_status_addr(%d0), %d2
554 addl #1, STATUS_RX_FRAME_ERRORS(%d2)
567 movel %d1, %d2 // D1 = D2 = tx_in BD# = desc#
586 mulul #DESC_LENGTH, %d2 // D2 = TX desc offset
587 addl ch_status_addr(%d0), %d2
588 addl #STATUS_TX_DESCS, %d2 // D2 = TX desc address
591 movel #PACKET_SENT, (%d2)
595 movel #PACKET_UNDERRUN, (%d2)
687 movel %d2, -(%sp)
722 movew #0x80E7, %d2 // D2 = input mask: ignore DSR
726 movew csr_output(%d0), %d2
727 andw #0x3000, %d2 // D2 = requested LL and DTR bits
728 orw %d2, %d1 // D1 = all requested output bits
729 movew #0x80FF, %d2 // D2 = input mask: include DSR
749 andw %d2, %d1 // input mask
764 movel (%sp)+, %d2