Lines Matching +full:reg +full:- +full:addr
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * hd64572.h Description of the Hitachi HD64572 (SCA-II), valid for
8 * Copyright: (c) 2000-2001 Cyclades Corp.
15 * PC300 initial CVS version (3.4.0-pre1)
28 #define PABR0L 0x20 /* Physical Addr Boundary Register 0 L */
29 #define PABR0H 0x21 /* Physical Addr Boundary Register 0 H */
30 #define PABR1L 0x22 /* Physical Addr Boundary Register 1 L */
31 #define PABR1H 0x23 /* Physical Addr Boundary Register 1 H */
46 #define M_REG(reg, chan) (reg + 0x80*chan) /* MSCI */ argument
47 #define DRX_REG(reg, chan) (reg + 0x40*chan) /* DMA Rx */ argument
48 #define DTX_REG(reg, chan) (reg + 0x20*(2*chan + 1)) /* DMA Tx */ argument
49 #define TRX_REG(reg, chan) (reg + 0x20*chan) /* Timer Rx */ argument
50 #define TTX_REG(reg, chan) (reg + 0x10*(2*chan + 1)) /* Timer Tx */ argument
51 #define ST_REG(reg, chan) (reg + 0x80*chan) /* Status Cnt */ argument
60 #define MD0 0x138 /* Mode reg 0 */
61 #define MD1 0x139 /* Mode reg 1 */
62 #define MD2 0x13a /* Mode reg 2 */
63 #define MD3 0x13b /* Mode reg 3 */
64 #define CTL 0x130 /* Control reg */
70 #define CMD 0x128 /* Command reg */
71 #define ST0 0x118 /* Status reg 0 */
72 #define ST1 0x119 /* Status reg 1 */
73 #define ST2 0x11a /* Status reg 2 */
74 #define ST3 0x11b /* Status reg 3 */
75 #define ST4 0x11c /* Status reg 4 */
76 #define FST 0x11d /* frame Status reg */
77 #define IE0 0x120 /* Interrupt enable reg 0 */
78 #define IE1 0x121 /* Interrupt enable reg 1 */
79 #define IE2 0x122 /* Interrupt enable reg 2 */
80 #define IE4 0x124 /* Interrupt enable reg 4 */
81 #define FIE 0x125 /* Frame Interrupt enable reg */
82 #define SA0 0x140 /* Syn Address reg 0 */
83 #define SA1 0x141 /* Syn Address reg 1 */
85 #define TRBL 0x100 /* TX/RX buffer reg L */
86 #define TRBK 0x101 /* TX/RX buffer reg K */
87 #define TRBJ 0x102 /* TX/RX buffer reg J */
88 #define TRBH 0x103 /* TX/RX buffer reg H */
89 #define TRC0 0x148 /* TX Ready control reg 0 */
90 #define TRC1 0x149 /* TX Ready control reg 1 */
91 #define RRC 0x14a /* RX Ready control reg */
96 #define GPO 0x131 /* General Purpose Output Pin Ctl Reg */
97 #define TFS 0x14b /* Tx Start Threshold Ctl Reg */
98 #define TFN 0x143 /* Inter-transmit-frame Time Fill Ctl Reg */
99 #define TBN 0x110 /* Tx Buffer Number Reg */
100 #define RBN 0x111 /* Rx Buffer Number Reg */
101 #define TNR0 0x150 /* Tx DMA Request Ctl Reg 0 */
102 #define TNR1 0x151 /* Tx DMA Request Ctl Reg 1 */
103 #define TCR 0x152 /* Tx DMA Critical Request Reg */
104 #define RNR 0x154 /* Rx DMA Request Ctl Reg */
105 #define RCR 0x156 /* Rx DMA Critical Request Reg */
121 #define PCR 0x40 /* DMA priority control reg */
122 #define DRR 0x44 /* DMA reset reg */
123 #define DMER 0x07 /* DMA Master Enable reg */
124 #define BTCR 0x08 /* Burst Tx Ctl Reg */
125 #define BOLR 0x0c /* Back-off Length Reg */
126 #define DSR_RX(chan) (0x48 + 2*chan) /* DMA Status Reg (Rx) */
127 #define DSR_TX(chan) (0x49 + 2*chan) /* DMA Status Reg (Tx) */
128 #define DIR_RX(chan) (0x4c + 2*chan) /* DMA Interrupt Enable Reg (Rx) */
129 #define DIR_TX(chan) (0x4d + 2*chan) /* DMA Interrupt Enable Reg (Tx) */
132 #define DMR_RX(chan) (0x54 + 2*chan) /* DMA Mode Reg (Rx) */
133 #define DMR_TX(chan) (0x55 + 2*chan) /* DMA Mode Reg (Tx) */
134 #define DCR_RX(chan) (0x58 + 2*chan) /* DMA Command Reg (Rx) */
135 #define DCR_TX(chan) (0x59 + 2*chan) /* DMA Command Reg (Tx) */
143 #define DARL 0x80 /* Dest Addr Register L (single-block, RX only) */
144 #define DARH 0x81 /* Dest Addr Register H (single-block, RX only) */
145 #define DARB 0x82 /* Dest Addr Register B (single-block, RX only) */
146 #define DARBH 0x83 /* Dest Addr Register BH (single-block, RX only) */
147 #define SARL 0x80 /* Source Addr Register L (single-block, TX only) */
148 #define SARH 0x81 /* Source Addr Register H (single-block, TX only) */
149 #define SARB 0x82 /* Source Addr Register B (single-block, TX only) */
150 #define DARBH 0x83 /* Source Addr Register BH (single-block, TX only) */
151 #define BARL 0x80 /* Buffer Addr Register L (chained-block) */
152 #define BARH 0x81 /* Buffer Addr Register H (chained-block) */
153 #define BARB 0x82 /* Buffer Addr Register B (chained-block) */
154 #define BARBH 0x83 /* Buffer Addr Register BH (chained-block) */
155 #define CDAL 0x84 /* Current Descriptor Addr Register L */
156 #define CDAH 0x85 /* Current Descriptor Addr Register H */
157 #define CDAB 0x86 /* Current Descriptor Addr Register B */
158 #define CDABH 0x87 /* Current Descriptor Addr Register BH */
159 #define EDAL 0x88 /* Error Descriptor Addr Register L */
160 #define EDAH 0x89 /* Error Descriptor Addr Register H */
161 #define EDAB 0x8a /* Error Descriptor Addr Register B */
162 #define EDABH 0x8b /* Error Descriptor Addr Register BH */
183 u8 unused; /* pads to 4-byte boundary */
193 6 - Short Frame
194 5 - Abort
195 4 - Residual bit
197 2 - CRC
199 0 EOT -
229 #define CMCR 0x158 /* Counter Master Ctl Reg */
233 #define TECCR 0x163 /* Tx EOM Counter Ctl Reg */
236 #define URCCR 0x167 /* Underrun Counter Ctl Reg */
240 #define RECCR 0x16b /* Rx EOM Counter Ctl Reg */
243 #define ORCCR 0x16f /* Overrun Counter Ctl Reg */
246 #define CECCR 0x173 /* CRC Counter Ctl Reg */
249 #define ABCCR 0x177 /* Abort frame Counter Ctl Reg */
252 #define SHCCR 0x17b /* Short frame Counter Ctl Reg */
255 #define RSCCR 0x17f /* Residual bit Counter Ctl Reg */
284 #define MD0_HDLC 0x80 /* Bit-sync HDLC mode */