Lines Matching +full:interrupt +full:- +full:counter
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * hd64572.h Description of the Hitachi HD64572 (SCA-II), valid for
8 * Copyright: (c) 2000-2001 Cyclades Corp.
15 * PC300 initial CVS version (3.4.0-pre1)
36 /* Interrupt Registers */
37 #define IVR 0x60 /* Interrupt Vector Register */
38 #define IMVR 0x64 /* Interrupt Modified Vector Register */
39 #define ITCR 0x68 /* Interrupt Control Register */
40 #define ISR0 0x6c /* Interrupt Status Register 0 */
41 #define ISR1 0x70 /* Interrupt Status Register 1 */
42 #define IER0 0x74 /* Interrupt Enable Register 0 */
43 #define IER1 0x78 /* Interrupt Enable Register 1 */
77 #define IE0 0x120 /* Interrupt enable reg 0 */
78 #define IE1 0x121 /* Interrupt enable reg 1 */
79 #define IE2 0x122 /* Interrupt enable reg 2 */
80 #define IE4 0x124 /* Interrupt enable reg 4 */
81 #define FIE 0x125 /* Frame Interrupt enable reg */
98 #define TFN 0x143 /* Inter-transmit-frame Time Fill Ctl Reg */
125 #define BOLR 0x0c /* Back-off Length Reg */
128 #define DIR_RX(chan) (0x4c + 2*chan) /* DMA Interrupt Enable Reg (Rx) */
129 #define DIR_TX(chan) (0x4d + 2*chan) /* DMA Interrupt Enable Reg (Tx) */
130 #define FCT_RX(chan) (0x50 + 2*chan) /* Frame End Interrupt Counter (Rx) */
131 #define FCT_TX(chan) (0x51 + 2*chan) /* Frame End Interrupt Counter (Tx) */
143 #define DARL 0x80 /* Dest Addr Register L (single-block, RX only) */
144 #define DARH 0x81 /* Dest Addr Register H (single-block, RX only) */
145 #define DARB 0x82 /* Dest Addr Register B (single-block, RX only) */
146 #define DARBH 0x83 /* Dest Addr Register BH (single-block, RX only) */
147 #define SARL 0x80 /* Source Addr Register L (single-block, TX only) */
148 #define SARH 0x81 /* Source Addr Register H (single-block, TX only) */
149 #define SARB 0x82 /* Source Addr Register B (single-block, TX only) */
150 #define DARBH 0x83 /* Source Addr Register BH (single-block, TX only) */
151 #define BARL 0x80 /* Buffer Addr Register L (chained-block) */
152 #define BARH 0x81 /* Buffer Addr Register H (chained-block) */
153 #define BARB 0x82 /* Buffer Addr Register B (chained-block) */
154 #define BARBH 0x83 /* Buffer Addr Register BH (chained-block) */
183 u8 unused; /* pads to 4-byte boundary */
193 6 - Short Frame
194 5 - Abort
195 4 - Residual bit
197 2 - CRC
199 0 EOT -
228 /* Status Counter Registers */
229 #define CMCR 0x158 /* Counter Master Ctl Reg */
230 #define TECNTL 0x160 /* Tx EOM Counter L */
231 #define TECNTM 0x161 /* Tx EOM Counter M */
232 #define TECNTH 0x162 /* Tx EOM Counter H */
233 #define TECCR 0x163 /* Tx EOM Counter Ctl Reg */
234 #define URCNTL 0x164 /* Underrun Counter L */
235 #define URCNTH 0x165 /* Underrun Counter H */
236 #define URCCR 0x167 /* Underrun Counter Ctl Reg */
237 #define RECNTL 0x168 /* Rx EOM Counter L */
238 #define RECNTM 0x169 /* Rx EOM Counter M */
239 #define RECNTH 0x16a /* Rx EOM Counter H */
240 #define RECCR 0x16b /* Rx EOM Counter Ctl Reg */
241 #define ORCNTL 0x16c /* Overrun Counter L */
242 #define ORCNTH 0x16d /* Overrun Counter H */
243 #define ORCCR 0x16f /* Overrun Counter Ctl Reg */
244 #define CECNTL 0x170 /* CRC Counter L */
245 #define CECNTH 0x171 /* CRC Counter H */
246 #define CECCR 0x173 /* CRC Counter Ctl Reg */
247 #define ABCNTL 0x174 /* Abort frame Counter L */
248 #define ABCNTH 0x175 /* Abort frame Counter H */
249 #define ABCCR 0x177 /* Abort frame Counter Ctl Reg */
250 #define SHCNTL 0x178 /* Short frame Counter L */
251 #define SHCNTH 0x179 /* Short frame Counter H */
252 #define SHCCR 0x17b /* Short frame Counter Ctl Reg */
253 #define RSCNTL 0x17c /* Residual bit Counter L */
254 #define RSCNTH 0x17d /* Residual bit Counter H */
255 #define RSCCR 0x17f /* Residual bit Counter Ctl Reg */
284 #define MD0_HDLC 0x80 /* Bit-sync HDLC mode */
440 #define IE0_UDRN 0x00008000 /* TX underrun MSCI interrupt enable */
441 #define IE0_CDCD 0x00000400 /* CD level change interrupt enable */