Lines Matching +full:rx +full:- +full:ts +full:- +full:max
4 * Copyright (C) 2008-2022, VMware, Inc. All Rights Reserved.
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23 * Maintained by: pv-drivers@vmware.com
56 VMXNET3_REG_RXPROD = 0x800, /* Rx Producer Index for ring 1 */
57 VMXNET3_REG_RXPROD2 = 0xA00 /* Rx Producer Index for ring 2 */
63 VMXNET3_REG_LB_RXPROD = 0x1400, /* Rx Producer Index for ring 1 */
64 VMXNET3_REG_LB_RXPROD2 = 0x1800, /* Rx Producer Index for ring 2 */
73 #define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */
129 * Little Endian layout of bitfields -
135 * Big Endian layout of bitfields -
262 u32 rqID:10; /* rx queue/ring ID */
274 u32 rqID:10; /* rx queue/ring ID */
284 u32 ts:1; /* Tag is stripped */ member
290 u32 ts:1; /* Tag is stripped */ member
396 /* Max size of a single tx buffer */
400 #define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \
403 /* max # of tx descs for a non-tso pkt */
405 /* max # of tx descs for a tso pkt */
408 /* Max size of a single rx buffer */
409 #define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1)
416 #define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1)
420 #define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1)
424 #define VMXNET3_TXDATA_DESC_SIZE_MASK (VMXNET3_TXDATA_DESC_SIZE_ALIGN - 1)
426 /* Rx Data Ring buffer size must be a multiple of 64 */
428 #define VMXNET3_RXDATA_DESC_SIZE_MASK (VMXNET3_RXDATA_DESC_SIZE_ALIGN - 1)
430 /* Max ring size */
457 #define VMXNET3_CDTYPE_RXCOMP 3 /* Rx Completion Descriptor */
458 #define VMXNET3_CDTYPE_RXCOMP_LRO 4 /* Rx Completion Descriptor for LRO */
474 u32 gosBits:2; /* 32-bit or 64-bit? */
476 u32 gosBits:2; /* 32-bit or 64-bit? */
539 __le32 rxRingSize[2]; /* # of rx desc */
540 __le32 compRingSize; /* # of rx comp desc */
544 __le16 rxDataRingDescSize; /* size of rx data ring buffer */
772 /* read-only region for device, read by dev in response to a SET cmd */
782 /* read-only region for device, read by dev in response to a SET cmd */