Lines Matching +full:big +full:- +full:endian +full:- +full:desc

4  * Copyright (C) 2008-2022, VMware, Inc. All Rights Reserved.
18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23  * Maintained by: pv-drivers@vmware.com
73 #define VMXNET3_REG_ALIGN       8	/* All registers are 8-byte aligned. */
129  *	Little Endian layout of bitfields -
135  *	Big Endian layout of bitfields -
141  *	Thus, le32_to_cpu on the dword will allow the big endian driver to read
143  *	bit fields written by big endian driver to format required by device.
399 /* # of tx desc needed for a tx buffer size */
400 #define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \
403 /* max # of tx descs for a non-tso pkt */
409 #define VMXNET3_MAX_RX_BUF_SIZE  ((1 << 14) - 1)
416 #define VMXNET3_RING_BA_MASK    (VMXNET3_RING_BA_ALIGN - 1)
420 #define VMXNET3_RING_SIZE_MASK  (VMXNET3_RING_SIZE_ALIGN - 1)
424 #define VMXNET3_TXDATA_DESC_SIZE_MASK  (VMXNET3_TXDATA_DESC_SIZE_ALIGN - 1)
428 #define VMXNET3_RXDATA_DESC_SIZE_MASK  (VMXNET3_RXDATA_DESC_SIZE_ALIGN - 1)
445  VMXNET3_ERR_NOEOP        = 0x80000000,  /* cannot find the EOP desc of a pkt */
474 	u32		gosBits:2;    /* 32-bit or 64-bit? */
476 	u32		gosBits:2;     /* 32-bit or 64-bit? */
508 	__le32		queueDescLen; /* queue desc. table len in bytes */
523 	__le32		txRingSize;   /* # of tx desc */
524 	__le32		dataRingSize; /* # of data desc */
525 	__le32		compRingSize; /* # of comp desc */
539 	__le32		rxRingSize[2];   /* # of rx desc */
540 	__le32		compRingSize;    /* # of rx comp desc */
772 	/* read-only region for device, read by dev in response to a SET cmd */
782 	/* read-only region for device, read by dev in response to a SET cmd */