Lines Matching refs:phydev
15 static bool genphy_c45_baset1_able(struct phy_device *phydev) in genphy_c45_baset1_able() argument
19 if (phydev->pma_extable == -ENODATA) { in genphy_c45_baset1_able()
20 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); in genphy_c45_baset1_able()
24 phydev->pma_extable = val; in genphy_c45_baset1_able()
27 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1); in genphy_c45_baset1_able()
34 static bool genphy_c45_pma_can_sleep(struct phy_device *phydev) in genphy_c45_pma_can_sleep() argument
38 stat1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1); in genphy_c45_pma_can_sleep()
49 int genphy_c45_pma_resume(struct phy_device *phydev) in genphy_c45_pma_resume() argument
51 if (!genphy_c45_pma_can_sleep(phydev)) in genphy_c45_pma_resume()
54 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in genphy_c45_pma_resume()
63 int genphy_c45_pma_suspend(struct phy_device *phydev) in genphy_c45_pma_suspend() argument
65 if (!genphy_c45_pma_can_sleep(phydev)) in genphy_c45_pma_suspend()
68 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in genphy_c45_pma_suspend()
78 int genphy_c45_pma_baset1_setup_master_slave(struct phy_device *phydev) in genphy_c45_pma_baset1_setup_master_slave() argument
82 switch (phydev->master_slave_set) { in genphy_c45_pma_baset1_setup_master_slave()
94 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); in genphy_c45_pma_baset1_setup_master_slave()
98 return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, in genphy_c45_pma_baset1_setup_master_slave()
107 int genphy_c45_pma_setup_forced(struct phy_device *phydev) in genphy_c45_pma_setup_forced() argument
112 if (phydev->duplex != DUPLEX_FULL) in genphy_c45_pma_setup_forced()
115 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); in genphy_c45_pma_setup_forced()
119 ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2); in genphy_c45_pma_setup_forced()
130 switch (phydev->speed) { in genphy_c45_pma_setup_forced()
132 if (genphy_c45_baset1_able(phydev)) in genphy_c45_pma_setup_forced()
165 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1); in genphy_c45_pma_setup_forced()
169 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2); in genphy_c45_pma_setup_forced()
173 if (genphy_c45_baset1_able(phydev)) { in genphy_c45_pma_setup_forced()
174 ret = genphy_c45_pma_baset1_setup_master_slave(phydev); in genphy_c45_pma_setup_forced()
179 return genphy_c45_an_disable_aneg(phydev); in genphy_c45_pma_setup_forced()
191 static int genphy_c45_baset1_an_config_aneg(struct phy_device *phydev) in genphy_c45_baset1_an_config_aneg() argument
202 switch (phydev->master_slave_set) { in genphy_c45_baset1_an_config_aneg()
221 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); in genphy_c45_baset1_an_config_aneg()
225 adv_l |= linkmode_adv_to_mii_t1_adv_l_t(phydev->advertising); in genphy_c45_baset1_an_config_aneg()
227 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L, in genphy_c45_baset1_an_config_aneg()
234 adv_m |= linkmode_adv_to_mii_t1_adv_m_t(phydev->advertising); in genphy_c45_baset1_an_config_aneg()
236 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M, in genphy_c45_baset1_an_config_aneg()
255 int genphy_c45_an_config_aneg(struct phy_device *phydev) in genphy_c45_an_config_aneg() argument
260 linkmode_and(phydev->advertising, phydev->advertising, in genphy_c45_an_config_aneg()
261 phydev->supported); in genphy_c45_an_config_aneg()
263 changed = genphy_config_eee_advert(phydev); in genphy_c45_an_config_aneg()
265 if (genphy_c45_baset1_able(phydev)) in genphy_c45_an_config_aneg()
266 return genphy_c45_baset1_an_config_aneg(phydev); in genphy_c45_an_config_aneg()
268 adv = linkmode_adv_to_mii_adv_t(phydev->advertising); in genphy_c45_an_config_aneg()
270 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, in genphy_c45_an_config_aneg()
279 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); in genphy_c45_an_config_aneg()
281 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, in genphy_c45_an_config_aneg()
303 int genphy_c45_an_disable_aneg(struct phy_device *phydev) in genphy_c45_an_disable_aneg() argument
307 if (genphy_c45_baset1_able(phydev)) in genphy_c45_an_disable_aneg()
310 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, in genphy_c45_an_disable_aneg()
323 int genphy_c45_restart_aneg(struct phy_device *phydev) in genphy_c45_restart_aneg() argument
327 if (genphy_c45_baset1_able(phydev)) in genphy_c45_restart_aneg()
330 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg, in genphy_c45_restart_aneg()
344 int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart) in genphy_c45_check_and_restart_aneg() argument
349 if (genphy_c45_baset1_able(phydev)) in genphy_c45_check_and_restart_aneg()
354 ret = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in genphy_c45_check_and_restart_aneg()
363 return genphy_c45_restart_aneg(phydev); in genphy_c45_check_and_restart_aneg()
380 int genphy_c45_aneg_done(struct phy_device *phydev) in genphy_c45_aneg_done() argument
385 if (genphy_c45_baset1_able(phydev)) in genphy_c45_aneg_done()
388 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in genphy_c45_aneg_done()
402 int genphy_c45_read_link(struct phy_device *phydev) in genphy_c45_read_link() argument
408 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { in genphy_c45_read_link()
409 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); in genphy_c45_read_link()
417 phydev->link = 0; in genphy_c45_read_link()
431 if (!phy_polling_mode(phydev) || !phydev->link) { in genphy_c45_read_link()
432 val = phy_read_mmd(phydev, devad, MDIO_STAT1); in genphy_c45_read_link()
439 val = phy_read_mmd(phydev, devad, MDIO_STAT1); in genphy_c45_read_link()
447 phydev->link = link; in genphy_c45_read_link()
458 static int genphy_c45_baset1_read_lpa(struct phy_device *phydev) in genphy_c45_baset1_read_lpa() argument
462 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT); in genphy_c45_baset1_read_lpa()
467 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising); in genphy_c45_baset1_read_lpa()
468 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, 0); in genphy_c45_baset1_read_lpa()
469 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, 0); in genphy_c45_baset1_read_lpa()
471 phydev->pause = 0; in genphy_c45_baset1_read_lpa()
472 phydev->asym_pause = 0; in genphy_c45_baset1_read_lpa()
477 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 1); in genphy_c45_baset1_read_lpa()
479 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_L); in genphy_c45_baset1_read_lpa()
483 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, val); in genphy_c45_baset1_read_lpa()
484 phydev->pause = val & MDIO_AN_T1_ADV_L_PAUSE_CAP ? 1 : 0; in genphy_c45_baset1_read_lpa()
485 phydev->asym_pause = val & MDIO_AN_T1_ADV_L_PAUSE_ASYM ? 1 : 0; in genphy_c45_baset1_read_lpa()
487 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_M); in genphy_c45_baset1_read_lpa()
491 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, val); in genphy_c45_baset1_read_lpa()
506 int genphy_c45_read_lpa(struct phy_device *phydev) in genphy_c45_read_lpa() argument
510 if (genphy_c45_baset1_able(phydev)) in genphy_c45_read_lpa()
511 return genphy_c45_baset1_read_lpa(phydev); in genphy_c45_read_lpa()
513 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in genphy_c45_read_lpa()
519 phydev->lp_advertising); in genphy_c45_read_lpa()
520 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); in genphy_c45_read_lpa()
521 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0); in genphy_c45_read_lpa()
522 phydev->pause = 0; in genphy_c45_read_lpa()
523 phydev->asym_pause = 0; in genphy_c45_read_lpa()
528 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, in genphy_c45_read_lpa()
532 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA); in genphy_c45_read_lpa()
536 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val); in genphy_c45_read_lpa()
537 phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0; in genphy_c45_read_lpa()
538 phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0; in genphy_c45_read_lpa()
541 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); in genphy_c45_read_lpa()
545 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val); in genphy_c45_read_lpa()
556 int genphy_c45_pma_baset1_read_master_slave(struct phy_device *phydev) in genphy_c45_pma_baset1_read_master_slave() argument
560 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; in genphy_c45_pma_baset1_read_master_slave()
561 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; in genphy_c45_pma_baset1_read_master_slave()
563 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL); in genphy_c45_pma_baset1_read_master_slave()
568 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; in genphy_c45_pma_baset1_read_master_slave()
569 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; in genphy_c45_pma_baset1_read_master_slave()
571 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; in genphy_c45_pma_baset1_read_master_slave()
572 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; in genphy_c45_pma_baset1_read_master_slave()
583 int genphy_c45_read_pma(struct phy_device *phydev) in genphy_c45_read_pma() argument
587 linkmode_zero(phydev->lp_advertising); in genphy_c45_read_pma()
589 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); in genphy_c45_read_pma()
595 phydev->speed = SPEED_10; in genphy_c45_read_pma()
598 phydev->speed = SPEED_100; in genphy_c45_read_pma()
601 phydev->speed = SPEED_1000; in genphy_c45_read_pma()
604 phydev->speed = SPEED_2500; in genphy_c45_read_pma()
607 phydev->speed = SPEED_5000; in genphy_c45_read_pma()
610 phydev->speed = SPEED_10000; in genphy_c45_read_pma()
613 phydev->speed = SPEED_UNKNOWN; in genphy_c45_read_pma()
617 phydev->duplex = DUPLEX_FULL; in genphy_c45_read_pma()
619 if (genphy_c45_baset1_able(phydev)) { in genphy_c45_read_pma()
620 val = genphy_c45_pma_baset1_read_master_slave(phydev); in genphy_c45_read_pma()
633 int genphy_c45_read_mdix(struct phy_device *phydev) in genphy_c45_read_mdix() argument
637 if (phydev->speed == SPEED_10000) { in genphy_c45_read_mdix()
638 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, in genphy_c45_read_mdix()
645 phydev->mdix = ETH_TP_MDI; in genphy_c45_read_mdix()
649 phydev->mdix = ETH_TP_MDI_X; in genphy_c45_read_mdix()
653 phydev->mdix = ETH_TP_MDI_INVALID; in genphy_c45_read_mdix()
673 int genphy_c45_pma_read_abilities(struct phy_device *phydev) in genphy_c45_pma_read_abilities() argument
677 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); in genphy_c45_pma_read_abilities()
678 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { in genphy_c45_pma_read_abilities()
679 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in genphy_c45_pma_read_abilities()
685 phydev->supported); in genphy_c45_pma_read_abilities()
688 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2); in genphy_c45_pma_read_abilities()
693 phydev->supported, in genphy_c45_pma_read_abilities()
697 phydev->supported, in genphy_c45_pma_read_abilities()
701 phydev->supported, in genphy_c45_pma_read_abilities()
705 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); in genphy_c45_pma_read_abilities()
710 phydev->supported, in genphy_c45_pma_read_abilities()
713 phydev->supported, in genphy_c45_pma_read_abilities()
716 phydev->supported, in genphy_c45_pma_read_abilities()
719 phydev->supported, in genphy_c45_pma_read_abilities()
722 phydev->supported, in genphy_c45_pma_read_abilities()
725 phydev->supported, in genphy_c45_pma_read_abilities()
729 phydev->supported, in genphy_c45_pma_read_abilities()
732 phydev->supported, in genphy_c45_pma_read_abilities()
736 phydev->supported, in genphy_c45_pma_read_abilities()
739 phydev->supported, in genphy_c45_pma_read_abilities()
743 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, in genphy_c45_pma_read_abilities()
749 phydev->supported, in genphy_c45_pma_read_abilities()
753 phydev->supported, in genphy_c45_pma_read_abilities()
758 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1); in genphy_c45_pma_read_abilities()
763 phydev->supported, in genphy_c45_pma_read_abilities()
766 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT); in genphy_c45_pma_read_abilities()
771 phydev->supported, in genphy_c45_pma_read_abilities()
786 int genphy_c45_baset1_read_status(struct phy_device *phydev) in genphy_c45_baset1_read_status() argument
791 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; in genphy_c45_baset1_read_status()
792 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; in genphy_c45_baset1_read_status()
794 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L); in genphy_c45_baset1_read_status()
798 cfg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M); in genphy_c45_baset1_read_status()
804 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; in genphy_c45_baset1_read_status()
806 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; in genphy_c45_baset1_read_status()
809 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_PREFERRED; in genphy_c45_baset1_read_status()
811 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_PREFERRED; in genphy_c45_baset1_read_status()
824 int genphy_c45_read_status(struct phy_device *phydev) in genphy_c45_read_status() argument
828 ret = genphy_c45_read_link(phydev); in genphy_c45_read_status()
832 phydev->speed = SPEED_UNKNOWN; in genphy_c45_read_status()
833 phydev->duplex = DUPLEX_UNKNOWN; in genphy_c45_read_status()
834 phydev->pause = 0; in genphy_c45_read_status()
835 phydev->asym_pause = 0; in genphy_c45_read_status()
837 if (phydev->autoneg == AUTONEG_ENABLE) { in genphy_c45_read_status()
838 ret = genphy_c45_read_lpa(phydev); in genphy_c45_read_status()
842 if (genphy_c45_baset1_able(phydev)) { in genphy_c45_read_status()
843 ret = genphy_c45_baset1_read_status(phydev); in genphy_c45_read_status()
848 phy_resolve_aneg_linkmode(phydev); in genphy_c45_read_status()
850 ret = genphy_c45_read_pma(phydev); in genphy_c45_read_status()
865 int genphy_c45_config_aneg(struct phy_device *phydev) in genphy_c45_config_aneg() argument
870 if (phydev->autoneg == AUTONEG_DISABLE) in genphy_c45_config_aneg()
871 return genphy_c45_pma_setup_forced(phydev); in genphy_c45_config_aneg()
873 ret = genphy_c45_an_config_aneg(phydev); in genphy_c45_config_aneg()
879 return genphy_c45_check_and_restart_aneg(phydev, changed); in genphy_c45_config_aneg()
885 int gen10g_config_aneg(struct phy_device *phydev) in gen10g_config_aneg() argument
891 int genphy_c45_loopback(struct phy_device *phydev, bool enable) in genphy_c45_loopback() argument
893 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, in genphy_c45_loopback()
909 int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable) in genphy_c45_fast_retrain() argument
914 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, in genphy_c45_fast_retrain()
917 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported)) { in genphy_c45_fast_retrain()
918 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, in genphy_c45_fast_retrain()
923 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_CTRL2, in genphy_c45_fast_retrain()
929 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, in genphy_c45_fast_retrain()