227 	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L,  in genphy_c45_baset1_an_config_aneg()
236 	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M,  in genphy_c45_baset1_an_config_aneg()
270 	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,  in genphy_c45_an_config_aneg()
281 	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,  in genphy_c45_an_config_aneg()
310 	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,  in genphy_c45_an_disable_aneg()
330 	return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg,  in genphy_c45_restart_aneg()
354 		ret = phy_read_mmd(phydev, MDIO_MMD_AN, reg);  in genphy_c45_check_and_restart_aneg()
388 	val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);  in genphy_c45_aneg_done()
409 		val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);  in genphy_c45_read_link()
462 	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT);  in genphy_c45_baset1_read_lpa()
479 	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_L);  in genphy_c45_baset1_read_lpa()
487 	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_M);  in genphy_c45_baset1_read_lpa()
513 	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);  in genphy_c45_read_lpa()
532 	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);  in genphy_c45_read_lpa()
541 	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);  in genphy_c45_read_lpa()
679 		val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);  in genphy_c45_pma_read_abilities()
766 			val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT);  in genphy_c45_pma_read_abilities()
794 	ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L);  in genphy_c45_baset1_read_status()
798 	cfg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M);  in genphy_c45_baset1_read_status()
918 		ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,  in genphy_c45_fast_retrain()
923 		ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_CTRL2,  in genphy_c45_fast_retrain()