Lines Matching refs:MDIO_MMD_VEND1
249 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_LTC_LOAD_CTRL, in _nxp_c45_ptp_gettimex64()
251 ts->tv_nsec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
253 ts->tv_nsec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
255 ts->tv_sec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
257 ts->tv_sec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
281 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_LTC_WR_NSEC_0, in _nxp_c45_ptp_settime64()
283 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_LTC_WR_NSEC_1, in _nxp_c45_ptp_settime64()
285 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_LTC_WR_SEC_0, in _nxp_c45_ptp_settime64()
287 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_LTC_WR_SEC_1, in _nxp_c45_ptp_settime64()
289 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_LTC_LOAD_CTRL, in _nxp_c45_ptp_settime64()
320 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_RATE_ADJ_SUBNS_0, in nxp_c45_ptp_adjfine()
327 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_RATE_ADJ_SUBNS_1, in nxp_c45_ptp_adjfine()
371 extts->tv_nsec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_extts()
373 extts->tv_nsec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_extts()
375 extts->tv_sec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_extts()
377 extts->tv_sec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_extts()
379 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EXT_TRG_TS_CTRL, in nxp_c45_get_extts()
390 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EGR_RING_CTRL, in nxp_c45_get_hwtxts()
392 reg = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EGR_RING_DATA_0); in nxp_c45_get_hwtxts()
400 hwts->sequence_id = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_hwtxts()
402 hwts->nsec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_hwtxts()
404 reg = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EGR_RING_DATA_3); in nxp_c45_get_hwtxts()
504 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_gpio_config()
522 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PTP_CONFIG, in nxp_c45_perout_enable()
524 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PTP_CONFIG, in nxp_c45_perout_enable()
554 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_perout_enable()
557 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_perout_enable()
563 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PTP_CONFIG, PPS_OUT_EN); in nxp_c45_perout_enable()
596 phy_clear_bits_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_extts_enable()
600 phy_set_bits_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_extts_enable()
763 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_EVENT_MSG_FILT, in nxp_c45_hwtstamp()
765 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_hwtstamp()
769 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_EVENT_MSG_FILT, in nxp_c45_hwtstamp()
771 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_PTP_CONTROL, in nxp_c45_hwtstamp()
779 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_hwtstamp()
782 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_hwtstamp()
809 { "phy_symbol_error_cnt", MDIO_MMD_VEND1,
811 { "phy_link_status_drop_cnt", MDIO_MMD_VEND1,
813 { "phy_link_availability_drop_cnt", MDIO_MMD_VEND1,
815 { "phy_link_loss_cnt", MDIO_MMD_VEND1,
817 { "phy_link_failure_cnt", MDIO_MMD_VEND1,
819 { "r_good_frame_cnt", MDIO_MMD_VEND1,
821 { "r_bad_frame_cnt", MDIO_MMD_VEND1,
823 { "r_rxer_frame_cnt", MDIO_MMD_VEND1,
825 { "rx_preamble_count", MDIO_MMD_VEND1,
827 { "tx_preamble_count", MDIO_MMD_VEND1,
829 { "rx_ipg_length", MDIO_MMD_VEND1,
831 { "tx_ipg_length", MDIO_MMD_VEND1,
870 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL, in nxp_c45_config_enable()
875 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_CONTROL, in nxp_c45_config_enable()
877 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL, in nxp_c45_config_enable()
879 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_INFRA_CONTROL, in nxp_c45_config_enable()
887 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL, in nxp_c45_start_op()
894 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_config_intr()
897 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_config_intr()
908 irq = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_IRQ_STATUS); in nxp_c45_handle_interrupt()
910 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_IRQ_ACK, in nxp_c45_handle_interrupt()
920 irq = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_PTP_IRQ_STATUS); in nxp_c45_handle_interrupt()
935 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL, in nxp_c45_soft_reset()
940 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, in nxp_c45_soft_reset()
948 return phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_CABLE_TEST, in nxp_c45_cable_test_start()
958 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_CABLE_TEST); in nxp_c45_cable_test_get_status()
985 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_CABLE_TEST, in nxp_c45_cable_test_get_status()
1061 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_SIGNAL_QUALITY); in nxp_c45_get_sqi()
1103 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, ID_ENABLE); in nxp_c45_disable_delays()
1104 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, ID_ENABLE); in nxp_c45_disable_delays()
1117 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, in nxp_c45_set_delays()
1120 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, in nxp_c45_set_delays()
1127 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, in nxp_c45_set_delays()
1130 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, in nxp_c45_set_delays()
1179 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_ABILITIES); in nxp_c45_set_phy_mode()
1188 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1199 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1212 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1220 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1228 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1236 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1261 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 1); in nxp_c45_config_init()
1262 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 2); in nxp_c45_config_init()
1264 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONFIG, in nxp_c45_config_init()
1267 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_LINK_DROP_COUNTER, in nxp_c45_config_init()
1269 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_PREAMBLE_COUNT, in nxp_c45_config_init()
1271 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TX_PREAMBLE_COUNT, in nxp_c45_config_init()
1273 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_IPG_LENGTH, in nxp_c45_config_init()
1275 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TX_IPG_LENGTH, in nxp_c45_config_init()
1284 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PTP_CLK_PERIOD, in nxp_c45_config_init()
1286 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_HW_LTC_LOCK_CTRL, in nxp_c45_config_init()
1288 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_TS_INSRT_CTRL, in nxp_c45_config_init()
1290 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_FUNC_ENABLES, in nxp_c45_config_init()
1315 ptp_ability = phy_read_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_probe()