62 static u32 vsc85xx_ts_read_csr(struct phy_device *phydev, enum ts_blk blk,  in vsc85xx_ts_read_csr()  argument
70 	switch (blk) {  in vsc85xx_ts_read_csr()
106 static void vsc85xx_ts_write_csr(struct phy_device *phydev, enum ts_blk blk,  in vsc85xx_ts_write_csr()  argument
117 		    blk == PROCESSOR;  in vsc85xx_ts_write_csr()
120 	switch (blk) {  in vsc85xx_ts_write_csr()
291 static int vsc85xx_ts_disable_flows(struct phy_device *phydev, enum ts_blk blk)  in vsc85xx_ts_disable_flows()  argument
295 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_NXT_COMP, 0);  in vsc85xx_ts_disable_flows()
296 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_UDP_CHKSUM,  in vsc85xx_ts_disable_flows()
298 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP2_NXT_PROT_NXT_COMP, 0);  in vsc85xx_ts_disable_flows()
299 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP2_NXT_PROT_UDP_CHKSUM,  in vsc85xx_ts_disable_flows()
301 	vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_MPLS_COMP_NXT_COMP, 0);  in vsc85xx_ts_disable_flows()
302 	vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT, 0);  in vsc85xx_ts_disable_flows()
303 	vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH2_NTX_PROT, 0);  in vsc85xx_ts_disable_flows()
306 		vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(i),  in vsc85xx_ts_disable_flows()
308 		vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP2_FLOW_ENA(i),  in vsc85xx_ts_disable_flows()
310 		vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(i),  in vsc85xx_ts_disable_flows()
312 		vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH2_FLOW_ENA(i),  in vsc85xx_ts_disable_flows()
314 		vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_MPLS_FLOW_CTRL(i),  in vsc85xx_ts_disable_flows()
320 		vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_ENA(i), 0);  in vsc85xx_ts_disable_flows()
321 		vsc85xx_ts_write_csr(phydev, blk,  in vsc85xx_ts_disable_flows()
323 		vsc85xx_ts_write_csr(phydev, blk,  in vsc85xx_ts_disable_flows()
325 		vsc85xx_ts_write_csr(phydev, blk,  in vsc85xx_ts_disable_flows()
327 		vsc85xx_ts_write_csr(phydev, blk,  in vsc85xx_ts_disable_flows()
329 		vsc85xx_ts_write_csr(phydev, blk,  in vsc85xx_ts_disable_flows()
331 		vsc85xx_ts_write_csr(phydev, blk,  in vsc85xx_ts_disable_flows()
333 		vsc85xx_ts_write_csr(phydev, blk,  in vsc85xx_ts_disable_flows()
335 		vsc85xx_ts_write_csr(phydev, blk,  in vsc85xx_ts_disable_flows()
337 		vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_OAM_PTP_FLOW_ENA(i),  in vsc85xx_ts_disable_flows()
505 static int vsc85xx_ptp_cmp_init(struct phy_device *phydev, enum ts_blk blk)  in vsc85xx_ptp_cmp_init()  argument
517 		vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_ENA(i),  in vsc85xx_ptp_cmp_init()
521 		val = vsc85xx_ts_read_csr(phydev, blk,  in vsc85xx_ptp_cmp_init()
524 		vsc85xx_ts_write_csr(phydev, blk,  in vsc85xx_ptp_cmp_init()
527 		vsc85xx_ts_write_csr(phydev, blk,  in vsc85xx_ptp_cmp_init()
531 		vsc85xx_ts_write_csr(phydev, blk,  in vsc85xx_ptp_cmp_init()
539 static int vsc85xx_eth_cmp1_init(struct phy_device *phydev, enum ts_blk blk)  in vsc85xx_eth_cmp1_init()  argument
545 	vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NXT_PROT_TAG, 0);  in vsc85xx_eth_cmp1_init()
546 	vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT_VLAN_TPID,  in vsc85xx_eth_cmp1_init()
549 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0),  in vsc85xx_eth_cmp1_init()
551 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_MATCH_MODE(0),  in vsc85xx_eth_cmp1_init()
553 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ADDR_MATCH1(0), 0);  in vsc85xx_eth_cmp1_init()
554 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ADDR_MATCH2(0), 0);  in vsc85xx_eth_cmp1_init()
555 	vsc85xx_ts_write_csr(phydev, blk,  in vsc85xx_eth_cmp1_init()
557 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_VLAN_TAG1(0), 0);  in vsc85xx_eth_cmp1_init()
558 	vsc85xx_ts_write_csr(phydev, blk,  in vsc85xx_eth_cmp1_init()
561 	val = vsc85xx_ts_read_csr(phydev, blk,  in vsc85xx_eth_cmp1_init()
565 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_MATCH_MODE(0),  in vsc85xx_eth_cmp1_init()
571 static int vsc85xx_ip_cmp1_init(struct phy_device *phydev, enum ts_blk blk)  in vsc85xx_ip_cmp1_init()  argument
577 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MATCH2_UPPER,  in vsc85xx_ip_cmp1_init()
580 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MASK2_UPPER,  in vsc85xx_ip_cmp1_init()
582 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MATCH2_LOWER,  in vsc85xx_ip_cmp1_init()
584 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MASK2_LOWER, 0);  in vsc85xx_ip_cmp1_init()
586 	val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0));  in vsc85xx_ip_cmp1_init()
589 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0), val);  in vsc85xx_ip_cmp1_init()
592 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_UPPER(0), 0);  in vsc85xx_ip_cmp1_init()
593 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_UPPER(0), 0);  in vsc85xx_ip_cmp1_init()
594 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_UPPER_MID(0),  in vsc85xx_ip_cmp1_init()
596 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_UPPER_MID(0),  in vsc85xx_ip_cmp1_init()
598 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_LOWER_MID(0),  in vsc85xx_ip_cmp1_init()
600 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_LOWER_MID(0),  in vsc85xx_ip_cmp1_init()
602 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_LOWER(0), 0);  in vsc85xx_ip_cmp1_init()
603 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_LOWER(0), 0);  in vsc85xx_ip_cmp1_init()
605 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_IP_CHKSUM_SEL, 0);  in vsc85xx_ip_cmp1_init()
780 static int vsc85xx_eth1_next_comp(struct phy_device *phydev, enum ts_blk blk,  in vsc85xx_eth1_next_comp()  argument
785 	val = vsc85xx_ts_read_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT);  in vsc85xx_eth1_next_comp()
788 	vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT, val);  in vsc85xx_eth1_next_comp()
792 	vsc85xx_ts_write_csr(phydev, blk,  in vsc85xx_eth1_next_comp()
798 static int vsc85xx_ip1_next_comp(struct phy_device *phydev, enum ts_blk blk,  in vsc85xx_ip1_next_comp()  argument
801 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_NXT_COMP,  in vsc85xx_ip1_next_comp()
808 static int vsc85xx_ts_ptp_action_flow(struct phy_device *phydev, enum ts_blk blk, u8 flow, enum ptp…  in vsc85xx_ts_ptp_action_flow()  argument
814 	vsc85xx_ts_write_csr(phydev, blk,  in vsc85xx_ts_ptp_action_flow()
826 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_PTP_ACTION(flow),  in vsc85xx_ts_ptp_action_flow()
841 	vsc85xx_ts_write_csr(phydev, blk,  in vsc85xx_ts_ptp_action_flow()
847 static int vsc85xx_ptp_conf(struct phy_device *phydev, enum ts_blk blk,  in vsc85xx_ptp_conf()  argument
858 		if (blk == INGRESS)  in vsc85xx_ptp_conf()
859 			vsc85xx_ts_ptp_action_flow(phydev, blk, msgs[i],  in vsc85xx_ptp_conf()
863 			vsc85xx_ts_ptp_action_flow(phydev, blk, msgs[i],  in vsc85xx_ptp_conf()
866 			vsc85xx_ts_ptp_action_flow(phydev, blk, msgs[i],  in vsc85xx_ptp_conf()
869 		val = vsc85xx_ts_read_csr(phydev, blk,  in vsc85xx_ptp_conf()
874 		vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_ENA(i),  in vsc85xx_ptp_conf()
881 static int vsc85xx_eth1_conf(struct phy_device *phydev, enum ts_blk blk,  in vsc85xx_eth1_conf()  argument
893 		vsc85xx_ts_write_csr(phydev, blk,  in vsc85xx_eth1_conf()
895 		vsc85xx_ts_write_csr(phydev, blk,  in vsc85xx_eth1_conf()
900 		vsc85xx_ts_write_csr(phydev, blk,  in vsc85xx_eth1_conf()
902 		vsc85xx_ts_write_csr(phydev, blk,  in vsc85xx_eth1_conf()
906 	val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0));  in vsc85xx_eth1_conf()
910 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0), val);  in vsc85xx_eth1_conf()
915 static int vsc85xx_ip1_conf(struct phy_device *phydev, enum ts_blk blk,  in vsc85xx_ip1_conf()  argument
920 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_IP1_MODE,  in vsc85xx_ip1_conf()
928 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_IP_MATCH1,  in vsc85xx_ip1_conf()
932 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_OFFSET2,  in vsc85xx_ip1_conf()
935 	val = vsc85xx_ts_read_csr(phydev, blk,  in vsc85xx_ip1_conf()
947 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_UDP_CHKSUM,  in vsc85xx_ip1_conf()
950 	val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0));  in vsc85xx_ip1_conf()
955 	vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0), val);  in vsc85xx_ip1_conf()