703 int phy_base_read(struct phy_device *phydev, u32 regnum)  in phy_base_read()  function
748 		val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);  in vsc85xx_csr_read()
756 	val_l = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_17);  in vsc85xx_csr_read()
759 	val_h = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_18);  in vsc85xx_csr_read()
807 		val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);  in vsc85xx_csr_write()
841 		reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD);  in vsc8584_cmd()
903 	reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);  in vsc8584_micro_assert_reset()
910 	reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);  in vsc8584_micro_assert_reset()
916 	reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);  in vsc8584_micro_assert_reset()
924 	reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);  in vsc8584_micro_assert_reset()
951 	*crc = phy_base_read(phydev, MSCC_PHY_VERIPHY_CNTL_2);  in vsc8584_get_fw_crc()
1006 	reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1));  in vsc8574_is_serdes_init()
1012 	reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1));  in vsc8574_is_serdes_init()
1018 	reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);  in vsc8574_is_serdes_init()
1024 	reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);  in vsc8574_is_serdes_init()
1115 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);  in vsc8574_config_pre_init()
1135 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);  in vsc8574_config_pre_init()
1155 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);  in vsc8574_config_pre_init()
1162 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);  in vsc8574_config_pre_init()
1374 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);  in vsc8584_config_pre_init()
1380 	reg = phy_base_read(phydev,  MSCC_PHY_BYPASS_CONTROL);  in vsc8584_config_pre_init()
1397 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);  in vsc8584_config_pre_init()
1405 	reg = phy_base_read(phydev, MSCC_PHY_TR_MSB);  in vsc8584_config_pre_init()
1426 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);  in vsc8584_config_pre_init()
1433 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);  in vsc8584_config_pre_init()
1487 	reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);  in vsc8584_config_pre_init()
1569 	val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);  in vsc8584_config_host_serdes()
1634 	val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);  in vsc8574_config_host_serdes()
1907 	val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);  in vsc8514_config_host_serdes()
1941 	val = phy_base_read(phydev, MSCC_INT_MEM_CNTL);  in vsc8514_config_host_serdes()
1993 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);  in vsc8514_config_pre_init()
1999 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);  in vsc8514_config_pre_init()
2010 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);  in vsc8514_config_pre_init()
2016 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);  in vsc8514_config_pre_init()
2041 	reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);  in vsc8514_config_pre_init()